CN108573948B

CN108573948B - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN108573948B
Application number: CN201710146537.2A
Authority: CN
Inventors: 黄凯易; 简育生; 叶达勋
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2017-03-13
Filing date: 2017-03-13
Publication date: 2020-04-07
Anticipated expiration: 2037-03-13
Also published as: CN108573948A

Abstract

A semiconductor component comprises two windings. The first winding is substantially located in a first metal layer of a semiconductor structure, and comprises: a first external coil; a first inner coil; and a first bridging structure located within the range substantially surrounded by the first inner coil for connecting the first outer coil and the first inner coil. The second winding is substantially located in a second metal layer of the semiconductor structure, and comprises: a second external coil; a second inner coil; and a second bridging structure located within the range substantially surrounded by the second inner coil for connecting the second outer coil and the second inner coil. The first bridging structure is substantially located at the second metal layer of the semiconductor structure, and the second bridging structure is substantially located at the first metal layer of the semiconductor structure.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present invention relates to semiconductor devices, and more particularly to transformers and balanced-unbalanced transformers.

Background

Inductors, transformers, and balanced-to-unbalanced (balun) transformers are important components of rf integrated circuits for single-ended-to-differential signal conversion, signal coupling, impedance matching, etc. As integrated circuits (ics) are developed into System on Chip (SoC), integrated inductors (inductors) and integrated transformers (transformers) have gradually replaced conventional discrete devices and are widely used in radio frequency integrated circuits. However, since the metal layers with low resistance are rare in the semiconductor structure and the passive devices (such as inductors, transformers and baluns) in the integrated circuit usually occupy a large chip area, it is an important issue to improve the utilization of the metal layers with low resistance and reduce the area of the passive devices while maintaining the characteristics of the devices (such as inductance, quality factor (Q) and coupling coefficient (K)).

Disclosure of Invention

In view of the deficiencies of the prior art, it is an object of the present invention to provide a semiconductor device having a small area and good characteristics.

The invention discloses a semiconductor device, which comprises a first winding and a second winding. The first winding, substantially located in a first metal layer of a semiconductor structure, includes: a first external coil; a first inner coil located within a first range substantially surrounded by the first outer coil; and a first bridging structure located within a second range substantially surrounded by the first inner coil for connecting the first outer coil and the first inner coil. The second winding, substantially located in a second metal layer of the semiconductor structure, includes: a second external coil; a second inner coil located within a third range substantially surrounded by the second outer coil; and a second bridging structure located within a fourth range substantially surrounded by the second inner coil for connecting the second outer coil and the second inner coil. The first bridging structure is substantially located at the second metal layer of the semiconductor structure, and the second bridging structure is substantially located at the first metal layer of the semiconductor structure.

The present invention further discloses a semiconductor device, substantially symmetrical to a symmetry axis, comprising a first winding and a second winding. The first winding, having a first end, a second end and a third end, substantially located in a first metal layer of a semiconductor structure, comprises: a first external coil, wherein the first terminal and the second terminal are located on the first external coil; a first inner coil located within a first range substantially surrounded by the first outer coil; and a center tap forming the third end and substantially located in a second metal layer of the semiconductor structure, wherein the center tap extends from a second range substantially surrounded by the first inner coil to outside the first range and is symmetrical to the axis of symmetry. The second winding, having a fourth terminal and a fifth terminal, substantially located in the first metal layer of the semiconductor structure, includes: a second external coil, wherein the fourth terminal and the fifth terminal are located on the second external coil; and a second inner coil located within a third range substantially surrounded by the second outer coil.

The present invention further discloses a semiconductor device, which is fabricated on a three-layer metal layer in a semiconductor structure, and comprises a first winding, a second winding and a third winding. The first winding includes: a first external coil located on a first metal layer; a first inner coil disposed in the first metal layer and within a substantially enclosed area of the first outer coil; and a first bridging structure located on a second metal layer for connecting the first external coil and the first internal coil. The second winding includes: a second outer coil located on the first metal layer; a second inner coil disposed in the first metal layer and within a substantially enclosed area of the second outer coil; and a second bridging structure located on the second metal layer for connecting the second external coil and the second internal coil. The third winding, substantially overlapping the first winding or the second winding, comprises: a third external coil located on a third metal layer; a third inner coil disposed in the third metal layer and within a substantially enclosed area of the third outer coil; and a third bridging structure located on the first metal layer or the second metal layer for connecting the third external coil and the third internal coil. The third bridging structure and the metal wire connected with the third bridging structure form a reverse-U-shaped structure together.

The semiconductor element of the invention occupies a small number of metal layers, so most of the metal wire segments can be manufactured in the metal layer with lower resistance in the semiconductor structure, and better element characteristics can be obtained. Compared with the prior art, the semiconductor element is simpler to manufacture and has better element characteristics.

The features, implementations and functions of the present invention will be described in detail with reference to the drawings.

Drawings

FIG. 1 is a block diagram of one embodiment of a semiconductor device of the present invention;

fig. 2 is a top view of the semiconductor device 100;

FIG. 3 is a block diagram of another embodiment of a semiconductor device of the present invention;

fig. 4 is a top view of the semiconductor device 200;

fig. 5A to 5B respectively show the distribution of metal line segments of the semiconductor device 200 in the lower metal layer and the upper metal layer;

FIGS. 6A-6B are block diagrams of another embodiment of a semiconductor device according to the present invention;

FIG. 7 is a block diagram of another embodiment of a semiconductor device of the present invention; and

fig. 8 is a top view of the semiconductor device 400.

[ notation ] to show

100. 200, 300, 400: a semiconductor element;

111a to 111c, 121a to 121c, 211a to 211b, 221a to 221b, 311a to 311c, 321a to 321b, 411a to 411 c: an endpoint;

110. 120, 210, 220, 410: a winding;

112 to 114, 115a, 115b, 122 to 124, 125a, 125b, 218a, 218b, 312 to 315, 412 to 414: a metal wire segment;

115. 125, 215, 218, 415, 418: a bridging structure;

116. 117, 126, 127, 216, 217, 316, 317, 416, 417: a range;

319: a center tap;

330: an axis of symmetry.

Detailed Description

The technical terms in the following description refer to the conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.

Fig. 1 is a structural diagram of an embodiment of a semiconductor device of the present invention. The semiconductor device 100 may be used as a transformer or a balun transformer, and includes a winding 110 and a winding 120. The winding 110 includes terminals 111 a-111 c (111c is the terminal of the center tap of the winding 110), wire segments 112-114, and a bridging structure 115. The bridging structure 115 includes

metal line segments

115a and 115 b. The strapping structure 115 is substantially at a first metal Layer (shown in light gray, e.g., a Re-Distribution Layer (RDL)) of the semiconductor structure. In addition to the

Metal line segments

115a and 115b, the winding 110 is located on a second Metal layer (indicated in dark gray, such as an Ultra Thick Metal (UTM) layer) of the semiconductor structure, that is, the winding 110 is substantially located on the second Metal layer. Similarly, winding 120 includes terminals 121 a-121 c (121c is the terminal of the center tap of winding 120), wire segments 122-124, and bridging structure 125. The bridging structure 125 includes

metal line segments

125a and 125 b. The bridging structure 125 is substantially located in the second metal layer of the semiconductor structure. The winding 120 is located in the first metal layer of the semiconductor structure except for the

metal wire segments

125a and 125b, that is, the winding 120 is substantially located in the first metal layer. Both

windings

110 and 120 are symmetrical structures (each symmetrical to the extension of the center tap). The metal segments 115a (115 b) of the cross-over structure 115 and the metal segments connected thereto form a n-shaped structure, and the two

metal segments

115a and 115b are substantially parallel.

The

wire segments

112 and 113 form the outer coil of the winding 110, and the wire segments 114 form the inner coil of the winding 110. The inner coil is located within a range 116 substantially enclosed by the outer coil. The bridging structure 115 is located within a substantially enclosed region 117 of the inner coil for connecting the outer coil and the inner coil. In detail, the metal line segment 115a connects the

metal line segments

112 and 114 Through a Via structure, Via array or Through-Silicon Via (TSV) on the Through position; the metal line segment 115b connects the

metal line segments

113 and 114. Similarly, for winding 120,

wire segments

122 and 123 form the outer coil of winding 120, and wire segments 124 form the inner coil of winding 120. The inner coil is located within a range 126 substantially enclosed by the outer coil. The bridging structure 125 is located within a substantially enclosed area 127 of the inner coil for connecting the outer coil and the inner coil. In detail, the metal line segment 125a connects the

metal line segments

122 and 124; metal line segment 125b connects

metal line segments

123 and 124.

A top view of the semiconductor element 100 is shown in fig. 2, with the winding 110 substantially overlapping the winding 120. In detail, the winding 110 overlaps with both outer coils of the winding 120, and both inner coils overlap. The vertical coupling of the magnetic fields of the

windings

110 and 120 is perpendicular to the first or second metal layer, i.e. perpendicular to the plane of the

windings

110 or 120, so that the semiconductor device 100 forms a stacked transformer or a balanced-unbalanced transformer, i.e. one of the

windings

110 and 120 is used as the primary coil and the other one is used as the secondary coil. As can be seen from fig. 2, the semiconductor device 100 only occupies two metal layers of the semiconductor structure, so that the semiconductor device 100 is not only more easily implemented (especially suitable for integrated passive device (integrated passive device) process, which includes at most three metal layers), but also all metal lines can be formed on the RDL and UTM layers with lower resistance in the semiconductor structure, so that the semiconductor device 100 has a high coupling coefficient. In addition, the

windings

110 and 120 themselves have excellent symmetry. When the winding 110 (or 120) is used as an inductance element (including two sensing units, one of which has the

terminals

111a and 111c as its two ends and includes the left half of the metal segment 112, the metal segment 115a, and the metal segment 114, and the other of which has the

terminals

111b and 111c as its two ends and includes the right half of the metal segment 113, the metal segment 115b, and the metal segment 114), the inductance characteristics of the two sensing units are almost identical.

Fig. 3 is a structural diagram of another embodiment of the semiconductor device of the present invention. The semiconductor device 200 is similar to the semiconductor device 100, except that the semiconductor device 200 includes three

windings

210 and 220, respectively, and thus two bridging structures. Taking winding 210 as an example, crossover 215 is located within a region 217 substantially enclosed by the inner coil, and crossover 218 is located outside a region 216 substantially enclosed by the outer coil. The winding 220 has a similar structure and will not be described in detail. A top view of semiconductor device 200 is shown in fig. 4, where winding 210 substantially overlaps winding 220. The semiconductor device 200 has two terminals 211a and 211b as one of the output port and the input port, and two

terminals

221a and 221b as the other, and the center taps of the

windings

210 and 220 may be grounded, for example. The input/output ports are formed at the outer coils of the

windings

210 and 220. As shown, the distance between the two ends of the I/O port is greater than the length of the two metal segments of the cross-over structure (e.g., the distance between the

ends

221a and 221b is greater than the length of the

metal segments

218a and 218 b).

Fig. 5A and 5B show the distribution of metal line segments of the semiconductor device 200 in the lower metal layer and the upper metal layer, respectively. As is apparent from the figure, the semiconductor device 200 of the present invention only requires two metal layers, and when the number of turns of the two windings is the same, the distribution of all the metal segments of one layer is turned over (by 180 degrees), and then the distribution of all the metal segments of the other layer is obtained. Specifically, FIG. 5A is flipped along the axis A-A' to obtain FIG. 5B; and vice versa. The axis a-a' is perpendicular to the center tap and divides the range surrounded by the inner and outer coils approximately equally. In other embodiments, the two windings of the semiconductor element of the invention may have different numbers of turns.

Because semiconductor device 100 (or 200) uses only two metal layers, it can be fabricated with low resistivity RDL and UTM layers in a semiconductor structure. When a large current needs to flow through the device (for example, in a power amplifier), the characteristics of the device can be improved because the low-resistance metal layer can withstand a high current and has a low parasitic resistance.

Fig. 6A and 6B are structural diagrams of another embodiment of a semiconductor device according to the present invention. Fig. 6A shows a laterally coupled planar transformer, which is located at substantially the same metal layer of the semiconductor structure (i.e., the remaining metal segments, except for the bridging structure and the center tap, are located at the metal layer shown in light gray), and is symmetrical about the axis of symmetry 330. The semiconductor element 300 is composed of two windings.

The first winding (indicated by the diagonal line segments) has

endpoints

311a, 311b, and 311c, where the endpoint 311c is the endpoint of the center tap 319 of the first winding. The center tap 319 is also symmetrical to the axis of symmetry 330. The first winding includes an outer coil (composed of the left half of the wire segment 312 and the wire segment 313) and at least one inner coil (composed of the right half of the wire segment 314 and the wire segment 315, for example). The

terminals

311a and 311b are located on the outer coil. The inner coil is located within a range 316 substantially enclosed by the outer coil. The center tap is fabricated in another metal layer (shown in dark grey) and extends from within range 317 substantially surrounded by the inner coil to outside range 316. The first winding in fact comprises two sensing cells, one of which has

terminals

311a and 311c as its two terminals and the other of which has

terminals

311b and 311c as its two terminals.

The second winding is located within the range 316 and has

ends

321a and 321 b. Similarly, the second winding has an outer coil and an inner coil, the inner coil being located within a range substantially surrounded by the outer coil. The

terminals

321a and 321b are located at the outer coil.

The semiconductor device 300 further includes a plurality of bridging structures (located on the symmetry axis 330, fabricated on the metal layer represented by dark gray) for connecting the outer coil and the inner coil of the winding, or two adjacent inner coils. The center tap 319 does not overlap the crossover structure.

Fig. 6B shows the center tap 319 separately. The center tap 319 is a closed polygonal (or circular) structure, symmetrical to the axis of symmetry 330. As shown in fig. 6A, the center tap 319 surrounds at least one jumper structure.

Fig. 7 is a structural view of another embodiment of the semiconductor device of the present invention. The semiconductor device 400 includes a semiconductor device 300 and a winding 410. Winding 410 is implemented in a third metal layer, which is different from the two metal layers used in semiconductor device 300. Winding 410 includes an outer coil (formed by wire segments 412 and 413) and at least one inner coil (formed by wire segments 414, for example).

Terminals

411a and 411b are located on the outer coil. The inner coil is located within a range 416 substantially enclosed by the outer coil. End 411c is the end of the center tap of winding 410. Winding 410 includes

crossover structures

415 and 418 for connecting the outer coil to the inner coil. The bridging structure 415 (or 418) comprises two metal line segments. The two metal line segments are formed on one of the two metal layers occupied by the semiconductor device 300. Thus, when semiconductor device 300 and winding 410 are stacked to form a semiconductor device 400 having three windings (a top view is shown in fig. 8), the device actually occupies only three metal layers in the semiconductor structure. In the present embodiment, the bridging structure 415 (or 418) is outside the range 416, however, in other embodiments, the bridging structure 415 (or 418) can be fabricated within the range 417.

When the semiconductor device 400 is used as a balun transformer, the combination of the two windings of the semiconductor device 300 can be used to convert a differential signal into a single-ended signal (e.g., applied to the output of an rf circuit), and the combination of one of the windings of the semiconductor device 300 and the winding 410 can be used to convert a single-ended signal into a differential signal (e.g., applied to the input of an rf circuit). In detail, when the semiconductor device 400 is applied to the output terminal of the rf circuit, a differential signal is inputted from the two

terminals

311a and 311b of the first winding and outputted from the terminal 321a of the second winding (the

terminals

311c and 321b are grounded); when the semiconductor device 400 is applied to an input terminal of an rf circuit, a single-ended signal is input from the terminal 321a and output from the two

terminals

411a and 411b of the winding 410 (the

terminals

321b and 411c are grounded). That is, the semiconductor device 400 can be shared by the output and input of one rf circuit, and only occupies three metal layers.

It should be noted that the shapes, sizes, proportions and the like of the elements in the drawings are illustrative only, and are not intended to be limiting, since those skilled in the art can understand the present invention. Furthermore, although the embodiments of the present disclosure are described with reference to integrated transformers and integrated balanced-unbalanced transformers, the present disclosure is not limited thereto, and those skilled in the art can appropriately apply the present disclosure to other types of semiconductor devices according to the disclosure of the present disclosure.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

Claims

1. A semiconductor device, comprising:

a first winding substantially in a first metal layer of a semiconductor structure, comprising:

a first external coil;

a first inner coil located within a first range substantially surrounded by the first outer coil; and

a first bridging structure including a first metal line segment and a second metal line segment, the first metal line segment connecting a first end of the first outer coil and a first end of the first inner coil, the second metal line segment connecting a second end of the first outer coil and a second end of the first inner coil, the first metal line segment and the second metal line segment being located within a second range substantially surrounded by the first inner coil; and

a second winding substantially in a second metal layer of the semiconductor structure, comprising:

a second external coil;

a second inner coil located within a third range substantially surrounded by the second outer coil; and

a second bridging structure located within a fourth range substantially surrounded by the second inner coil for connecting the second outer coil and the second inner coil;

the first bridging structure is substantially located in the second metal layer of the semiconductor structure, and the second bridging structure is substantially located in the first metal layer of the semiconductor structure.

2. The semiconductor device as defined in claim 1, wherein the second strapping structure comprises a third metal line segment and a fourth metal line segment in the first metal layer.

3. The semiconductor device as defined in claim 1, wherein the first metal line segment and the second metal line segment are substantially parallel.

4. The semiconductor device as defined in claim 1, wherein the first metal line segment and the metal line segments connected thereto form a n-shape.

5. A semiconductor device substantially symmetrical about an axis of symmetry, comprising:

a first winding having a first end, a second end, and a third end, substantially in a first metal layer of a semiconductor structure, comprising:

a first external coil, wherein the first terminal and the second terminal are located on the first external coil;

a center tap forming the third end and located substantially in a second metal layer of the semiconductor structure, wherein the center tap extends outside the first range within a second range substantially surrounded by the first inner coil and is symmetrical to the axis of symmetry; and

a second winding having a fourth terminal and a fifth terminal, substantially in the first metal layer of the semiconductor structure, comprising:

a second external coil, wherein the fourth terminal and the fifth terminal are located on the second external coil; and

a second inner coil located within a third range substantially enclosed by the second outer coil.

6. The semiconductor device of claim 5, wherein the semiconductor device further comprises:

a first bridging structure substantially located in the second metal layer for connecting the first outer coil and the first inner coil; and

a second bridging structure substantially located in the second metal layer for connecting the second outer coil and the second inner coil;

wherein the center tap is symmetrical to the symmetry axis but does not overlap with the first bridging structure or the second bridging structure.

7. The semiconductor device as defined in claim 5, wherein the center tap is a closed polygon structure, the closed polygon structure being symmetrical to the symmetry axis and surrounding a fourth range.

8. The semiconductor device as defined in claim 5, further comprising:

a third winding substantially in a third metal layer of the semiconductor structure, comprising:

a third external coil;

a third inner coil disposed within a fourth range substantially enclosed by the third outer coil; and

a bridging structure located within a fifth range substantially surrounded by the third inner coil or located outside the fourth range for connecting the third outer coil and the third inner coil;

wherein the bridging structure is substantially located in the first metal layer or the second metal layer of the semiconductor structure.

9. The semiconductor device as claimed in claim 8, wherein the bridging structure and the metal segments connected thereto form a n-shape.

10. A semiconductor device, which is fabricated in a semiconductor structure with three metal layers, comprises:

a first winding, comprising:

a first external coil located on a first metal layer;

a first inner coil disposed in the first metal layer and within a substantially enclosed area of the first outer coil; and

a first bridging structure located on a second metal layer for connecting the first external coil and the first internal coil; a second winding, comprising:

a second outer coil located on the first metal layer;

a second inner coil disposed in the first metal layer and within a substantially enclosed area of the second outer coil; and

a second bridging structure located on the second metal layer for connecting the second external coil and the second internal coil; and

a third winding substantially overlapping the first winding or the second winding, comprising:

a third external coil located on a third metal layer;

a third inner coil disposed in the third metal layer and within a substantially enclosed area of the third outer coil; and

a third bridging structure located on the first metal layer or the second metal layer for connecting the third external coil and the third internal coil;

wherein, the third bridging structure and the metal wire connected with the third bridging structure form a structure like a reversed U.