CN108573677B - Control signal driving circuit and driving method and pixel circuit driving method - Google Patents
Control signal driving circuit and driving method and pixel circuit driving method Download PDFInfo
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- CN108573677B CN108573677B CN201710132445.9A CN201710132445A CN108573677B CN 108573677 B CN108573677 B CN 108573677B CN 201710132445 A CN201710132445 A CN 201710132445A CN 108573677 B CN108573677 B CN 108573677B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Engineering & Computer Science (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a control signal driving circuit and a driving method and a pixel circuit driving method, wherein the control signal driving circuit comprises a first transistor, a ninth transistor, a first capacitor and a second capacitor, wherein an external circuit provides a first clock signal, a second clock signal, a high power supply voltage, a low power supply voltage and an input signal to the control signal driving circuit, and finally outputs a control signal with a high level and an output signal with a low level; the control signal driving circuit is simple in structure, a small number of transistors and capacitors are adopted to achieve output of control signals, integration is facilitated, the yield of a screen body is improved, and the driving circuit is stable in work, and output stability of the control signals is improved.
Description
Technical Field
The invention relates to the field of flat panel display, in particular to a control signal driving circuit, a driving method and a pixel circuit driving method.
Background
Organic Light Emitting Displays (OLEDs) are classified into Passive Matrix (PMOLED) and Active Matrix (AMOLED) driving methods. An active organic light emitting display device (AMOLED) utilizes a Thin Film Transistor (TFT) in combination with a Capacitor (Capacitor) to store a signal, so as to control the brightness and gray scale expression of the OLED. Compared with a thin film transistor liquid crystal display (TFT-LCD) in the current mainstream flat panel display technology, the AMOLED display has the advantages of high contrast, wide viewing angle, low power consumption, thinner thickness and the like.
Different pixel circuits in a conventional organic light emitting display need different driving timing signals, for example, a 2T1C (2 thin film transistors and 1 capacitor) pixel circuit only needs one scanning (Scan) driving signal, and a general pixel compensation circuit, called as an mTnC (including m thin film transistors and n capacitors) pixel circuit, needs a plurality of scanning driving signals and a plurality of control signals, and the defects of the process are compensated by matching certain timings, so that the uniformity of the display of the screen is improved.
The conventional driving circuit for generating control signals is relatively complex IN structure, as shown IN fig. 1, which is a schematic structural diagram of a driving circuit for generating control signals IN the prior art, and includes 15 thin film transistors (M1 to M11 and M44, M55, M88 and M99) and 5 capacitors (C1 to C5), and also requires a plurality of signals, such as an input signal IN, a high power voltage signal VGH, a low power voltage signal VGL, three clock signals CK1, CK2 and CK3, a Reset signal Reset, a final output control signal, and output signals OUT1 and OUT1, as input signals of a next stage of driving circuit.
The driving circuit has a complex structure, and the number of thin film transistors and capacitors used is large, and the required input signals are also large, which easily causes instability of output signals. If the driving circuit is integrated in the screen body of the organic light emitting display, the driving circuit occupies too much area of the screen body, which affects the yield of the screen body and is not beneficial to saving the cost.
Therefore, it is an urgent technical problem to be solved by those skilled in the art to design a control signal driving circuit with a simple structure to provide a control signal to a pixel circuit.
Disclosure of Invention
The invention aims to provide a control signal driving circuit, a driving method and a pixel circuit driving method, which are used for simplifying the control signal driving circuit and providing stable control signals.
In order to achieve the above object, the present invention provides a control signal driving circuit, which includes first to ninth transistors, a first capacitor and a second capacitor, wherein,
the grid electrode of the first transistor and the grid electrode of the fourth transistor are connected to a first clock signal end, the first electrode of the first transistor is connected to an input signal end, and the second electrode of the first transistor and the grid electrode of the second transistor are connected to a first node;
the second electrode of the second transistor is connected to a second clock signal terminal; the first electrode of the second transistor, the grid electrode of the third transistor, the first electrode of the fifth transistor, the grid electrode of the sixth transistor, the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are connected to a second node;
a first electrode of the third transistor and a second electrode of the fourth transistor are connected to a gate electrode of the fifth transistor, and a second electrode of the third transistor, a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of the eighth transistor are connected to a first power supply voltage signal terminal;
a first electrode of the fourth transistor, a first electrode of the seventh transistor and a first electrode of the ninth transistor are connected to a second power supply voltage signal end; a first electrode of the sixth transistor, a second electrode of the seventh transistor, and a gate of the ninth transistor are connected to one end of the second capacitor, and a first electrode of the eighth transistor, a second electrode of the ninth transistor, and the other end of the second capacitor are connected to a control signal terminal;
the first capacitor is connected between the second node and the first node.
Optionally, the circuit further includes a tenth transistor and an eleventh transistor, a gate of the tenth transistor is connected to the first clock signal terminal, a first electrode of the tenth transistor is connected to the input signal terminal, a second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor, a gate of the eleventh transistor is connected to the second clock signal terminal, and a second electrode of the eleventh transistor is connected to the first node.
Optionally, the integrated circuit further includes a third capacitor and a fourth capacitor, one end of the third capacitor and one end of the fourth capacitor are connected to the first power voltage signal end, the other end of the third capacitor is connected to the second node, and the other end of the fourth capacitor is connected to the second electrode of the tenth transistor.
Optionally, the second node is connected to an output signal terminal.
Optionally, the first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode.
Optionally, the driving timing sequence of the driving circuit includes a first stage, a second stage and a third stage; in the first stage, the input signal and the first clock signal are at low level, and the second clock signal is at high level; in the second stage, the input signal and the first clock signal are at high level, the second clock signal is at low level, and a high-level control signal and a low-level output signal are output; in a third stage, the first clock signal is at a low level, the input signal and the second clock signal are at a high level, and a low-level control signal and a high-level output signal are output.
Optionally, in the second stage, the output signal is used as an input signal of a next stage control signal driving circuit.
Correspondingly, the present invention further provides a driving method of a control signal driving circuit, which generates a control signal by using the control signal driving circuit, including:
the first stage is as follows: the input signal end provides an input signal, and the voltage of the first node is low level;
and a second stage: the second clock signal is at a low level, the voltage of the first node is less than 2 times of a second power supply voltage, the output signal end outputs an output signal at the low level, and the control signal end outputs a control signal at a high level;
and a third stage: the first clock signal is at a low level, the input signal and the second clock signal are at a high level, the output signal end outputs an output signal at the high level, and the control signal end outputs a control signal at the high level.
Optionally, the output signal of the second stage is used as the input signal of the next stage control signal driving circuit.
Correspondingly, the invention also provides a driving method of the pixel circuit, which adopts the control signal driving circuit to provide the control signal.
Compared with the prior art, the control signal driving circuit, the driving method and the pixel circuit driving method simplify the structure of the control signal driving circuit, realize the output of the control signal by adopting a small number of transistors and capacitors, facilitate the realization of circuit integration, contribute to improving the yield of a screen body, and improve the working stability of the driving circuit and the output stability of the control signal.
Drawings
FIG. 1 is a schematic diagram of a control signal driving circuit in the prior art;
fig. 2 is a schematic structural diagram of a control signal driving circuit according to an embodiment of the present invention;
fig. 3 is a signal timing diagram of the control signal driving circuit shown in fig. 2.
Detailed Description
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
Fig. 2 is a schematic structural diagram of a control signal driving circuit according to an embodiment of the present invention, and as shown IN fig. 2, the present invention provides a control signal driving circuit, which includes a first transistor M1 to a ninth transistor M9, a first capacitor C1 and a second capacitor C2, wherein a gate of the first transistor M1 and a gate of the fourth transistor M4 are connected to a first clock signal terminal CLK1, a first electrode of the first transistor M1 is connected to an input signal terminal IN, and a second electrode of the first transistor M1 and a gate of the second transistor M2 are connected to a first node N; the second electrode of the second transistor M2 is connected to a second clock signal terminal CLK 2; the first electrode of the second transistor M2, the gate of the third transistor M3, the first electrode of the fifth transistor M5, the gate of the sixth transistor M6, the gate of the seventh transistor M7 and the gate of the eighth transistor M8 are connected to a second node M; a first electrode of the third transistor M3, a second electrode of the fourth transistor M4 and a gate electrode of the fifth transistor M5 are connected, and a second electrode of the third transistor M3, a second electrode of the fifth transistor M5, a second electrode of the sixth transistor M6 and a second electrode of the eighth transistor M8 are connected to a first power supply voltage signal terminal VGH; a first electrode of the fourth transistor M4, a first electrode of the seventh transistor M7 and a first electrode of the ninth transistor M9 are connected to a second power supply voltage signal terminal VGL; a first electrode of the sixth transistor M6, a second electrode of the seventh transistor M7, and a gate of the ninth transistor M9 are connected to one end of the second capacitor C2, and a first electrode of the eighth transistor M8, a second electrode of the ninth transistor M9, and the other end of the second capacitor C2 are connected to a control signal terminal EM; the first capacitor C1 is connected between the second node M and the first node N.
The control signal driving circuit further includes a tenth transistor M10 and an eleventh transistor M11, a gate of the tenth transistor M10 is connected to the first clock signal terminal CLK1, a first electrode of the tenth transistor M10 is connected to the input signal terminal IN, a second electrode of the tenth transistor M10 is connected to a first electrode of the eleventh transistor M11, a gate of the eleventh transistor M11 is connected to the second clock signal terminal CLK2, and a second electrode of the eleventh transistor M11 is connected to the first node N.
The control signal driving circuit further includes a third capacitor C3 and a fourth capacitor C4, wherein one end of the third capacitor C3 is connected to the first power voltage signal terminal VGH, and the other end of the third capacitor C3 is connected to the second node M. One end of the fourth capacitor C4 is connected to the first power voltage signal terminal VGH, and the other end of the fourth capacitor C4 is connected to the second electrode of the tenth transistor M10.
The input signal terminal IN provides an input signal IN, the first clock signal terminal CLK1 provides a first clock signal CLK1, the second clock signal terminal CLK2 provides a second clock signal CLK2, the first power supply voltage signal terminal VGH provides a high power supply voltage VGH, and the second power supply voltage signal terminal VGL provides a low power supply voltage VGL. One end of the first capacitor C1, the first electrode of the second transistor M2, the gate of the third transistor M3, the first electrode of the fifth transistor M5, the gate of the sixth transistor M6, the gate of the seventh transistor M7, and the gate of the eighth transistor M8 are connected to a second node M, which is connected to an output signal terminal OUT, to provide an output signal OUT. One end of the second capacitor C2, the first electrode of the eighth transistor M8, and the second electrode of the ninth transistor M9 are connected to each other and to the control signal terminal EM for outputting the control signal EM.
In this embodiment, the first electrode is a source, and the second electrode is a drain; or, the first electrode is a drain electrode, and the second electrode is a source electrode.
The driving timing of the control signal driving circuit comprises a first stage T1, a second stage T2 and a third stage T3; in the first phase T1, the input signal in and the first clock signal clk1 are low, and the second clock signal clk2 is high; in a second phase T2, the input signal in and the first clock signal clk1 are high, the second clock signal clk2 is low, and a high control signal em and a low output signal out are output; in the third stage T3, the first clock signal clk1 is low, the input signal in and the second clock signal clk2 are high, and a low control signal em1 and a high output signal out1 are output. The timing diagram of the control signal driving circuit shown in fig. 2 is shown in fig. 3, and it can be seen from the first stage T1 to the third stage T3 that the control signal em1 is a signal having a high level in the second stage to be supplied to the pixel circuit. The low-level output signal out1 outputted in the second stage T2 is used as the input signal of the next-stage control signal driving circuit, then in the third stage T3, the next-stage control signal driving circuit outputs a high-level control signal em2 and a low-level output signal out2 (not shown in the figure), the output signal out2 is used as the input signal of the next-stage control signal driving circuit, and so on, a plurality of control signals are generated, and the high levels of the plurality of control signals are shifted sequentially and provided to different pixel circuits in the display.
Correspondingly, the invention also provides a driving method of the control signal driving circuit, and the control signal driving circuit is adopted to generate the control signal. Referring to the signal timing diagram shown in fig. 3, the driving method of the control signal driving circuit includes:
first stage T1: inputting a voltage at a signal input end IN, wherein the voltage at the end N of the first node is at a low level;
second stage T2: the second clock signal clk2 is at a low level, the voltage at the N-terminal of the first node is less than 2 times of the low power supply voltage, the output signal terminal outputs an output signal at a low level, and the control signal terminal outputs a control signal at a high level;
third stage T3: the first clock signal is at a low level, the input signal and the second clock signal are at a high level, the output signal end outputs an output signal at the high level, and the control signal end outputs a control signal at the high level.
Specifically, in the first phase T1, the input signal in and the first clock signal clk1 are at a low level, the second clock signal clk2 is at a high level, and the voltage at the first node N end is at a low level VGL + | Vth | (where Vth is the threshold voltage of the first transistor M1).
In the second stage T2, the input signal in and the first clock signal clk1 are high, the second clock signal clk2 is low, the voltage at the first node N is less than 2Vgl, the output signal terminal OUT outputs the low-level output signal OUT, and the control signal terminal EM outputs the high-level control signal EM 1.
In the organic light emitting display device, a plurality of data lines and scan lines are disposed on a substrate, a plurality of pixel units arranged in a rectangular shape are formed by intersecting the data lines and the scan lines, a waveform provided by each row of scan lines sequentially turns on a switching transistor in each row of pixel units, and the data lines in the entire row are preferably used to simultaneously charge the pixel units in the entire row to respective required voltages, so as to display different gray scales. When each row is charged, the voltage is turned off by the scanning line, then the voltage is turned on by the scanning line of the next row, and the pixel units of the next row are charged and discharged by the same row of data lines, so that in sequence, when the pixel units of the last row are charged, a frame is formed, and then the charging is started from the first row. Each pixel unit is internally provided with a pixel circuit for charging and discharging the pixel unit, and a control signal needs to be provided when the charging and discharging are completed, so that the pixel circuit in each row needs to be provided with a control signal driving circuit for providing a control signal, therefore, the arrangement of the control signal driving circuit should correspond to a scanning line, a plurality of stages of control signal driving circuits are arranged on the substrate, and each stage of control signal driving circuit corresponds to one scanning line. The output signal OUT of the output signal terminal OUT of each stage of the control signal driving circuit at the second stage T2 is outputted as the input signal of the next stage of the control signal driving circuit, and the input signal of the first stage of the control signal driving circuit is provided as the input signal IN by the input signal terminal IN.
In the third stage T3, the first clock signal clk1 is at a low level, the input signal in and the second clock signal clk2 are at a high level, the output signal terminal OUT outputs the high-level output signal OUT, and the control signal terminal EM outputs the low-level control signal EM 1.
In the third stage T3, for the control signal driving circuit of the next stage, the output signal terminal OUT outputs the output signal OUT of the low level, and at the same time, the control signal terminal EM outputs the control signal EM2 of the high level, the control signal EM2 is supplied to the pixel circuit corresponding thereto, and the output signal OUT is used as the input signal of the control signal driving circuit of the further next stage.
And the control signal driving circuit of each stage sequentially provides control signals to the corresponding pixel circuit until one frame is finished, each control signal driving circuit provides the control signal at the moment, and then the control signal driving circuit of the first stage is started, wherein the working sequence of the control signal driving circuit is consistent with that of the pixel unit.
Correspondingly, the invention also provides a driving method of the pixel circuit, and the control signal driving circuit is adopted to provide the control signal. The control signal driving circuit provided by the invention has a simple structure, and when the control signal driving circuit is integrated in the screen body of the organic light-emitting display, the control signal driving circuit does not occupy too much area of the screen body, thereby being beneficial to reducing the cost. And, because the simple structure, then the work of circuit is more stable, can provide the stability of control signal.
In summary, the control signal driving circuit, the driving method and the pixel circuit driving method provided by the invention simplify the structure of the control signal driving circuit, realize the output of the control signal by adopting a small number of transistors and capacitors, facilitate the realization of integration, and contribute to improving the yield of the screen body, and the driving circuit has stable work and improves the output stability of the control signal.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (9)
1. A control signal driving circuit includes first to eleventh transistors, a first capacitor, and a second capacitor,
the grid electrode of the first transistor and the grid electrode of the fourth transistor are connected to a first clock signal end, the first electrode of the first transistor is connected to an input signal end, and the second electrode of the first transistor and the grid electrode of the second transistor are connected to a first node;
the second electrode of the second transistor is connected to a second clock signal end, and the first electrode of the second transistor, the grid electrode of the third transistor, the first electrode of the fifth transistor, the grid electrode of the sixth transistor, the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are connected to a second node;
a first electrode of the third transistor and a second electrode of the fourth transistor are connected to a gate electrode of the fifth transistor, and a second electrode of the third transistor, a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of the eighth transistor are connected to a first power supply voltage signal terminal;
a first electrode of the fourth transistor, a first electrode of the seventh transistor and a first electrode of the ninth transistor are connected to a second power supply voltage signal end;
a first electrode of the sixth transistor, a second electrode of the seventh transistor, and a gate of the ninth transistor are connected to one end of the second capacitor, and a first electrode of the eighth transistor, a second electrode of the ninth transistor, and the other end of the second capacitor are connected to a control signal terminal;
the first capacitor is connected between the second node and the first node;
a gate of the tenth transistor is connected to the first clock signal terminal, a first electrode of the tenth transistor is connected to the input signal terminal, a second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor, a gate of the eleventh transistor is connected to the second clock signal terminal, and a second electrode of the eleventh transistor is connected to the first node.
2. The control signal driving circuit according to claim 1, further comprising a third capacitor and a fourth capacitor, wherein one end of the third capacitor and one end of the fourth capacitor are connected to the first power supply voltage signal terminal, the other end of the third capacitor is connected to the second node, and the other end of the fourth capacitor is connected to the second electrode of the tenth transistor.
3. The control signal driving circuit according to claim 2, wherein the second node is connected to an output signal terminal.
4. The control signal driving circuit according to claim 3, wherein the first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode.
5. The control signal driving circuit according to any one of claims 1 to 4, wherein the driving timing of the driving circuit includes a first stage, a second stage, and a third stage; in the first stage, the input signal and the first clock signal are at low level, and the second clock signal is at high level; in the second stage, the input signal and the first clock signal are at high level, the second clock signal is at low level, and a high-level control signal and a low-level output signal are output; in a third stage, the first clock signal is at a low level, the input signal and the second clock signal are at a high level, and a low-level control signal and a high-level output signal are output.
6. The control signal driving circuit according to claim 5, wherein in the second stage, the output signal is used as an input signal of a control signal driving circuit of a next stage.
7. A driving method of a control signal driving circuit for generating a control signal using the control signal driving circuit according to any one of claims 1 to 6, comprising:
the first stage is as follows: the input signal end provides an input signal, and the voltage of the first node is low level;
and a second stage: the second clock signal is at a low level, the voltage of the first node is less than 2 times of a second power supply voltage, the output signal end outputs an output signal at the low level, and the control signal end outputs a control signal at a high level;
and a third stage: the first clock signal is at a low level, the input signal and the second clock signal are at a high level, the output signal end outputs an output signal at the high level, and the control signal end outputs a control signal at the high level.
8. The driving method of the control signal driving circuit according to claim 7, wherein the output signal of the second stage is used as the input signal of the control signal driving circuit of the next stage.
9. A driving method of a pixel circuit, wherein a control signal is provided by using the control signal driving circuit according to any one of claims 1 to 6.
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| CN201710132445.9A CN108573677B (en) | 2017-03-07 | 2017-03-07 | Control signal driving circuit and driving method and pixel circuit driving method |
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| JP4944689B2 (en) * | 2007-03-02 | 2012-06-06 | 三星モバイルディスプレイ株式會社 | Organic light emitting display and driving circuit thereof |
| KR100958023B1 (en) * | 2008-11-04 | 2010-05-17 | 삼성모바일디스플레이주식회사 | Organic Light emitting Display device |
| KR101804315B1 (en) * | 2010-12-06 | 2018-01-11 | 삼성디스플레이 주식회사 | Display device, and scan driving apparatus for the display device and driving method thereof |
| CN102857207B (en) * | 2012-07-25 | 2015-02-18 | 京东方科技集团股份有限公司 | Shift register unit, driving method thereof, grid driving device and display device |
| CN103021358B (en) * | 2012-12-07 | 2015-02-11 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving circuit and display device |
| CN104751769A (en) * | 2013-12-25 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driver and organic light emitting display employing same |
| CN104183219B (en) * | 2013-12-30 | 2017-02-15 | 昆山工研院新型平板显示技术中心有限公司 | Scanning drive circuit and organic light-emitting displayer |
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