CN108572872B - Resource management method based on FPGA reconfigurable technology - Google Patents

Resource management method based on FPGA reconfigurable technology Download PDF

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CN108572872B
CN108572872B CN201810193908.7A CN201810193908A CN108572872B CN 108572872 B CN108572872 B CN 108572872B CN 201810193908 A CN201810193908 A CN 201810193908A CN 108572872 B CN108572872 B CN 108572872B
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王国华
刘嵩
王帅
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Beihang University
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061Partitioning or combining of resources
    • G06F9/5066Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs

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Abstract

The invention relates to a resource management method based on FPGA reconfigurable technology, which comprises the following steps: 1. in the task scheduling process, when a new task comes, the new task is stored in a ready list, and meanwhile, the tasks in the delay list which are not configured successfully before are added into the ready list and are sequenced according to priority; 2. distributing the tasks in the ready list according to a sorting sequence, and judging whether a distribution area exists or not by comparing the maximum free area of the MER list with the task area information; 3. waiting for a task execution completion signal, and after the execution of a certain task is completed, clearing the task in the FPGA resource and updating the operation list and the MER list; the ready list can also monitor and compare the current time with the relative ending time of the tasks in the queue, and if the current time exceeds the relative ending time, the tasks are discarded; 4. and repeating the above operations until all tasks are executed or discarded.

Description

Resource management method based on FPGA reconfigurable technology
Technical Field
The invention relates to a resource management method based on an FPGA (field programmable gate array) reconfigurable technology, which is used for effectively scheduling and allocating hardware tasks in a reconfigurable system and particularly has an obvious effect of limiting resources on an FPGA chip.
Background
With the continuous improvement of electronic system technology, logic functions become more and more complex, and the design of internal chips is also developing towards large scale, multiple functions, high density and high complexity. However, no matter the logic function module is a sequential logic system or a combinational logic system, the functions are sequentially executed by time-sharing modules according to the task requirements of the system in the execution process. As such, large-scale electronic systems face the problem of inefficient use of resources. How to improve the resource utilization rate and realize the logic design with complex functions by using limited resources is the key point of current research, and the reconfigurable technology is developed on the background. The core idea of the reconfigurable technology is to realize time division multiplexing of resources and meet the application requirements of large-scale electronic design by dynamically configuring the resources. By dynamically configuring logic circuits of the FPGA during the running period of the FPGA, the time sequence function of a large-scale system can be realized by using less hardware logic resources. The technology can greatly improve the resource utilization rate of the embedded system based on the FPGA, improve the fault tolerance of the system, and reduce the damage rate of devices while reducing the power consumption. In the reconfigurable system, the primary task is to manage the reconfigurable hardware resources which change in real time and distribute the newly arrived reconfigurable tasks, search the idle area on the reconfigurable resources according to the parameters such as the area of the hardware tasks and the like, select an optimal position for the idle area, and effectively schedule according to the time parameter information of the hardware tasks, thereby realizing a reasonable execution sequence. Effective management of reconfigurable resources is a key for improving the performance of reconfigurable systems, so that a resource management technology is now a hot spot for research of many researchers, but the following defects exist in the current resource management technology: the hardware task generates extra fragments during distribution, and the next distribution is influenced; the storage structure of resource management is too complex, and the maintenance and merging process is very complicated; when multiple hardware tasks arrive at the same time, effective scheduling cannot be carried out; the utilization rate of resources is limited, and the space is further improved. On the basis, the invention provides a resource management method based on the FPGA reconfigurable technology, thereby overcoming the defects, further improving the resource utilization rate of the reconfigurable system and laying a foundation for the conversion and application of research results.
Disclosure of Invention
In order to improve the resource utilization efficiency of a reconfigurable system, reduce the fragmentation degree generated in the distribution process and solve the problem that a plurality of hardware tasks arrive at the same time, the invention provides a resource management method based on an FPGA reconfigurable technology.
As shown in fig. 1, a flowchart of specific execution steps of a resource management method based on the FPGA reconfigurable technology is shown. The technical scheme of the invention is as follows:
(1) in the task scheduling process, when a new task comes, the new task is stored in a ready list, meanwhile, the tasks in the delay list which are not configured successfully before are added into the ready list, and the priority ranking is performed, wherein the specific content of the priority ranking is as follows: the smaller the relative allocation deadline, the higher the task priority; if the relative distribution deadline is the same, the task priority is higher when the area is smaller; if the areas are the same, the task priority is higher the earlier the deadline is.
(2) And allocating the tasks in the ready list according to the sequencing order, and judging whether an allocation area exists or not by comparing the maximum free area of the MER list with the task area information. If the assignable areas exist, calculating a contact value according to an assignment algorithm, selecting an MER with the largest contact value for task assignment, adding the task into an operation list, updating an MER list, and assigning the next task; if the distributable area does not exist after the MER list is traversed, adding the task into the delay list to wait for next call; when a new task arrives, storing the task in a ready list, extracting the unfinished tasks previously stored in a delay list, sequencing the unfinished tasks according to the priority sequence of the tasks, and executing the execution steps to distribute the tasks;
the task allocation process in step (2) is explained in detail below by way of specific examples. Fig. 2 is a diagram of a specific configuration example, in which fig. 1 and 2 represent tasks T1 and T2 that have been allocated, respectively, and the two tasks have been allocated to reasonable positions of the FPGA by a resource management method. In FIG. 2, 4 and 5 represent the execution times of the assigned tasks T1 and T2, respectively, where the execution time of T1 is time1, and the execution time of T2 is time 2. From the locations of the assigned tasks T1 and T2, a maximum idle matrix may be generated. Fig. 2 shows the maximum idle matrices 1, 2 and 3 at 7, 8 and 9, respectively, where the maximum idle matrix refers to the maximum rectangle that the idle area can form, and the edges of the rectangle are the allocated tasks or FPGA edges. FIGS. 2, 3 and 6 represent the execution time3 for the unassigned tasks T3 and T3, respectively. The method comprises the steps of traversing the currently existing maximum idle matrix, placing unallocated tasks at the positions of four corners (upper left, lower left, upper right and lower right) of the maximum idle matrix, and respectively calculating the contact values of the tasks at the four corners of different maximum idle matrices (a specific calculation method of the contact values comprises the steps of firstly calculating the contact length between the unallocated tasks and configured tasks or FPGA edges, then calculating the residual time of the unallocated tasks, and finally multiplying the contact length and the residual time to obtain a product). By calculation, the position where the contact value is maximum is selected as the optimal position to be assigned, and the unassigned task is assigned to this position.
(3) And waiting for a task execution completion signal, and clearing the task in the FPGA resource and updating the operation list and the MER list after the execution of a certain task is completed. The ready list also monitors and compares the current time with the relative deadline of the task in the queue, and discards the task if the current time exceeds the relative deadline.
(4) And repeating the above operations until all tasks are executed or discarded.
The invention has the beneficial effects that:
(1) the resource management method provided by the invention can effectively improve the resource utilization rate of the reconfigurable system, can realize higher task acceptance rate under the condition of limited resources, reduces the waste of resources and reduces the cost required by the system.
(2) In the distribution process, the generation of fragments is reduced, the fragment degree is reduced, and the distribution effect is improved.
(3) Because the resource management method provided by the invention comprises the task scheduling part, the task can be effectively scheduled, the condition that a plurality of tasks arrive at the same time is solved, and the practicability of the method is improved.
(4) The storage structure for storing the scheduling information is relatively less, the calculation process is relatively simple and convenient, and the maintenance and combination process is easier.
Drawings
FIG. 1 is a flowchart illustrating the steps of a resource management method according to the present invention.
FIG. 2 is a diagram illustrating an example of hardware task allocation in the resource management method of the present invention.
The numbers in the figures illustrate the following:
1. assigned task T1; 2. assigned task T2; 3. unassigned task T3; 4. task T1 execution time; 5. task T2 execution time; 6. task T3 execution time; 7. maximum idle matrix 1; 8. maximum idle matrix 2; 9. a maximum idle matrix 3; 10. the FPGA can reconstruct resources.
Detailed Description
The invention provides a resource management method for effectively improving the resource utilization rate in order to solve the problem of insufficient resources in a reconstruction system, and a simulation experiment is designed for verification in order to verify the effectiveness of the resource management method. This experiment was performed on a 3.2Ghz intel core CPU, and the resource utilization performance was analyzed by calculating the task acceptance rate of the resource management method. The task acceptance rate represents that the task can be completed within a specified time and is not discarded, and if the task acceptance rate is high, the resource utilization rate of the algorithm is high, and the fragmentation rate generated by task allocation is low.
In an experiment, the reconstruction area of the FPGA is set to 100 × 100, the unit is the length of the CLB basic unit, 6 tasks are designed according to different task areas, the number of each task is set to 100, the area size, the arrival frequency and the execution time of each task are randomly generated according to a rule, but the task arrival frequencies of the task settings with the same area are different, and the specific rule is as follows:
task 1, the area range of the task is 10 × 10 to 20 × 20, the execution time range is 5 to 15, and the task arrival frequency is low (0-10); task 2, the area range of the task is 10 multiplied by 10 to 20 multiplied by 20, the execution time range is 5 to 15, and the task arrival frequency is high (0-100); task 3, the area range of the task is 20 × 20 to 30 × 30, the execution time range is 5 to 15, and the task arrival frequency is low (0-10); task 4, the area range of the task is 20 × 20 to 30 × 30, the execution time range is 5 to 15, and the task arrival frequency is high (0-100); task 5, the area range of the task is 30 x 30 to 40 x 40, the execution time range is 5 to 15, and the task arrival frequency is low (0-10); task 6, the area range of the task is 30 × 30 to 40 × 40, the execution time range is 5 to 15, and the task arrival frequency is high (0-100).
The specific embodiment is as follows:
firstly, one or more tasks which arrive firstly are stored into a ready list, at the moment, a delay list is empty, and an MER list is the size of the reconstruction area of the FPGA. The tasks in the ready list are sorted according to task priorities, and the specific content of the priority sorting is as follows: the smaller the relative allocation deadline, the higher the task priority; if the relative distribution deadline is the same, the task priority is higher when the area is smaller; if the areas are the same, the task priority is higher the earlier the deadline is. Traversing each task in the ready list according to the sorting sequence, comparing the area of each task with each MER in the MER list, if a certain MER is larger than the ready task, simulating the position of the task placed at four corners (upper left, lower left, upper right and lower right) of the MER, respectively calculating and storing contact values of the task and the four corners of the MER, wherein the calculation formula is as follows:
Figure BDA0001592508690000041
(wherein CV denotes a Contact Value, i is an unassigned task number, liDenotes an unallocated task contact edge, l denotes an allocated task contact edge, TiAnd T refers to the residual time of the distributed tasks. The specific calculation method of the contact value is as follows: firstly, calculating the contact length of the unallocated task and the configured task or the FPGA edge, then calculating the residual time of the unallocated task, and finally multiplying the contact length by the residual time to obtain a product). The convenience MER list then continues and contact values for the task with MERs that meet the condition are calculated until traversal is complete. By calculation, the position where the contact value is maximum is selected as the optimal position to be assigned, and the unassigned task is assigned to this position. Each time a task is allocated, the following steps need to be completed: according to the distribution position of the task, the MERs containing the task are divided again, and an MER list is updated; adding the task information into a running list; an allocation calculation for the next task in the ready list is performed. And if the distributable area does not exist after the MER list is traversed, adding the task into the delay list to wait for the next call. When a new task arrivesWhen the task is up, storing the task in a ready list, extracting the unfinished tasks previously stored in a delay list, sequencing the unfinished tasks according to the priority sequence of the tasks, and executing the execution steps so as to distribute the tasks. In the execution process, a task execution completion signal needs to be waited, when a certain task is executed, the task is cleared from FPGA resources, and a running list (the task information is removed from the running list) and an MER list (MERs containing the task are merged and then the MER list is traversed, so that the MERs with inclusion relations are removed). The ready list also monitors and compares the current time with the relative deadline of the task in the queue, and discards the task if the current time exceeds the relative deadline. Through simulation calculations, the following data can be obtained:
the task acceptance rate in the case of task 1 is 100%; the task acceptance rate in the case of task 2 is 100%; the task acceptance rate in the case of task 3 is 97%; the task acceptance rate in the case of task 4 is 61%; the task acceptance rate in the case of task 5 is 53%; the task acceptance rate in the case of task 62 is 32%.
The embodiments of the present invention are not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and they are included in the scope of the present invention.

Claims (4)

1. A resource management method based on FPGA reconfigurable technology comprises two parts of task scheduling and task allocation, and is characterized in that:
(1) in the task scheduling process, when a new task comes, the new task is stored in a ready list, and meanwhile, the tasks in the delay list which are not configured successfully before are added into the ready list and are sequenced according to priority;
(2) distributing the tasks in the ready list according to a sorting sequence, and judging whether a distribution area exists or not by comparing the maximum free area of the MER list with the task area information; if the assignable areas exist, calculating a contact value according to an assignment algorithm, selecting an MER with the largest contact value for task assignment, adding the task into an operation list, updating an MER list, and assigning the next task; if the distributable area does not exist after the MER list is traversed, adding the task into the delay list to wait for next call; when a new task arrives, storing the task in a ready list, extracting uncompleted tasks previously stored in a delay list, and sequencing according to the priority sequence of the tasks, thereby distributing the tasks;
the specific calculation method of the contact value comprises the following steps: firstly, calculating the contact length between an unallocated task and a configured task or the edge of an FPGA (field programmable gate array), then calculating the residual time of the allocated task, and finally multiplying the contact length by the residual time to obtain a product; the calculation formula is as follows:
Figure FDA0003155190440000011
wherein CV refers to a Contact Value, i is an unallocated task number, li refers to an unallocated task Contact edge, l refers to a Contact edge of a configured task or an FPGA edge, Ti refers to unallocated task remaining time, and T refers to allocated task remaining time;
(3) waiting for a task execution completion signal, and after the execution of a certain task is completed, clearing the task in the FPGA resource and updating the operation list and the MER list; the ready list can also monitor and compare the current time with the relative ending time of the tasks in the queue, and if the current time exceeds the relative ending time, the tasks are discarded;
(4) and (4) continuously repeating the steps (1) to (3) until all tasks are executed or discarded.
2. The resource management method based on the FPGA reconfigurable technology according to claim 1, characterized in that: the specific contents of the priority ranking are as follows: the smaller the relative allocation deadline, the higher the task priority; if the relative distribution deadline is the same, the task priority is higher when the area is smaller; if the areas are the same, the task priority is higher the earlier the deadline is.
3. The resource management method based on the FPGA reconfigurable technology according to claim 1, characterized in that: let T1 and T2 be the assigned tasks, where the execution time of T1 is time1 and the execution time of T2 is time 2; generating a maximum idle matrix according to the positions of the distributed tasks T1 and T2; the maximum idle matrix refers to a maximum rectangle which can be formed by idle areas, and the edges of the rectangle are allocated tasks or FPGA edges; the method comprises the steps of placing unallocated tasks at the upper left position, the lower left position, the upper right position and the lower right position of a maximum idle matrix by traversing the currently existing maximum idle matrix, and respectively calculating the contact values of the tasks at four corners of different maximum idle matrices; by calculation, the position where the contact value is maximum is selected as the optimal position to be assigned, and the unassigned task is assigned to this position.
4. The resource management method based on the FPGA reconfigurable technology according to claim 1, characterized in that: the updating operation list is to remove the task information from the operation list; and updating the MER list to merge MERs containing the task, and then traversing the MER list to remove MERs with inclusion relations.
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