CN108564921B - Display driver chip port multiplexing method and device and computer equipment - Google Patents
Display driver chip port multiplexing method and device and computer equipment Download PDFInfo
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- CN108564921B CN108564921B CN201810386306.3A CN201810386306A CN108564921B CN 108564921 B CN108564921 B CN 108564921B CN 201810386306 A CN201810386306 A CN 201810386306A CN 108564921 B CN108564921 B CN 108564921B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The application relates to a display driver chip port multiplexing method, a display driver chip port multiplexing device, computer equipment and a storage medium. The method comprises the following steps: receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information; generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal; the method for multiplexing the display driving chip port can generate different signals by using the same mode and can select any output port on the display driving chip to output, thereby changing the mode that the traditional display driving chip port can only transmit one signal, greatly improving the development speed of the display driving chip port and shortening the development period of the display driving chip port.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a display driver chip port multiplexing method and apparatus, and a computer device.
Background
With the development of electronic products, the function of the display driver chip is required to be powerful enough, for example, an additional port is generally adopted to output more signals. For another example, most of the digital products on the market have display screens. In order to display normally, the display screen is provided with a corresponding display driving chip. With the rapid development of the related art, the upgrading of the functions of the display driving chip is also imminent.
In order to transmit more signals or connect more peripheral circuits, it is necessary to display the ports of the driving chip, but in the implementation process, the inventor finds that at least the following problems exist in the conventional technology: increasing the number of ports of the display driving chip results in a long period of time for developing the port module.
Disclosure of Invention
In view of the above, it is necessary to provide a method, an apparatus and a computer device for multiplexing ports of a display driver chip, which can shorten a time period for developing a port module.
A display driving chip port multiplexing method comprises the following steps:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
and configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
In one embodiment, the signal generation instruction further comprises an inversion parameter;
the method for configuring the selection control register in the display driving chip according to the port information, selecting the output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port comprises the following steps:
configuring an inverting control register in the display driving chip according to the inverting parameter, and performing phase inverting processing on the first output signal through the inverting control register to obtain a second output signal;
and outputting the second output signal from the output port corresponding to the port information.
In one embodiment, the display driving chip is a display driving chip applied to drive an OLED display screen or an LCD display screen; the timing control signal is an RGB control signal.
In one embodiment, the step of configuring the corresponding register in the display driving chip according to the signal generation parameter includes:
the signal generation parameters comprise reference point values, offset values, row values, negative pulse row values, periodic row values, in-row rising values and in-row falling values;
the steps of configuring the register in the display driving chip are as follows:
configuring a reference point register of an output signal according to the reference point value;
according to the offset value, configuring a starting point register of the output signal relative to a register reference point;
configuring a row number control register of an output signal according to the row number value;
configuring a negative pulse row number control register of an output signal according to the negative pulse row number value;
configuring a periodic line number control register of an output signal according to the periodic line number value;
according to the ascending numerical value in the row, configuring an ascending delay control register in the row of the output signal;
and configuring an in-line falling delay control register of the output signal according to the in-line falling value.
In one embodiment, the first output signal includes a vst signal, a vg signal, an f0 signal, an f1 signal, a p0 signal, a p1 signal, a vgh signal, a vgl signal, a high level signal, and a low level signal.
A display driver chip port multiplexing device, comprising:
the signal receiving module is used for receiving the time sequence control signal and the signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
the signal generation module is used for generating parameters according to signals, configuring a corresponding register in the display driving chip and generating a first output signal according to a signal time sequence contained in the time sequence control signal;
and the selection output module is used for configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
In one embodiment, the selection output module further comprises:
the signal negation unit is used for configuring a negation control register in the display driving chip according to the negation parameters, and performing phase negation processing on the first output signal through the negation control register to obtain a second output signal;
and an output unit for outputting the second output signal from the output port corresponding to the port information.
A display driving chip comprises a memory and a processor; the processor includes a register; the memory stores a computer program that when executed by the processor performs the steps of:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
and configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
In one embodiment, the display driving chip is a display driving chip applied to drive an OLED display screen or an LCD display screen.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
and configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
One of the above technical solutions has the following advantages and beneficial effects:
the display driving chip receives a control signal and a signal generation instruction, wherein the control signal controls the signal timing sequence of the first output signal, the signal generation instruction comprises a signal generation parameter and port information, and configuring a corresponding register in the display driving chip to generate a first output signal according to the signal generation parameter, the output port matched with the port signal is selected according to the port signal to output the first output signal, and the display driving chip port multiplexing method can generate different signals by using the same mode, any output port on the display driving chip can be selected for output, the mode that only one signal can be transmitted by one port of the traditional display driving chip is changed, the port multiplexing method of the invention can lead the port to output different signals, therefore, the development speed of the port of the display driving chip is greatly improved, and the development period of the port of the display driving chip is shortened.
Drawings
FIG. 1 is a flowchart illustrating a first step of a method for multiplexing ports of a driver IC according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating the inverse steps in the method for multiplexing driver IC ports according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a second step of the method for multiplexing driver IC ports according to one embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a port structure of a display driver chip according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a signal generating module in a display driver chip according to an embodiment of the present invention;
FIG. 6 is a timing diagram of the output signals of the present invention in one embodiment;
FIG. 7 is a diagram illustrating a structure of a selective output module in a display driver chip according to an embodiment of the present invention;
FIG. 8 is a flowchart showing the steps of configuring registers in the method for multiplexing driver IC ports according to an embodiment of the present invention;
FIG. 9 is a block diagram showing the structure of a driver IC port multiplexing device according to an embodiment;
fig. 10 is an internal structural view showing a driver chip in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In order to solve the problem of long time period of the conventional display driver chip development port module, in an embodiment, as shown in fig. 1, a display driver chip port multiplexing method is provided, which includes the following steps:
step S110, receiving a timing control signal and a signal generation instruction; the signal generation instruction includes a signal generation parameter and port information.
Specifically, the display driver chip receives a control signal and a signal generation instruction sent by an external device, where the control signal may drive the display driver chip to normally operate and control a counter in a process of generating the first output signal to count, so as to control a signal timing sequence of the first output signal.
The signal generation instruction is used for controlling a signal generation module in the display driving chip to generate a first output signal, and the first output signal comprises signal generation parameters and port information. The signal generation parameters are values configured in or written into corresponding registers in the display driving chip, the signal generation module is controlled to generate the first output signal, and further, the signal generation parameters corresponding to different signals are different, and the specific reason why the signal generation parameters can be obtained according to specification requirements of external devices connected with the display driving chip.
Each output port of the display driving chip is matched with corresponding port information (the port information is equivalent to that of an identity card relative to a person, and the port information is in one-to-one correspondence), the corresponding output port can be found by the selection control register in the display driving chip through the port information, so that the output port is selected.
By using the display driving chip port multiplexing method, the signal generation module in the display driving chip can generate output signals with various types through a unified mode, and the output signals and the signal generation instructions are corresponding to each other.
Step S120, generating a first output signal according to the signal generation parameter, configuring a corresponding register in the display driving chip, and according to a signal timing included in the timing control signal.
Specifically, a counter in the process of generating the first output signal is controlled by the control signal to count, and the signal timing for generating the first output signal is controlled, so that the signal generation parameter is written into a corresponding register in the display driving chip, and the first output signal is generated after a certain time delay (generally, a nanosecond level). And the first output signal generated by the signal generating module is temporarily stored in the register, when the first output signal needs to be output, the corresponding register is configured to form a control signal, and the control register is selected to read and output the first output signal according to the physical address mapped to the first output signal by the control signal.
The signal generation parameters correspond to the output signals of the display driving chip, and when the type of the output signals needs to be changed, the signal generation parameters corresponding to the signal generation module are only needed.
Step S130, configuring a selection control register in the display driver chip according to the port information, selecting an output port corresponding to the port information in the display driver chip through the selection control register, and outputting the first output signal from the output port.
Specifically, after the selection register in the display driver chip obtains the port information, the port information is written into the selection control register, the selection control register finds the corresponding output port according to the port information, and the output signal generated by the signal generation module is output from the port.
It should be noted that, when the display driver chip outputs a signal, the method of the present invention can be used to control each port on the display driver chip to output a signal at the same time. For example, when the display driver chip includes 32 output ports, the method of the present invention can control the 32 output ports to simultaneously output one signal, and can also control the 32 output ports to simultaneously output different kinds of signals.
The display driving chip port multiplexing method comprises the steps that the display driving chip receives a control signal and a signal generation instruction, wherein the control signal controls the signal time sequence of a first output signal, the signal generation instruction comprises a signal generation parameter and port information, a corresponding register in the display driving chip is configured according to the signal generation parameter to generate a first output signal, an output port matched with the port signal is selected according to the port signal to output the first output signal, the display driving chip port multiplexing method can generate different signals by using the same mode, any output port on the display driving chip can be selected to output, the mode that only one signal can be transmitted by one port of a traditional display driving chip is changed, the port multiplexing method can enable the port to output different signals, and therefore the development speed of the display driving chip port is greatly improved, the period of development of the display driving chip port is shortened.
In one embodiment, in one of the embodiments, the signal generation instruction further comprises an inversion parameter;
in the step of configuring the selection control register in the display driver chip according to the port information, and selecting the corresponding output port in the display driver chip through the selection control register to output the first output signal, as shown in fig. 2, the method includes:
step S210, configuring an inverting control register in the display driving chip according to the inverting parameter, and performing phase inverting processing on the first output signal through the inverting control register to obtain a second output signal;
in step S220, the second output signal is output from the output port corresponding to the port information.
Specifically, the signal generation instruction further includes an inversion parameter, and the inversion parameter is used for writing into the inversion control register, so as to control whether to perform phase inversion processing on the first output signal before outputting the first output signal. The negation control register is opposite to the switch, and if the negation parameter is '1', the switch is closed, and then phase negation processing is carried out on the first output signal; when the inversion parameter is "0", the first output signal is output as it is without performing phase inversion processing on the first output signal.
In each embodiment of the port multiplexing method for the display driving chip, the first output signal is subjected to phase inversion, so that one more mode can be adopted during the output signal, in the mode, additional control logic and a configuration register are not needed, and on the assumption that the signal is subjected to phase inversion processing only by inverting the phase of the control signal of the control register, the register resource is saved, the size of the display driving chip is reduced, the repeated configuration register is reduced, and the power consumption of the display driving chip is reduced.
In one embodiment, as shown in fig. 3, the method for multiplexing ports of a display driver chip according to the present invention includes the following steps:
step S310, receiving a timing control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
step S320, generating a first output signal according to the signal generation parameter, configuring a corresponding register in the display driving chip and the signal time sequence contained in the time sequence control signal;
step S330, configuring an inverting control register in the display driving chip according to the inverting parameter, and performing phase inverting processing on the first output signal through the inverting control register to obtain a second output signal;
step S340, configuring a selection control register in the display driver chip according to the port information, selecting an output port corresponding to the port information in the display driver chip through the selection control register, and outputting the second output signal from the output port.
The embodiments of the port multiplexing method of the display driving chip provide a mode of inverting the phase of the first output signal and outputting the second output signal through the output port, thereby further optimizing the design of the port multiplexing method of the display driving chip and simplifying the logic.
In one embodiment, the display driving chip is a display driving chip applied to drive an OLED display screen or an LCD display screen; the timing control signal is an RGB control signal.
Further, the first output signal includes a vst signal, a vg signal, an f0 signal, an f1 signal, a p0 signal, a p1 signal, a vgh signal, a vgl signal, a high level signal, and a low level signal.
It should be noted that, when the Display driving chip port multiplexing method of the present invention is applied to a Display driving chip, the Display driving chip can drive different types of Display screens, such as an Organic Light Emitting Diode (OLED) Display screen, a Liquid Crystal Display (LCD) Display screen, a Light Emitting Diode (LED) Display screen, or an electronic ink Display screen.
Specifically, the display driver chip port multiplexing method of the present invention is applied to a display driver chip for generating corresponding signals to drive different types of display screens to work normally, and an AMOLED (Active-matrix organic light emitting diode) display screen is taken as an example for description below. The RGB (color mode) control signal is necessary for driving the display chip to work normally, and the display driving chip works normally is the basis for operating the steps of the method of the invention after the display driving chip is powered on.
The display driving chip comprises a GIP module, a GAMMA module, a SOURCE module, a DSP module, a SHIFT module and a CP module. The display driver chip port multiplexing method of the present invention provides a unified mode for generating signals, and the GIP module is used to explain the method steps of the present invention:
as shown in FIG. 4, the GIP module comprises 22 output ports (cgout _ r 1-11, cgout _ 11-111), as shown, a mux _ cell is included inside the GIP module, and as shown, a sig _ gen cell is also included inside the GIP module.
As shown in fig. 5, the CLK signal, REST _ N signal, REG OR CTRL SIGNAL signal in the sig _ gen cell are control signals for the sig _ gen cell to generate the first output signal. In one embodiment, the signal generation module of the display driver chip generates a vst signal, a vg signal, an f0 signal, an f1 signal, a p0 signal, a p1 signal, a vgh signal, a vgl signal, a high level signal and a low level signal at the same time, and buffers the signals in the register, and when any one of the signals needs to be output, a corresponding selection control register is configured to generate a control signal, and the control signal is mapped to a physical address corresponding to the control signal (the physical address is an address in which each signal generated by the signal generation module is buffered in the register), and the selection control register outputs an output signal corresponding to the physical address.
The first output signals are a vst signal (short pulse signal), a vg signal (clock signal), an f0/f1 signal (display related control signal), a p0/p1 signal (single pulse output signal), a vgh signal (fixed high level), a vgl signal (fixed low level), a high level signal, and a low level signal (as shown in fig. 6, a timing chart of each output signal). Furthermore, the display driving chip can generate periodic signals with various pulse widths by adopting the method.
The sig _ gen unit outputs the generated signal to the mux _ unit (as shown in fig. 7), and the mux _ unit selects a corresponding output port from the output ports of the display driver chip 22 according to the port information and outputs the signal.
In the embodiments of the port multiplexing method for the display driving chip, the port output signals of each module in the display driving chip are designed to be flexible and configurable, enough margin is reserved in the signal processing process, and the sub-modules in each module adopt a multiplexing mode.
In one embodiment, the step of configuring the corresponding register in the display driving chip according to the signal generation parameter includes:
the signal generation parameters comprise reference point values, offset values, row values, negative pulse row values, periodic row values, in-row rising values and in-row falling values;
the steps of configuring the register in the display driving chip are as follows:
step S810, configuring a reference point register of an output signal according to the reference point value;
step S820, configuring a starting point register of the output signal relative to a register reference point according to the offset value;
step S830, configuring a row number control register of the output signal according to the row number value;
step 840, configuring a negative pulse line number control register of the output signal according to the negative pulse line number value;
step S850, configuring a periodic line number control register of the output signal according to the periodic line number value;
step S860, according to the ascending numerical value in the row, the ascending delay control register in the row of the configuration output signal;
in step S870, the intra-row falling delay control register of the output signal is configured according to the intra-row falling value.
Specifically, the process of generating vsr _ signal (vsr _ signal represents any output signal generated by the display driver chip through the method of the present invention) by the configuration register is as follows:
firstly, a reference point register (cr _ bp) of a signal vsr _ relative to a starting point (0 row) is configured;
a reference point register (cr _ gip _ shift [11]), cr _ gip _ shift [11] ═ 1, at the left side or the right side of the configuration vsr _ signal, on the right side of the reference point, cr _ gip _ shift [11] ═ 0, at the left side of the reference point; cr _ gip _ shift [10:0] is the number of rows from the reference point to the starting point;
a line number control register (cr _ gip _ length) from the starting point to the end point of the vsr _ signal is configured;
a vsr-signal negative pulse line number control register (cr _ line _ width) is configured;
reconfiguring vsr-signal cycle row number control register (cr _ cycle);
an intra-row rising delay control register (cr _ vgh) for reconfiguring vsr-signal edge relative to the rising delay in the starting point row;
an intra-row falling numerical control register (cr _ vgl) for delaying the falling edge of the signal vsr-corresponding to the row of the starting point is configured;
after the registers are configured, the signal generation module generates an vsr signal and transmits a vsr signal to the selection output module, and the selection output module performs the following processing:
whether to invert vsr phase is controlled by an invert register (cr _ switch _);
finally, the select output register (cr _ mux _) selects which vsr _signalto output to the cgout _pin (as shown in fig. 4).
For example, vst _1 is to be generated by the set of registers 1 and output by the cgout _ l11 pin.
A reference point register cr _ bp is configured to be 5;
configuring a reference point register cr _ gip _1_ shift [11] ═ 1 (right shift), with a starting point at the right side of the reference point by 5 rows (cr _ gip _1_ shift [10:0] ═ 5);
a configuration line number control register cr _ gip _ length ═ 3;
the negative pulse line number control register cr _ line _ width _1 is configured to be 2 (number starting from 0);
the configuration cycle number control register cr _ cycle _1 is set to 2 (number starting from 0);
the configuration intra-row rising delay control register cr _ vgh _1 is set to 20;
the configuration inline droop value control register cr _ vgl _1 is set to 20;
then, inverting the signal output by the signal generating module by an inverting register cr _ switch _ 1-1;
the vsr _1 port output is selected by the select register cr _ mux _22 ═ 1.
According to the port multiplexing method, when the port selects to output, one output signal can be repeated, the phase of the output signal can be changed, the flexibility of signal output is improved, the operation of repeatedly configuring a register is reduced, and the power consumption of a display driving chip is reduced.
In one embodiment, after the step of selecting the output port of the display driver chip to output the output signal according to the port information, the method further includes:
driving a display screen externally connected with a display driver according to the first output signal;
when the display screen is normally lighted, the output signal configuration is judged to be correct.
Specifically, the display driving chip is used for driving an external display screen to display an output signal, and when a control signal input into the display screen is matched with the display screen, the display screen is normally lightened; when the control signal input into the display screen is not matched with the display screen, the display screen cannot be normally lightened. When the display screen was lit normally, it was confirmed that the actually required output signal could be generated using the method of the present invention.
In one embodiment, the method for multiplexing ports of a display driver chip of the present invention includes the following steps:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting a first output signal from the output port;
driving a display screen externally connected with a display driver according to the first output signal;
when the display screen is normally lighted, the output signal configuration is judged to be correct.
In the embodiments of the display driver chip port multiplexing method, the method of the present invention is used to generate signals for driving external devices, and different signals can be generated in the same mode, that is, the display driver chip loaded with the method of the present invention can generate different signals to adapt to devices connected with the display driver chip, so that the present invention has strong adaptability and a wide application range.
It should be understood that although the various steps in the flowcharts of fig. 1-3, 8 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-3, 8 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 9, there is provided a display driver chip port multiplexing apparatus including:
the signal receiving module 11 is configured to receive a timing control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
the signal generation module 12 is configured to configure a corresponding register in the display driver chip according to the signal generation parameter, and generate a first output signal according to a signal timing sequence included in the timing control signal;
and the selection output module 14 is configured to configure a selection control register in the display driver chip according to the port information, select an output port corresponding to the port information in the display driver chip through the selection control register, and output the first output signal from the output port.
In one embodiment, the selection output module further comprises:
the signal negation unit is used for configuring a negation control register in the display driving chip according to the negation parameters, and performing phase negation processing on the first output signal through the negation control register to obtain a second output signal;
and an output unit for outputting the second output signal from the output port corresponding to the port information.
For specific limitations of the display driver chip port multiplexing apparatus, reference may be made to the above limitations on the display driver chip port multiplexing method, which are not described herein again. All or part of each module in the display driver chip port multiplexing device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a display driver chip is provided, and an internal structural diagram thereof may be as shown in fig. 10. The display driving chip includes a processor, a memory, and a register connected through a system bus. Wherein, the processor of the display driving chip is used for providing calculation and control capability. The memory of the display driving chip comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The port of the display driving chip is used for connecting and communicating with an external device. The computer program is executed by a processor to implement a display driver chip port multiplexing method.
Those skilled in the art will appreciate that the architecture shown in fig. 10 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
and configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
configuring an inverting control register in the display driving chip according to the inverting parameter, and performing phase inverting processing on the first output signal through the inverting control register to obtain a second output signal;
and outputting the second output signal from the output port corresponding to the port information.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
the signal generation parameters comprise reference point values, offset values, row values, negative pulse row values, periodic row values, in-row rising values and in-row falling values;
the steps of configuring the register in the display driving chip are as follows:
configuring a reference point register of an output signal according to the reference point value;
according to the offset value, configuring a starting point register of the output signal relative to a register reference point;
configuring a row number control register of an output signal according to the row number value;
configuring a negative pulse row number control register of an output signal according to the negative pulse row number value;
configuring a periodic line number control register of an output signal according to the periodic line number value;
according to the ascending numerical value in the row, configuring an ascending delay control register in the row of the output signal;
and configuring an in-line falling delay control register of the output signal according to the in-line falling value.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
and configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
In one embodiment, the computer program when executed by the processor further performs the steps of:
configuring an inverting control register in the display driving chip according to the inverting parameter, and performing phase inverting processing on the first output signal through the inverting control register to obtain a second output signal;
and outputting the second output signal from the output port corresponding to the port information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
the signal generation parameters comprise reference point values, offset values, row values, negative pulse row values, periodic row values, in-row rising values and in-row falling values;
the steps of configuring the register in the display driving chip are as follows:
configuring a reference point register of an output signal according to the reference point value;
according to the offset value, configuring a starting point register of the output signal relative to a register reference point;
configuring a row number control register of an output signal according to the row number value;
configuring a negative pulse row number control register of an output signal according to the negative pulse row number value;
configuring a periodic line number control register of an output signal according to the periodic line number value;
according to the ascending numerical value in the row, configuring an ascending delay control register in the row of the output signal;
and configuring an in-line falling delay control register of the output signal according to the in-line falling value.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-accessible storage medium, and which, when executed, may comprise processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A display driving chip port multiplexing method is characterized by comprising the following steps:
receiving a time sequence control signal and a signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information;
generating a first output signal according to the signal generation parameter, configuring a corresponding register in a display driving chip and according to a signal time sequence contained in the time sequence control signal;
configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port;
the timing control signal is used for controlling the counting of a counter in the generation process of the first output signal.
2. The method according to claim 1, wherein the signal generation instruction further comprises an inversion parameter;
configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port, wherein the step includes:
configuring an inversion control register in the display driving chip according to the inversion parameters, and performing phase inversion processing on the first output signal through the inversion control register to obtain a second output signal;
and outputting the second output signal from an output port corresponding to the port information.
3. The method for multiplexing ports of display driver chips according to claim 1 or 2, wherein the display driver chips are display driver chips applied to drive OLED display screens or LCD display screens; the time sequence control signal is an RGB control signal.
4. The method for multiplexing ports of a display driver chip according to claim 3, wherein the step of configuring the corresponding register in the display driver chip according to the signal generation parameter comprises:
the signal generation parameters comprise reference point values, offset values, row values, negative pulse row values, periodic row values, in-row rising values and in-row falling values;
the step of configuring the register in the display driving chip is specifically as follows:
configuring a reference point register of the output signal according to the reference point value;
configuring a starting point register of the output signal relative to the register reference point according to the offset value;
configuring a row number control register of the output signal according to the row number value;
configuring a negative pulse row number control register of the output signal according to the negative pulse row number value;
configuring a periodic line number control register of the output signal according to the periodic line number value;
configuring an in-row rising delay control register of the output signal according to the in-row rising value;
and configuring an intra-row falling delay control register of the output signal according to the intra-row falling value.
5. The port multiplexing method of a display driver chip according to claim 4, wherein the first output signal comprises a vst signal, a vg signal, an f0 signal, an f1 signal, a p0 signal, a p1 signal, a vgh signal, a vgl signal, a high level signal, and a low level signal; wherein the vst signal is a short pulse signal; the vg signal is a clock signal; the f0 signal and the f1 signal are both display-related control signals; the p0 signal and the p1 signal are both single pulse signals; the vgh signal is a fixed high level signal; the vgl signal is a fixed low signal.
6. A display driver chip port multiplexing device, comprising:
the signal receiving module is used for receiving the time sequence control signal and the signal generation instruction; the signal generation instruction comprises a signal generation parameter and port information; the time sequence control signal is used for controlling the counting of a counter in the generation process of the first output signal;
the signal generation module is used for generating parameters according to the signals, configuring a corresponding register in a display driving chip and generating first output signals according to the signal time sequence contained in the time sequence control signals;
and the selection output module is used for configuring a selection control register in the display driving chip according to the port information, selecting an output port corresponding to the port information in the display driving chip through the selection control register, and outputting the first output signal from the output port.
7. The port multiplexing device of display driver chip according to claim 6, wherein the signal generating instruction further comprises an inverting parameter, and the selection output module further comprises:
the signal negation unit is used for configuring a negation control register in the display driving chip according to the negation parameters, and performing phase negation processing on the first output signal through the negation control register to obtain a second output signal;
an output unit for outputting the second output signal from an output port corresponding to the port information.
8. A display driving chip comprises a memory and a processor; the processor includes a register; the memory stores a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 5 when executing the computer program.
9. The display driving chip according to claim 8, wherein the display driving chip is a display driving chip applied to drive an OLED display screen or an LCD display screen.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 5.
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