CN108563533A - A method of it obtaining ICI impact factors and promotes error correcting capability - Google Patents
A method of it obtaining ICI impact factors and promotes error correcting capability Download PDFInfo
- Publication number
- CN108563533A CN108563533A CN201810258934.3A CN201810258934A CN108563533A CN 108563533 A CN108563533 A CN 108563533A CN 201810258934 A CN201810258934 A CN 201810258934A CN 108563533 A CN108563533 A CN 108563533A
- Authority
- CN
- China
- Prior art keywords
- storage unit
- cell
- ici
- impact factors
- interference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The invention discloses a kind of acquisition ICI impact factors and the methods for promoting error correcting capability, it is characterized in that adjacent interference storage unit, which is obtained ahead of time, according to experiment stores different data to storage unit Cell influence degrees, the data that interference storage unit by reading storage unit Cell is actually written into, the sub- impact factor for obtaining each interference storage unit respectively, is finally overlapped and obtains final ICI impact factors.The present invention is directed to the influence of the crosstalk ICI between consecutive storage unit in NAND Flash, obtain ICI impact factors, and it applies it in the LLR of Cell to generate the LUT tables more fully and refined, to promote LDPC error correcting capabilities, the method to promote NAND Flash service lifes.This method can solve the problems, such as that modification threshold voltage can not judge that overlapping part is distributed, and ICI influences are applied, and promote error correcting capability.
Description
Technical field
The present invention relates to technical field of memory more particularly to a kind of sides for obtaining ICI impact factors and promoting error correcting capability
Method.
Background technology
Nand Flash are a kind of non-volatile memories semiconductors, by injecting electronics to storage unit Cell floating gate layers
Mode store data.As electron number increases in storage unit floating gate layer, corresponding voltage also can gradually increase.Flash's
Erasing can damage the oxidation raceway groove of floating transistor, and the fluctuation and offset of voltage value, interfacial state trap is caused to restore and electronics
Escape will also result in the reduction of voltage, and usual Cell voltages can be approximately Gaussian Profile.By Cell voltages and judge voltage Vth
(also referred to as threshold voltage) comparison, may thereby determine that the data Level of its storage.
Fig. 1 is two kinds of contiguous memory locations voltage's distribiuting schematic diagrames, and wherein A is point of ideal two neighboring storage unit
Overlapping cases are not present in the voltage of cloth, two storage units, therefore default judgement voltage Default Vref is taken to can be realized
The data of two storage units judge that there is no influence each other.But the data of Nand Flash storages can be by adjacent
The interference of Cell is detained influence and the random noise disturbance of Retention characteristics, causes the offset and broadening of voltage's distribiuting.
Judge that voltage Vth range will result in erroneous judgement when part Cell voltage's distribiutings exceed, mistake Bit numbers is caused to increase.B is adjacent two
There is the distribution for overlapping situation in a storage unit；But when adjacent Level distributions overlap, simple adjustment judges electricity
Pressure not can determine that the voltage's distribiuting at overlapping place.Targetedly offset judges that voltage can reduce erroneous judgement, this is current universal
Error correction method.
LDPC (Low-density Parity-check, low-density checksum) algorithm is a kind of loop iteration algorithm,
It is mainly judged by carrying out reliability (Log Likelihood Ratio) to each bit, ultimately generates LUT tables (Look Up
Table. look-up table, exactly each bit can have the reliability metric form of oneself in a lookup table, for characterizing corresponding bit
Whether the reliable and degree of reliability), overturn the mode of iteration error correction to carrying out part bit to the data of read error and carry out.Its
During generating LUT tables, required average information is known as Soft Inform ation.The acquisition of Soft Inform ation, it is contemplated that factor it is more,
Information generation more refines, and LUT tables are more accurate, to which LDPC error correcting capabilities are promoted.
Invention content
LUT tables are refined last real for disadvantages described above present invention aims at how to obtain more detailed Soft Inform ation
Now promote the purpose of LDPC error correcting capabilities.
To achieve the goals above, the present invention provides a kind of methods obtaining ICI impact factors, it is characterised in that according to
Adjacent interference storage unit storage different data is obtained ahead of time to storage unit Cell influence degrees in experiment, is stored by reading
The data that the interference storage unit of unit Cell is actually written into obtain the sub- impact factor of each interference storage unit, most respectively
It is overlapped afterwards and obtains final ICI impact factors.
The method of the acquisition ICI impact factors, it is characterised in that only choose maximum on storage unit Cell influences
Two adjacent storage units only read the number that the two interference storage units selected are actually written into as interference storage unit
According to, and two sub- impact factors are obtained, final ICI impact factors are obtained after the two sub- impact factors are overlapped.
The method of the acquisition ICI impact factors, it is characterised in that Nand Flash are MLC types, and interference storage is single
" 10 " are pressed in influence of the data of member storage to storage unit Cell>“00”>“01”>" 11 " are distributed from big to small；Storage is single
The ICI impact factors selection Cell [WLi-1, BLj] and two storage units of Cell [WLi+1, BLj] of first Cell [WLi, BLj]
As interference storage unit.
A method of promoting error correcting capability, reliability of the feature in calculating LDPC algorithms according to ICI impact factors
LLR (Log Likelihood Ratio) and LUT tables, error correction is iterated using LLR and LUT tables；The acquisition ICI influence because
Son is obtained according to following method, is that adjacent interference storage unit storage different data is obtained ahead of time to storage list according to experiment
First Cell influence degrees, the data that the interference storage unit by reading storage unit Cell is actually written into, obtain each respectively
The sub- impact factor for interfering storage unit is finally overlapped and obtains final ICI impact factors.
The method of the promotion error correcting capability, it is characterised in that only choose influences maximum two to storage unit Cell
Adjacent storage unit only reads the data that the two interference storage units selected are actually written into as interference storage unit, and
Two sub- impact factors are obtained, final ICI impact factors are obtained after the two sub- impact factors are overlapped.
The method of the promotion error correcting capability, it is characterised in that Nand Flash are MLC types, and interference storage unit is deposited
" 10 " are pressed in influence of the data of storage to storage unit Cell>“00”>“01”>" 11 " are distributed from big to small；Storage unit
Two storage units of ICI impact factors selection Cell [WLi-1, BLj] and Cell [WLi+1, BLj] of Cell [WLi, BLj] are made
To interfere storage unit.
The present invention is directed to the influence of the crosstalk ICI between consecutive storage unit in NAND Flash, obtains ICI impact factors,
And apply it to generate the LUT tables more fully and refined in the LLR of Cell, to promote LDPC error correcting capabilities, to
The method for promoting NAND Flash service lifes.This method, which can solve modification threshold voltage, can not judge overlapping part distribution
Problem, and ICI influences are applied, promote error correcting capability.
Description of the drawings
Fig. 1 is two kinds of contiguous memory locations voltage's distribiuting schematic diagrames；
Fig. 2 is the structural schematic diagram of NAND Flash storage units；
Fig. 3 is the voltage's distribiuting schematic diagram for MLC Nand；
Fig. 4 is Flash consecutive storage unit schematic diagrames；
Fig. 5 is that data distribution influence schematic diagram is written with it in the impacted degree of WLi；
Fig. 6 is the influence schematic diagram that the different Cell states of WLi are subject in different adjacent WL under Cell states respectively.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
Fig. 2 is the structural schematic diagram of NAND Flash storage units, mainly include source electrode (Source), drain electrode (Drain),
Grid (Control Gate) and floating gate (Floating Gate) are controlled, stores the size of data by injecting electron institute
The voltage swing of generation indicates.To must first be wiped it before the write-in of NAND Flash, nothing in floating gate after erasing
Electronics is expressed as " 1 ", it is written, then is that electronics, different electron amounts difference are injected to floating gate layer according to the data of write-in
Indicate different data informations.
Nand Flash interfacial state traps restore and the obedience Poisson distribution of the detrapping process approximation of electronics, therefore its voltage
Distribution can be approximated to be Gaussian Profile.Fig. 3 is the voltage's distribiuting schematic diagram for MLC Nand, is that Low Page sentence with wherein VL
Power-off pressure, VH1 and VH2 are that High Page judge voltage.
Fig. 4 is Flash consecutive storage unit schematic diagrames, in Nand Flash, there are a kind of adjacent interval interference phenomenon,
I.e. arbitrary storage unit can be caused storage charge number to change by the crosstalk of consecutive storage unit.Intermediate storage unit is known as
Disturbed storage unit VictimCell, the storage unit for generating interference around remaining to Victim Cell are known as interfering storage
Unit Aggressor Cell.Any one storage unit is both that Victim Cell are interfered by surrounding storage unit, and
Aggressor Cell disturb the storage unit near it.
Interference of the Aggressor Cell to Victim Cell, interfere between mainly adjacent Cell it is larger, in Fig. 4
For, it is Cell [WLi-1, BLj] respectively to interfere larger Cell [WLi, BLj], Cell [WLi+1, BLj], Cell [WLi,
BLj-1] and Cell [WLi, BLj+1], wherein adjacent word line WL Cell [WLi-1, BLj], Cell [WLi+1, BLj] influence compared with
Greatly, the influence of the two is mainly considered herein.
Influences of the Aggressor Cell of adjacent WL to Victim Cell, essentially consists in the ablation process to WLi+1
In, it needs to apply WLi certain voltage, this voltage causes in some electron injections to the floating gate layer of WLi, this effect is referred to as soft
It programs (Soft Program), under the action of soft programming, the voltage's distribiuting of Cell generates variation.
The size that WLi+1 acts on the soft programming of WLi, it is related with the write-in data of WLi+1, from the acquiescence after erasing "
The span difference of 11 " states to end-state is bigger, bigger to the soft programming effect of WLi, that is to say, that by taking MLC as an example, in Cell
In the case that [WLi, BLj] data with existing is written and state distribution has been determined, when data are written in Cell [WLi+1, BLj], write-in
Different data be " 10 " to the influence degree situations of data in Cell [WLi, BLj]>“00”>“01”>“11”.
Degree impacted WLi is written data distribution with it and further relates to, the high state of spread voltage about susceptible,
That is, by taking MLC as an example, if Fig. 5 is that the impacted degree of WLi is written with it shown in data distribution influence schematic diagram, F1 is
Arrow initial position is distributed：Electronic voltage distribution situation after program in Cell；F2 is distributed for arrow final position：
Electronic voltage distribution situation after influences of the Aggressor Cell to different Victim Cell electronic voltages.Cell [WLi+1,
BLj] write-in data it is the same in the case of, the impacted degree of different distributions is in Cell [WLi, BLj]：“10”>“00”>“01”
>“11”。
Shown in Fig. 6, characterization is that the different Cell states of WLi are subject in different adjacent WL under Cell states respectively
It influences.Solid line：Electronic voltage distribution after data program；Dotted line：Victim when corresponding states being written in adjacent WL
Electronic voltage distribution after cell is impacted.
In NAND Flash in error correction procedure, by taking High Page as an example, the impact factor of Aggressor Cell obtain and
Applying step is as follows：
Step 1：When being read out the mistake for occurring can not correcting to WLi data, the Low of adjacent WLi-1 is read
Page data obtain data set { D10, D11, D12, D13 ... }, and wherein D10 is first Bit data, and D11 is second Bit
Data, and so on；And the High Page data of adjacent WLi-1 are read, data set { D20, D21, D22, D23 ... } is obtained,
Middle D20 is first Bit data, and D21 is second Bit data, and so on.Thus, it is possible to obtain the 2bit numbers in Cell
According to collection, i.e., { (D10D20), (D11D21), (D12D22), (D13D23) ... }, wherein (D10D20) is in first Cell
2bit data, (D11D21) they are the 2bit data in second Cell, and so on.
Step 2：If there are valid data in WLi+1, obtained in WLi+1 in each Cell according to method in step 1
2bit data such as obtain data set { (D30D40), (D31D41), (D32D42), (D33D43) ... }, wherein (D30D40) is the
2bit data in one Cell, (D31D41) they are the 2bit data in second Cell, and so on.
Step 3：The data of Cell in WLi-1 are indicated with impact factor herein according to the interval of itself and " 11 " distribution, are divided
It is 4 grades, is indicated respectively with 1,2,3,4, numerical value is bigger indicates that its distance " 11 " state is remoter.When there is valid data in WLi+1,
Its impact factor is superimposed with the impact factor of WLi-1, obtain all Cell in WL impact factor collection L0, L1, L2,
L3 ... }, wherein L0 is the impact factor of first Cell, and L1 is the impact factor of second Cell, and so on.
Step 4：It can be with influence factor value is bigger, indicates that its influence to WLi is bigger from previous step and analysis.
Step 5：If the reading of High Page in the WLi of error reads the Low Page in WLi, to obtain at this time
The 2bit data sets in each Cell of current WLi are got, according to obtained Cell distribution situations, described in step 3
Degree of susceptibility, be added to impacted degree as impact factor addition in acquired impact factor.
Step 6：After the impact factor for obtaining Cell, the data of the position of the bigger Cell of impact factor more can not
It leans on, that is, the probability that malfunctions is higher.In LDPC algorithms, LLR is smaller, i.e., when corrupt data, positive exact figures are obtained after being overturn
According to probability it is higher.
Step 7：According to the correspondence of the LLR and LUT tables of LDPC algorithms in used controller.Applying to LDPC
When, according to the difference of each controller realization method, this likelihood ratio can be mapped, being mapped to oneself controller can
Identify the value used.
When final error correction in the controller, LUT tables, that is, the value after mapping are used.Error correction principles are：When going out
When existing UECC mistakes, check that the reliability of each bit, the low bit of reliability are the portion that bit overturnings have occurred in maximum possible
Point, which is overturn, i.e., 1 overturning is that 0,0 overturning is 1, then goes to judge current data correctness again, if still not just
Really, then the minimum bit of reliability is overturn, is iterated by the reliability for calculating each bit again, until data are whole just
Iteration maximum times that are true or reaching setting.
Rational LLR and LUT tables can be calculated according to this impact factor for iteration error correction, are improved error correcting capability, are obtained
To correct data.
Above disclosed is only an embodiment of the present invention, cannot limit the right model of the present invention with this certainly
It encloses, those skilled in the art can understand all or part of the processes for realizing the above embodiment, and is wanted according to right of the present invention
Equivalent variations made by asking still fall within the range that the present invention is covered.
Claims (6)
1. a kind of method obtaining ICI impact factors, it is characterised in that adjacent interference storage unit is obtained ahead of time according to experiment
Different data is stored to storage unit Cell influence degrees, the interference storage unit by reading storage unit Cell is actually written into
Data, obtain the sub- impact factor of each interference storage unit respectively, be finally overlapped obtain final ICI influence because
Son.
2. the method according to claim 1 for obtaining ICI impact factors, it is characterised in that only choose to storage unit Cell
Maximum two adjacent storage units are influenced as interference storage unit, and it is practical only to read the two interference storage units selected
The data of write-in, and two sub- impact factors are obtained, final ICI is obtained after the two sub- impact factors are overlapped to be influenced
The factor.
3. the method according to claim 2 for obtaining ICI impact factors, it is characterised in that the number of interference storage unit storage
" 10 " are pressed according to the influence to storage unit Cell>“00”>“01”>" 11 " are distributed from big to small；Storage unit Cell [WLi,
BLj] two storage units of ICI impact factors selection Cell [WLi-1, BLj] and Cell [WLi+1, BLj] as interference storage
Unit.
4. a kind of method promoting error correcting capability, reliability LLR of the feature in calculating LDPC algorithms according to ICI impact factors
(Log Likelihood Ratio) and LUT tables, error correction is iterated using LLR and LUT tables；The acquisition ICI impact factors
It is obtained according to following method, is that adjacent interference storage unit, which is obtained ahead of time, according to experiment stores different data to storage unit
Cell influence degrees, the data that the interference storage unit by reading storage unit Cell is actually written into obtain each dry respectively
The sub- impact factor for disturbing storage unit is finally overlapped and obtains final ICI impact factors.
5. the method according to claim 4 for promoting error correcting capability, it is characterised in that only choose to storage unit Cell shadows
Maximum two adjacent storage units are rung as interference storage units, only read two interference selecting storage unit is practical and write
Data entered, and obtain two sub- impact factors, obtained after the two sub- impact factors are overlapped final ICI influence because
Son.
6. the method according to claim 5 for promoting error correcting capability, it is characterised in that Nand Flash are MLC types, are done
Influence of the data of storage unit storage to storage unit Cell is disturbed by " 10 ">“00”>“01”>" 11 " are divided from big to small
Cloth；The ICI impact factors selection Cell [WLi-1, BLj] and Cell [WLi+1, BLj] two of storage unit Cell [WLi, BLj]
Storage unit is as interference storage unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810258934.3A CN108563533A (en) | 2018-03-27 | 2018-03-27 | A method of it obtaining ICI impact factors and promotes error correcting capability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810258934.3A CN108563533A (en) | 2018-03-27 | 2018-03-27 | A method of it obtaining ICI impact factors and promotes error correcting capability |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108563533A true CN108563533A (en) | 2018-09-21 |
Family
ID=63533522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810258934.3A Pending CN108563533A (en) | 2018-03-27 | 2018-03-27 | A method of it obtaining ICI impact factors and promotes error correcting capability |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108563533A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102171767A (en) * | 2008-09-30 | 2011-08-31 | Lsi公司 | Methods and apparatus for soft data generation for memory devices based on performance factor adjustment |
| US20130094293A1 (en) * | 2011-10-18 | 2013-04-18 | Samsung Electronics Co., Ltd. | Memory device and method of reading data from memory device |
| CN103226974A (en) * | 2011-12-15 | 2013-07-31 | 马维尔国际贸易有限公司 | Inter-cell interference cancellation |
| CN105679364A (en) * | 2014-12-08 | 2016-06-15 | 桑迪士克技术有限公司 | Rewritable multibit non-volatile memory with soft decode optimization |
-
2018
- 2018-03-27 CN CN201810258934.3A patent/CN108563533A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102171767A (en) * | 2008-09-30 | 2011-08-31 | Lsi公司 | Methods and apparatus for soft data generation for memory devices based on performance factor adjustment |
| US20130094293A1 (en) * | 2011-10-18 | 2013-04-18 | Samsung Electronics Co., Ltd. | Memory device and method of reading data from memory device |
| CN103226974A (en) * | 2011-12-15 | 2013-07-31 | 马维尔国际贸易有限公司 | Inter-cell interference cancellation |
| CN105679364A (en) * | 2014-12-08 | 2016-06-15 | 桑迪士克技术有限公司 | Rewritable multibit non-volatile memory with soft decode optimization |
Non-Patent Citations (2)
| Title |
|---|
| MINCHEOL PARK .ETC: "Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of NAND Flash Cell Arrays", 《IEEE ELECTRON DEVICE LETTERS》 * |
| VEERESH TARANALLI .ETC: "Error analysis and inter-cell interference mitigation in multi-level cell flash memories", 《2015 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC)》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI574277B (en) | Error correction operations in a memory device | |
| US9087598B2 (en) | Reliability metrics management for soft decoding | |
| TWI569273B (en) | Method for read disturbance management in non-volatile memory devices | |
| US8036035B2 (en) | Erase cycle counter usage in a memory device | |
| US11163483B2 (en) | Robust detection techniques for updating read voltages of memory devices | |
| US8689082B2 (en) | Method of operating memory controller, and memory system, memory card and portable electronic device including the memory controller | |
| US7894270B2 (en) | Data restoration method for a non-volatile memory | |
| US9478298B2 (en) | Memory system and method of reading data thereof | |
| CN108647109A (en) | A kind of method that solid state disk promotes LDPC error correcting capabilities | |
| US9342401B2 (en) | Selective in-situ retouching of data in nonvolatile memory | |
| US11557353B2 (en) | Optimal detection voltage obtaining method, reading control method and apparatus of memory | |
| US9490024B1 (en) | Solid state storage device and reading control method thereof | |
| US9430339B1 (en) | Method and apparatus for using wear-out blocks in nonvolatile memory | |
| US9053011B2 (en) | Selective protection of lower page data during upper page write | |
| CN108154900B (en) | Method for relieving write interference problem of MLC flash memory | |
| CN108595286A (en) | A kind of method and solid state disk promoting reliability of flash memory | |
| US11513879B2 (en) | Detection and mitigation for solid-state storage device read failures due to weak erase | |
| CN108563533A (en) | A method of it obtaining ICI impact factors and promotes error correcting capability | |
| JP2022525273A (en) | A method for writing to a non-volatile memory device by applying multiple bit line bias voltages | |
| JP5039193B2 (en) | Semiconductor memory device and control method | |
| CN117296098A (en) | Voltage block group calibration based on temporary voltage shift offset | |
| CN110908825B (en) | Data reading method and device, storage equipment and storage medium | |
| US9754685B2 (en) | Memory control device and memory control method | |
| JP2022524535A (en) | Methods and equipment for the operation of the non-volatile memory mechanism | |
| CN117724878A (en) | Data processing method, electronic equipment and computer readable storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180921 |
|
| RJ01 | Rejection of invention patent application after publication |