CN108540688B - Distributed splicing controller, image sending method and image processing method - Google Patents
Distributed splicing controller, image sending method and image processing method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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- H04N5/04—Synchronising
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- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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Abstract
The embodiment of the invention provides a distributed splicing controller, an image sending method and an image processing method, wherein the distributed splicing controller comprises the following steps: each acquisition processor controls to send acquired video images to the data exchange equipment through timing reference pulses; the data exchange equipment is used for receiving the video images sent by each acquisition processor and sending each received video image to the corresponding at least one display processor according to the preset corresponding relation between each acquisition processor and the corresponding at least one display processor; each display processor controls the receiving, the laminating processing and the output of the video images through the timing reference pulse; wherein, the time interval between every two adjacent timing reference pulses is greater than or equal to the preset receiving time delay, and the preset receiving time delay is as follows: a time determined from a delay skew of the data exchange device. To achieve synchronization of the display of video images of the same video source.
Description
Technical Field
The invention relates to the technical field of multimedia, in particular to a distributed splicing controller, an image sending method and an image processing method.
Background
With the development of social informatization, people need a larger display wall which can be composed of a plurality of display devices to comprehensively display a variety of information. In the industries of railway command and dispatch, public security, coal, petrochemical industry, electric power, communication, traffic and the like, a larger display wall is required to comprehensively display various information. The distributed splice controller can meet the above requirements of people.
Fig. 1 is a diagram illustrating an example of a large-screen display using a distributed tiled controller, where the distributed tiled controller includes a plurality of acquisition processors, a data exchange device (such as the switch in fig. 1), a plurality of display processors, and a master server. The workflow of the distributed splice controller is generally: the acquisition processor acquires video images sent by a video source, packages the acquired video images according to the instruction of the master control server and sends the video images to the data exchange equipment through the Ethernet; the data exchange equipment sends each encapsulated video image to at least one corresponding display processor according to the preset corresponding relation between each acquisition processor and at least one display processor; each display processor performs lamination processing on the received video images according to the timing reference pulse to obtain laminated images, and reads and outputs the laminated images according to the timing reference pulse so that the display equipment corresponding to the display processor displays the laminated images. Wherein, the lamination treatment comprises the following steps: each display processor performs image superposition processing on the received video images according to the image occlusion information set by the master control server, and a plurality of display devices form the display wall in fig. 1.
However, in the distributed splice controller, due to its own performance, when receiving video images of the same video source and sending the video images of the same video source to corresponding different display processors from different interfaces, the data exchange device may have a sequence, that is, when sending video images of the same video source between different interfaces of the data exchange device, there may be a time difference of hundreds of microseconds, that is, there is a delay deviation. In the process of sending the video image, which interface sends first, and the order of sending after which interface cannot be determined.
When receiving the video images of the same video source, the display processor which receives the video images firstly carries out lamination processing on the currently received video images when the timing reference pulse arrives to obtain laminated images, and outputs the laminated images of the currently received video images when the next timing reference pulse arrives; and the display processor for later receiving performs lamination processing on the previous frame of video image of the video image because the current receiving is not completed when the timing reference pulse arrives, and outputs the lamination image of the previous frame of video image of the video image when the next timing reference pulse arrives. At this point, the displayed video images will be out of sync between different display devices displaying the same video source.
The problem of asynchronous display of video images of the same video source becomes an urgent problem to be solved.
Disclosure of Invention
The embodiment of the invention aims to provide a distributed splicing controller, an image sending method and an image processing method so as to realize the synchronization of video image display of the same video source. The specific technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a distributed splice controller, where the distributed splice controller includes multiple acquisition processors, multiple display processors, and a data exchange device;
each acquisition processor is used for sending the acquired Nth frame of video image to the data exchange equipment when a timing reference pulse at the time T arrives, wherein N is a positive integer, and T is a non-negative number;
the data exchange equipment is used for receiving the video images sent by each acquisition processor and determining at least one display processor corresponding to each received video image according to a preset corresponding relation; sending each received video image to at least one corresponding display processor, wherein the preset corresponding relation is the corresponding relation between each acquisition processor and at least one display processor;
each display processor is used for receiving the Nth frame of video image sent by the data exchange equipment according to the preset corresponding relation when the timing reference pulse at the moment of T +1 arrives, carrying out lamination processing on the Nth-1 frame of video image and outputting a lamination image corresponding to the Nth-2 frame of video image;
wherein, the time interval between the timing reference pulse at the time T and the timing reference pulse at the time T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is: time determined from the delay skew of the data exchange device.
Optionally, the crystal oscillators set by the plurality of acquisition processors and the crystal oscillators set by the plurality of display processors have the same frequency.
Optionally, one of the multiple acquisition processors in the distributed splice controller is used as a master processor, and the other acquisition processors except the master processor and the multiple display processors are used as slave processors; or
One display processor in a plurality of display processors in the distributed splicing controller is used as a main processor, and other display processors except the main processor and the plurality of acquisition processors are used as auxiliary processors;
the main processor is configured to: and sending first reference clock information to each slave processor in a timing mode, wherein the first reference clock information comprises first time, so that each slave processor performs clock correction according to the first time and generates a timing reference pulse according to the corrected clock.
Optionally, the slave processor is configured to: receiving the first reference clock information, wherein the first reference clock information comprises the first time; according to the first time, clock correction is carried out; a timing reference pulse is generated based on the corrected clock.
In one aspect, an embodiment of the present invention provides an image sending method based on the distributed splice controller, which is applied to a data exchange device in the distributed splice controller, and the method includes:
the data exchange equipment receives an Nth frame of video image which is sent by each acquisition processor when a timing reference pulse at the time T arrives, wherein N is a positive integer, T is a non-negative number, the time interval between the timing reference pulse at the time T and a timing reference pulse at the time T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: time determined according to the delay deviation of the data exchange equipment;
determining at least one display processor corresponding to each Nth frame of video image according to a preset corresponding relationship, wherein the preset corresponding relationship is as follows: the corresponding relation between each acquisition processor and at least one display processor in the distributed splicing controller;
and sending each Nth frame video image to the determined corresponding at least one display processor.
Optionally, the crystal oscillators set by the multiple acquisition processors in the distributed splicing controller have the same frequency as the crystal oscillators set by the multiple display processors in the distributed splicing controller.
In one aspect, an embodiment of the present invention provides an image processing method based on the above-mentioned distributed stitching controller, which is applied to a display processor in the distributed stitching controller, and the method includes:
when a timing reference pulse at the time of T +1 arrives, receiving an Nth frame of video image sent by data exchange equipment according to a preset corresponding relation, wherein the preset corresponding relation is as follows: the distributed splicing controller comprises a distributed splicing controller and at least one display processor, wherein each acquisition processor in the distributed splicing controller corresponds to at least one display processor, the time interval between a timing reference pulse at the moment T and a timing reference pulse at the moment T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: time determined according to the delay deviation of the data exchange equipment;
and performing lamination processing on the N-1 frame video image, and outputting a lamination image corresponding to the N-2 frame video image.
Optionally, the crystal oscillator set by the display processor has the same frequency as the crystal oscillators set by other display processors except the display processor in the distributed splicing controller and the plurality of acquisition processors in the distributed splicing controller.
Optionally, when the display processor is used as a main processor in the distributed splice controller, the method further includes:
and sending second reference clock information to other display processors except the self and the plurality of acquisition processors in the distributed splicing controller at regular time, wherein the second reference clock information comprises second time, so that the other display processors except the self and the plurality of acquisition processors in the distributed splicing controller carry out clock correction according to the second time, and generate timing reference pulses according to the corrected clock.
Optionally, when the display processor is used as a slave processor in the distributed splice controller, the method further includes:
receiving third reference clock information, wherein the third reference clock information comprises a third time;
according to the third time, clock correction is carried out;
a timing reference pulse is generated based on the corrected clock.
In the embodiment of the invention, each acquisition processor is used for sending the acquired Nth frame of video image to the data exchange equipment when a timing reference pulse at the time T arrives, wherein N is a positive integer, and T is a non-negative number; the data exchange equipment is used for receiving the video images sent by each acquisition processor and determining at least one display processor corresponding to each received video image according to a preset corresponding relation; sending each received video image to a corresponding at least one display processor, wherein the preset corresponding relation is the corresponding relation between each acquisition processor and the at least one display processor; each display processor is used for receiving the N frame of video image sent by the data exchange equipment according to the preset corresponding relation when the timing reference pulse at the moment of T +1 arrives, carrying out lamination processing on the N-1 frame of video image and outputting a lamination image corresponding to the N-2 frame of video image; the time interval between the timing reference pulse at the moment T and the timing reference pulse at the moment T +1 is greater than or equal to the preset receiving time delay, and the preset receiving time delay is as follows: a time determined from a delay skew of the data exchange device.
The time interval between the timing reference pulses is greater than or equal to the preset receiving time delay, so that when the acquisition processor sends the video images, the previous frame of the sent video images is sent to each corresponding display processor through the data exchange equipment. The method avoids the asynchronous processing of the same video image by different display processors caused by the time delay of sending the same video image to different display processors due to the self performance factor of the data exchange equipment, and further avoids the asynchronous display of the video image between different display equipment displaying the same video source. Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is an exemplary diagram of a large screen display using a distributed splice controller;
fig. 2 is a schematic structural diagram of a distributed splice controller according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of an image sending method based on the distributed splice controller of claim 1 according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of an image processing method based on the distributed stitching controller of claim 1 according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a distributed splicing controller, an image sending method and an image processing method, which are used for realizing the synchronization of video image display of the same video source.
First, a distributed splice controller according to an embodiment of the present invention is described below.
As shown in fig. 2, an embodiment of the present invention provides a distributed splice controller, and the distributed splice controller 200 may include a plurality of acquisition processors 210, a plurality of display processors 220, and a data exchange device 230;
each acquisition processor 210 is configured to send an acquired nth frame of video image to the data exchange device 230 when a timing reference pulse at a time T comes, where N is a positive integer and T is a non-negative number;
a data exchange device 230, configured to receive the video images sent by each acquisition processor 210, and determine, according to a preset correspondence, at least one display processor 220 corresponding to each received video image; sending each received video image to a corresponding at least one display processor 220, wherein the preset corresponding relationship is a corresponding relationship between each acquisition processor 210 and at least one display processor 220;
each display processor 220 is configured to receive the nth frame of video image sent by the data exchange device 230 according to a preset corresponding relationship when the timing reference pulse at the time T +1 arrives, perform stack processing on the N-1 th frame of video image, and output a stack image corresponding to the N-2 th frame of video image;
the time interval between the timing reference pulse at the moment T and the timing reference pulse at the moment T +1 is greater than or equal to the preset receiving time delay, and the preset receiving time delay is as follows: a time determined from a delay skew of the data exchange device 230.
It is understood that each data exchange device 230 corresponds to a delay variation, which is an inherent attribute parameter of each data exchange 230 and can be provided by the manufacturer of the data exchange device 230. The delay offset may be: when the same video image is output using all but one of the interfaces in the data exchange device 230 that receives the video image, an offset value is calculated that is equal to: and subtracting the output time corresponding to the interface outputting the video image at the earliest time from the output time corresponding to the interface outputting the video image at the latest time.
Wherein, the N-1 frame video image is: the display processor 220 receives the image when the timing reference pulse at the time point T-1 arrives, and the video image of the N-2 th frame is: the image received by processor 220 at the time of the arrival of the timing reference pulse at time T-2 is displayed. Each acquisition processor 210 and each display processor 220 included in the distributed splicing controller 200 according to the embodiment of the present invention may periodically generate timing reference pulses, and the time interval between every two adjacent timing reference pulses is the same. I.e., the time interval between the timing reference pulse at time T-1 and the timing reference pulse at time T-2 is equal to the time interval between the timing reference pulse at time T and the timing reference pulse at time T-1, and equal to the time interval between the timing reference pulse at time T and the timing reference pulse at time T + 1.
It is understood that the timing reference pulse at the time T-1 is a timing reference pulse previous to the timing reference pulse at the time T, and the timing reference pulse at the time T +1 is a timing reference pulse subsequent to the timing reference pulse at the time T; for example, when the time T is 10 hours and 30 seconds, the time interval between timing reference pulses is 16 milliseconds, and in this case, the time T-1 represents 29.984 seconds at 10 hours, the time T +1 represents 30.016 seconds at 10 hours, and so on, the time T-n represents (30 seconds-n × 16 milliseconds at 10 hours), and the time T + n represents (30 seconds + n × 16 milliseconds at 10 hours), where n is a non-negative number.
The data switching devices 230 may be switch devices, wherein the switch devices may be at least one.
It should be noted that the connection between each acquisition processor 210 and the data exchange device 230 and between the data exchange device 230 and each display processor 220 shown in fig. 2 are only used to indicate that a communication connection exists and do not represent a physical connection. Each of the acquisition processors 210 corresponds to one video source, that is, each of the acquisition processors 210 can acquire a video image provided by one video source.
Each acquisition processor 210 and each display processor 220 in the distributed splice controller 200 work independently and exchange information through the connected data exchange device 230, for example: each acquisition processor 210 sends the acquired video image to at least one display processor 220 corresponding to each acquisition processor 210 through the data exchange device 230; different display processors 220 can receive video images of the same video source through the preset corresponding relationship of the data exchange device 230.
In the distributed stitching controller 200, each acquisition processor 210 may correspond to at least one display processor 220, i.e., the video images acquired by each acquisition processor 210 may be transmitted to the corresponding at least one display processor 220 through the data exchange device 230. The at least one display processor 220 can implement synchronous reception, synchronous lamination processing and synchronous output of video images of the same video source according to the timing reference pulse, and further, the display device corresponding to the at least one display processor 220 performs synchronous display of the video images of the same video source, thereby implementing large-screen display of the video images.
In addition, in the embodiment of the present invention, the time interval between every two adjacent timing reference pulses is greater than the preset receiving delay, so that different display processors receiving the same frame of video image can receive the same frame of video image when the timing reference pulse at the same time arrives, and further, can perform the stack processing on the received same frame of video image when the timing reference pulse at the next same time arrives.
It is understood that there is a time difference from when the acquisition processor 210 starts to transmit the acquired video image to when the corresponding display processor 220 receives the video image; the display processor 220 needs to consume time for performing the stack processing on the video images, and the time consumed for performing the stack processing on the video images is referred to as processing time; the display processor 220 reads the stacked image, and also requires a time consumption, which is referred to herein as a reading time; based on the above, in setting the reception time delay in advance, a time having the largest value may be selected from among the time difference, the processing time, and the reading time as a target time, and the reception time delay may be set to: the sum of the target time and the delay offset of the data exchange device 230, i.e., the time interval between every two adjacent timing reference pulses, may be greater than or equal to the sum of the target time and the delay offset of the data exchange device 230. The time difference, the processing time and the reading time can be obtained by the prior art, and are not described herein again.
It will be appreciated that each acquisition processor 220 effects the transmission of acquired video images by timing reference pulses. When each timing reference pulse arrives, each acquisition processor 220 sends a frame of video image, and the time interval between every two adjacent timing reference pulses is greater than or equal to a preset receiving delay, where the receiving delay is: the time determined according to the delay skew of the data exchange device 230 is used to ensure that the data exchange device 230 can complete the transmission of the video image of the previous frame of the received video image from each corresponding interface when the video image is received.
It is understood that the distributed stitching controller 200 further includes a master server, and as is known in the art, the preset correspondence relationship in the data exchange device 230 is controlled by the master server, and the overlay processing performed on the video images by each display processor 220 is also controlled by the master server.
By applying the embodiment of the invention, the time interval between the timing reference pulses is greater than or equal to the preset receiving time delay, so that when the acquisition processor sends the video images, the previous frame of the sent video images is sent to each corresponding display processor through the data exchange equipment. The asynchronous display method and the asynchronous display device avoid the problem that the different display processors process the same video image asynchronously due to time delay caused by self performance factors of the data exchange device when the same video image is sent to the different display processors, and further avoid the asynchronous display of the video image between different display devices displaying the same video source.
In one implementation, since each acquisition processor 210 and each display processor 220 in the distributed tiled controller 200 operate independently, in order to ensure synchronization of each acquisition processor 210 and each display processor 220 in the distributed tiled controller 200, the crystal oscillators set by the plurality of acquisition processors 210 and the crystal oscillators set by the plurality of display processors 220 have the same frequency. The crystal oscillator is configured to provide a clock for a corresponding processor (including the acquisition processor 210 and the display processor 220), and as is known in the art, the crystal oscillator may divide a generated frequency by a clock dividing device to a clock frequency of the corresponding processor, so as to provide the clock for the corresponding processor; specifically, each of the acquisition processors 210 generates a timing reference pulse according to its own clock; each display processor 220 generates a timing reference pulse according to its own clock.
It is understood that due to the performance of the oscillators, clock frequency offsets of several tens of PPM (parts Per milliont) exist between different oscillators, and the accumulated clock frequency offsets increase with the increase of time, which further causes the timing reference pulses in each processor (including the acquisition processor 210 and the display processor 220) in the distributed splice controller 200 to be misaligned, i.e., causes the timing reference pulses in each processor in the distributed splice controller 200 to be generated at different times. To ensure synchronization of the clocks in each processor in the distributed splice controller 200, i.e., to synchronously generate the timing Reference pulses, the clocks of each processor (including the acquisition processor and the Display processor) in the distributed splice controller 200 can be corrected using DCR (Display Clock Reference) techniques to achieve synchronization of each processor in the distributed splice controller 200. The processor included in the distributed splice controller 200 may be randomly determined to serve as a main processor, and used to send reference clock information, so that the other processors except the processor serving as the main processor in the distributed splice controller respectively correct their own clocks according to the reference clock information.
In one implementation, one acquisition processor 210 of the plurality of acquisition processors 210 in the distributed splice controller 200 serves as a master processor, and the other acquisition processors 210 except the master processor and the plurality of display processors 220 in the distributed splice controller 200 serve as slave processors; or
One display processor 220 of the plurality of display processors 220 in the distributed tiled controller 200 is used as a master processor, and the other display processors 220 except the master processor and the plurality of acquisition processors 210 in the distributed tiled controller are used as slave processors;
the main processor is configured to: sending first reference clock information to each slave processor in a timed mode, wherein the first reference clock information comprises first time, so that each slave processor performs clock correction according to the first time and generates a timing reference pulse according to the corrected clock;
in one implementation, the first time may be a current time of the host processor.
And, the slave processor is configured to: receiving first reference clock information, wherein the first reference clock information comprises first time; according to the first time, clock correction is carried out; a timing reference pulse is generated based on the corrected clock.
The process of clock correction by each slave processor according to the first time and the process of generating the timing reference pulse according to the corrected clock may adopt the prior art, and are not described herein.
Corresponding to the distributed stitching controller, an embodiment of the present invention provides an image sending method based on the distributed stitching controller, which is applied to a data exchange device in the distributed stitching controller, and as shown in fig. 3, the image sending method may include the following steps:
s301: the data exchange equipment receives an Nth frame of video image which is sent by each acquisition processor when a timing reference pulse at the moment T arrives, wherein N is a positive integer, T is a non-negative number, the time interval between the timing reference pulse at the moment T and the timing reference pulse at the moment T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: time determined from the delay skew of the data switching device;
s302: determining at least one display processor corresponding to each Nth frame of video image according to a preset corresponding relationship, wherein the preset corresponding relationship is as follows: the corresponding relation between each acquisition processor and at least one display processor in the distributed splicing controller;
s303: and sending each Nth frame video image to the determined corresponding at least one display processor.
It is understood that each acquisition processor in the distributed stitching controller corresponds to one video source, i.e., each acquisition processor can acquire a video image provided by one video source. The acquisition processor transmits the acquired video images through the timing reference pulse. Each time the timing reference pulse arrives, the acquisition processor sends a frame of video image to the data exchange device.
And the data exchange equipment receives the Nth frame of video image sent by each acquisition processor, determines at least one display processor corresponding to each Nth frame of video image according to a preset corresponding relation, and sends each received Nth frame of video image to the corresponding at least one display processor. Wherein, the time interval between every two adjacent timing reference pulses generated by the acquisition processor is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: and the time is determined according to the delay deviation of the data exchange equipment, so that the data exchange equipment can ensure that the data exchange equipment can finish sending the video image which is the frame before the received video image from each corresponding interface when receiving the video image, and at least one display processor corresponding to the acquisition processor can simultaneously receive the video image which is the frame before the received video image when the timing reference pulse arrives. At least one display processor corresponding to the acquisition processor is ensured to carry out lamination processing on the same frame of video images when a timing reference pulse at the same time arrives.
By applying the embodiment of the invention, the time interval between the timing reference pulses is greater than or equal to the preset receiving time delay, so that when the acquisition processor sends the video images, the previous frame of the sent video images is sent to each corresponding display processor through the data exchange equipment. The asynchronous display method and the asynchronous display device avoid the problem that the different display processors process the same video image asynchronously due to time delay caused by self performance factors of the data exchange device when the same video image is sent to the different display processors, and further avoid the asynchronous display of the video image between different display devices displaying the same video source.
Because each acquisition processor and each display processor in the distributed splicing controller work independently, in order to ensure the synchronization of each acquisition processor and each display processor in the distributed splicing controller, in one implementation mode, the crystal oscillator set by the acquisition processor has the same frequency as the crystal oscillators set by other acquisition processors except the acquisition processor and all display processors in the distributed splicing controller. The crystal oscillator is configured to provide a clock for a corresponding processor (including the acquisition processor and the display processor), and as is known in the art, the crystal oscillator may divide a frequency generated by the crystal oscillator by a clock dividing device to a clock frequency of the corresponding processor, so as to provide the clock for the corresponding processor.
It can be understood that, due to the performance factors of the oscillators, clock frequency offsets of the order of tens of PPM (Part Per milliont) exist between different oscillators, and as time increases, the accumulated clock frequency offsets also increase, which further causes the timing reference pulses in each processor (including the acquisition processor and the display processor) in the distributed splicing controller to be misaligned, i.e., causes the timing reference pulses in each processor in the distributed splicing controller to be generated at different times. In order to ensure the synchronization of the clocks in each processor in the distributed tiled controller, i.e. the synchronous generation of the timing Reference pulse, the Clock of each processor in the distributed tiled controller may be corrected by using a DCR (Display Clock Reference) technique, so as to achieve the synchronization of each processor in the distributed tiled controller. The distributed splicing controller may further include a processor, which is determined to be a main processor from the processors included in the distributed splicing controller at random, and is configured to send reference clock information, so that the other processors except the processor serving as the main processor in the distributed splicing controller respectively correct their own clocks according to the reference clock information.
Specifically, the master processor may send reference clock information to the slave processors in the distributed splice controller at regular time, where the reference clock information includes time related to the master processor; the slave processors in the distributed splice controller may receive the reference clock information and perform clock correction according to the time for the master processor contained in the reference clock information, and then generate timing reference pulses according to the corrected clock. In this way, the clocks of all processors (acquisition processor and display processor) included in the distributed splice controller are guaranteed to be synchronized. The time related to the host processor contained in the reference clock information may be the current time of the host processor.
Corresponding to the distributed stitching controller, an embodiment of the present invention provides an image processing method based on the distributed stitching controller, which can be applied to a display processor in the distributed stitching controller, and as shown in fig. 4, the method may include the following steps:
s401: when the timing reference pulse at the time of T +1 arrives, receiving the Nth frame of video image sent by the data exchange device according to a preset corresponding relation, wherein the preset corresponding relation is the corresponding relation between each acquisition processor and at least one display processor in the distributed splicing controller, the time interval between the timing reference pulse at the time of T and the timing reference pulse at the time of T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: time determined from the delay skew of the data switching device;
s402: and performing lamination processing on the N-1 frame video image, and outputting a lamination image corresponding to the N-2 frame video image.
In the distributed splicing controller, each acquisition processor transmits an acquired N frame video image to the data exchange equipment when a timing reference pulse at the time T arrives, the display processor receives the N frame video image transmitted by the data exchange equipment when a timing reference pulse at the time T +1 arrives, the time interval between the timing reference pulse at the time T and the timing reference pulse at the time T +1 is larger than the preset receiving time delay, so that each display processor receiving the same frame N frame image can simultaneously receive the same frame N frame image when the timing reference pulse at the time T +1 arrives, each display processor receiving the same frame N frame image is confirmed to receive the same frame N frame image when the timing reference pulse at the time T +2 arrives, and the same frame N frame image can be synchronously subjected to stacking processing, and synchronously outputting, and further synchronously displaying the laminated images corresponding to the same frame of the N frame of images by each display device corresponding to the display processor receiving the same frame of the N frame of images.
By applying the embodiment of the invention, the time interval between the timing reference pulses is greater than or equal to the preset receiving time delay, so that when the acquisition processor sends the video images, the previous frame of the sent video images is sent to each corresponding display processor through the data exchange equipment. The asynchronous display method and the asynchronous display device avoid the problem that the different display processors process the same video image asynchronously due to time delay caused by self performance factors of the data exchange device when the same video image is sent to the different display processors, and further avoid the asynchronous display of the video image between different display devices displaying the same video source.
Because each acquisition processor and each display processor in the distributed splicing controller work independently, in order to ensure the synchronization of each acquisition processor and each display processor in the distributed splicing controller, in one implementation mode, the crystal oscillator set by the display processor has the same frequency as the crystal oscillators set by other display processors except the display processor in the distributed splicing controller and the acquisition processors in the distributed splicing controller. The crystal oscillator is configured to provide a clock for a corresponding processor (including the acquisition processor and the display processor), and as is known in the art, the crystal oscillator may divide a frequency generated by the crystal oscillator by a clock dividing device to a clock frequency of the corresponding processor, so as to provide the clock for the corresponding processor.
When the clock correction is performed on the processor in the distributed tiled controller, the display processor may serve as a main processor for performing the clock correction, and is configured to send reference clock information, so that the other display processors in the distributed tiled controller except the display processor serving as the main processor and all the acquisition processors in the distributed tiled controller respectively correct their own clocks according to the reference clock information.
In one implementation, when the display processor is used as a main processor in a distributed splice controller, the method may further include:
and sending second reference clock information to other display processors and the plurality of acquisition processors in the distributed splicing controller at regular time, wherein the second reference clock information comprises second time, so that the other display processors and the plurality of acquisition processors in the distributed splicing controller carry out clock correction according to the second time, and generate timing reference pulses according to the corrected clock.
In yet another implementation, the second time may be a current time of the display processor.
Or, in another implementation, when performing clock correction on the processor in the distributed tiled controller, the display processor serves as the slave processor in the distributed tiled controller; at this time, the method may further include:
receiving third reference clock information, wherein the third reference clock information comprises a third time;
according to the third time, clock correction is carried out;
a timing reference pulse is generated based on the corrected clock.
At this time, the sender of the third reference clock information may be any one of the other display processors in the distributed mosaic controller except the display processor described above, or any one of the acquisition processors in the distributed mosaic controller.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A distributed splice controller, comprising a plurality of acquisition processors, a plurality of display processors, and a data exchange device;
each acquisition processor is used for sending the acquired Nth frame of video image to the data exchange equipment when a timing reference pulse at the time T arrives, wherein N is a positive integer, and T is a non-negative number;
the data exchange equipment is used for receiving the video images sent by each acquisition processor and determining at least one display processor corresponding to each received video image according to a preset corresponding relation; sending each received video image to at least one corresponding display processor, wherein the preset corresponding relation is the corresponding relation between each acquisition processor and at least one display processor;
each display processor is used for receiving the Nth frame of video image sent by the data exchange equipment according to the preset corresponding relation when the timing reference pulse at the moment of T +1 arrives, carrying out lamination processing on the Nth-1 frame of video image and outputting a lamination image corresponding to the Nth-2 frame of video image;
wherein, the time interval between the timing reference pulse at the time T and the timing reference pulse at the time T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is: and the time is determined according to the delay deviation of the data exchange equipment, wherein the delay deviation of the data exchange equipment is equal to the subtraction of the output time corresponding to the interface which outputs the video image at the latest and the output time corresponding to the interface which outputs the video image at the earliest when the data exchange equipment outputs the same video image.
2. The distributed splice controller of claim 1, wherein the crystal oscillators set by the plurality of acquisition processors are co-frequent with the crystal oscillators set by the plurality of display processors.
3. The distributed splice controller of claim 2 wherein one of the plurality of acquisition processors within the distributed splice controller acts as a master processor, and the other acquisition processors except the master processor and the plurality of display processors act as slave processors; or
One display processor in a plurality of display processors in the distributed splicing controller is used as a main processor, and other display processors except the main processor and the plurality of acquisition processors are used as auxiliary processors;
the main processor is configured to: and sending first reference clock information to each slave processor at fixed time, wherein the first reference clock information comprises first time, the first time is the current time of the master processor, so that each slave processor performs clock correction according to the first time and generates a timing reference pulse according to the corrected clock.
4. The distributed splice controller of claim 3,
the slave processor is configured to: receiving the first reference clock information, wherein the first reference clock information comprises the first time; according to the first time, clock correction is carried out; a timing reference pulse is generated based on the corrected clock.
5. An image sending method based on the distributed splicing controller of claim 1, wherein the method is applied to a data exchange device in the distributed splicing controller, and the method comprises:
the data exchange equipment receives an Nth frame of video image which is sent by each acquisition processor when a timing reference pulse at the time T arrives, wherein N is a positive integer, T is a non-negative number, the time interval between the timing reference pulse at the time T and a timing reference pulse at the time T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: the time is determined according to the delay deviation of the data exchange equipment, and the delay deviation of the data exchange equipment is equal to the subtraction of the output time corresponding to the interface which outputs the video image at the latest and the output time corresponding to the interface which outputs the video image at the earliest when the data exchange equipment outputs the same video image;
determining at least one display processor corresponding to each Nth frame of video image according to a preset corresponding relationship, wherein the preset corresponding relationship is as follows: the corresponding relation between each acquisition processor and at least one display processor in the distributed splicing controller;
and sending each Nth frame video image to the determined corresponding at least one display processor.
6. The method of claim 5, wherein the crystal oscillators set by the plurality of acquisition processors in the distributed splice controller are at the same frequency as the crystal oscillators set by the plurality of display processors in the distributed splice controller.
7. An image processing method based on the distributed splicing controller of claim 1, applied to a display processor in the distributed splicing controller, the method comprising:
when a timing reference pulse at the time of T +1 arrives, receiving an Nth frame of video image sent by data exchange equipment according to a preset corresponding relation, wherein the preset corresponding relation is as follows: the distributed splicing controller comprises a distributed splicing controller and at least one display processor, wherein each acquisition processor in the distributed splicing controller corresponds to at least one display processor, the time interval between a timing reference pulse at the moment T and a timing reference pulse at the moment T +1 is greater than or equal to a preset receiving time delay, and the preset receiving time delay is as follows: the time is determined according to the delay deviation of the data exchange equipment, and the delay deviation of the data exchange equipment is equal to the subtraction of the output time corresponding to the interface which outputs the video image at the latest and the output time corresponding to the interface which outputs the video image at the earliest when the data exchange equipment outputs the same video image;
and performing lamination processing on the N-1 frame video image, and outputting a lamination image corresponding to the N-2 frame video image.
8. The method of claim 7, wherein the display processor is configured with a crystal oscillator that is co-frequent with crystal oscillators configured by other display processors in the distributed splice controller except for the display processor itself and a plurality of acquisition processors in the distributed splice controller.
9. The method of claim 8, wherein when the display processor is acting as a master processor in the distributed splice controller, the method further comprises:
and sending second reference clock information to other display processors except the self and the plurality of acquisition processors in the distributed splicing controller at regular time, wherein the second reference clock information comprises second time which is the current time of the display processors, so that the other display processors except the self and the plurality of acquisition processors in the distributed splicing controller carry out clock correction according to the second time and generate timing reference pulses according to the corrected clock.
10. The method of claim 8, wherein when the display processor is a slave processor in the distributed splice controller, the method further comprises:
receiving third reference clock information, wherein the third reference clock information comprises third time, and the third time is the time when the main processor sends the third reference clock information;
according to the third time, clock correction is carried out;
a timing reference pulse is generated based on the corrected clock.
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|---|---|---|---|---|
| CN102226943A (en) * | 2011-04-29 | 2011-10-26 | 杭州海康威视数字技术股份有限公司 | System and method for realizing screen splicing |
| CN106454010A (en) * | 2016-10-21 | 2017-02-22 | 青岛海信电器股份有限公司 | Synchronous display calibration method for multi-screen spliced display system, displays and multi-screen spliced display system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102226943A (en) * | 2011-04-29 | 2011-10-26 | 杭州海康威视数字技术股份有限公司 | System and method for realizing screen splicing |
| CN106454010A (en) * | 2016-10-21 | 2017-02-22 | 青岛海信电器股份有限公司 | Synchronous display calibration method for multi-screen spliced display system, displays and multi-screen spliced display system |
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