CN108538812A - Encapsulating structure - Google Patents
Encapsulating structure Download PDFInfo
- Publication number
- CN108538812A CN108538812A CN201710702304.6A CN201710702304A CN108538812A CN 108538812 A CN108538812 A CN 108538812A CN 201710702304 A CN201710702304 A CN 201710702304A CN 108538812 A CN108538812 A CN 108538812A
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- China
- Prior art keywords
- bit patterns
- pair
- conductive layer
- crystal grain
- encapsulating structure
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of encapsulating structures, including a crystal grain, one first insulating layer and one first conductive layer.The crystal grain includes one first pair of bit patterns.First insulating layer includes one first opening.First conductive layer includes one first conductive pattern and one second pair of bit patterns.First conductive pattern is located at described first and is open, and second pair of bit patterns are located on first insulating layer.First pair of bit patterns setting corresponding with second pair of bit patterns.This on crystal grain and conductive layer disclosed in being respectively set to bit patterns, and therefore, this exposure can utilize the contraposition that bit patterns are carried out with crystal grain and conductive layer.After contraposition, crystal grain on conductive layer to bit patterns i.e. can be overlapped.This exposure can be according to the overlapping cases to bit patterns on crystal grain and conductive layer, while measuring the overlay errors of X-direction and Y-direction, to promote measurement efficiency.
Description
Technical field
The present invention relates to a kind of encapsulating structures, more particularly to a kind of encapsulating structure that can effectively promote aligning accuracy.
Background technology
Flip chip packaging technologies are that Solder Bumps (solder bump) is generated in the engagement pad of crystal grain (die), and crystal grain is turned over
Turn, so that Solder Bumps is aligned with the circuit on substrate, then melt Solder Bumps via reflow (reflow) processing procedure.Wait for tin
After lead convex block cooled and solidified, the signal transmission pathway between crystal grain and substrate is just formed.Since the prior art leans on the contact of crystal grain
The circuit on Solder Bumps and substrate on pad is aligned, and is had the bad problem of aligning accuracy and is occurred.In addition, for contraposition
Overlay errors (overlay error) afterwards measure, and the prior art must separate the overlay errors for measuring X-direction and Y-direction, amount
It is bad to survey efficiency.Furthermore after the completion of crystal grain is engaged with substrate, the prior art, which must first complete pressing mold (molding), to be measured
It is electrically whether normal, can not be together with conductive layer, such as layer (redistribution layer, RDL) is reassigned, it measures connect together
It is electrical after conjunction.
Invention content
Problem to be solved by this invention is：In order to make up for the deficiencies of the prior art, contraposition can effectively be promoted by providing one kind
The encapsulating structure of precision.
The encapsulating structure of the present invention uses following technical scheme：
A kind of encapsulating structure, which is characterized in that the encapsulating structure includes：
One crystal grain, including one first pair of bit patterns；
One first insulating layer, including one first opening；And
One first conductive layer, including one first conductive pattern and one second pair of bit patterns, first conductive pattern are located at
First opening, second pair of bit patterns are located on first insulating layer；
Wherein, first pair of bit patterns setting corresponding with second pair of bit patterns.
The encapsulating structure, wherein the crystal grain further includes a third to bit patterns, and first conductive layer further includes
One the 4th pair of bit patterns, the 4th pair of bit patterns are located on first insulating layer, and the third to bit patterns with it is described
The 4th pair of corresponding setting of bit patterns.
The encapsulating structure, wherein the encapsulating structure further includes an electric conductor, and the electric conductor connects the crystalline substance
Grain and first conductive layer.
The encapsulating structure, wherein the electric conductor connects the crystalline substance by low temperature ultrasonic or anisotropic conductive adhesive paste
Grain and first conductive layer.
The encapsulating structure, wherein the encapsulating structure further includes an electric conductor and one second conductive layer, and described
Two conductive layers are between the crystal grain and first conductive layer, and the electric conductor connects the crystal grain and led with described second
Electric layer.
The encapsulating structure, wherein the electric conductor connects the crystalline substance by low temperature ultrasonic or anisotropic conductive adhesive paste
Grain and second conductive layer.
The encapsulating structure, wherein the crystal grain further includes one first engagement pad, and first engagement pad is neighbouring described
First pair of bit patterns, and first between of bit patterns with first engagement pad at a distance from be greater than or equal to and 20 microns and be less than
Or it is equal to 200 microns.
The encapsulating structure, wherein the area of first engagement pad be greater than or equal to 400 square microns and be less than or
Equal to 106Square micron.
The encapsulating structure, wherein first conductive layer further includes a test pattern, the area of the test pattern
More than or equal to 400 square microns and it is less than or equal to 106Square micron.
The encapsulating structure, wherein the crystal grain further includes one first engagement pad, and first conductive layer further includes one
Test pattern, first engagement pad are electrically connected the test pattern.
Therefore, according to preceding solution, encapsulating structure of the invention at least has following advantages and advantageous effect：This hair
Bright to be respectively set to bit patterns on crystal grain and conductive layer, therefore, the present invention can carry out crystal grain and conductive layer using to bit patterns
Contraposition.After contraposition, crystal grain on conductive layer to bit patterns i.e. can be overlapped.The present invention can be according on crystal grain and conductive layer
To the overlapping cases of bit patterns, while the overlay errors of X-direction and Y-direction are measured, to promote measurement efficiency.In addition, of the invention
Test pattern can be formed on the electrically conductive when making conductive layer.After the completion of crystal grain is engaged with conductive layer, using conductive layer
On test pattern directly measure the electrical of crystal grain and conductive layer.It is carried out after confirming that electrically there is no problem, then to encapsulating structure
Pressing mold, to promote the yield of encapsulating structure.
Description of the drawings
Fig. 1 is the sectional view of the encapsulating structure of one embodiment of the invention.
Fig. 2 is the vertical view of the encapsulating structure in Fig. 1.
Fig. 3 A are the schematic diagrames of first pair of bit patterns and second pair of bit patterns.
Fig. 3 B are another schematic diagrames of first pair of bit patterns and second pair of bit patterns.
Fig. 3 C are another schematic diagrames of first pair of bit patterns and second pair of bit patterns.
Fig. 4 A are the schematic diagrames that test pattern corresponds to an engagement pad.
Fig. 4 B are another schematic diagrames that test pattern corresponds to an engagement pad.
Fig. 4 C are another schematic diagrames that test pattern corresponds to two engagement pads.
Fig. 5 is the sectional view of the encapsulating structure of another embodiment of the present invention.
Fig. 6 A to Fig. 6 I are the processing procedure schematic diagrames of the encapsulating structure in Fig. 1.
Reference sign：1,1'- encapsulating structures；10- crystal grain；The first insulating layers of 11-；The first conductive layers of 12-；14- is led
Electric body；16- engagement pads；The first engagement pads of 16a-；The second engagement pads of 16b-；17- second insulating layers；The second conductive layers of 18-；20-
Glass substrate；22- release layers；24- weld pads；26- third insulating layers；100- first is to bit patterns；102- thirds are to bit patterns；
110- first is open；120- second is to bit patterns；The 4th pair of bit patterns of 122-；The first conductive patterns of 123-；124- test patterns；
170- second is open；The second conductive patterns of 180-；260- thirds are open；280- third conductive patterns；D1, D2- distance.
Specific implementation mode
Please refer to Fig.1 and Fig. 2, Fig. 1 be one embodiment of the invention encapsulating structure 1 sectional view, Fig. 2 is in Fig. 1
The vertical view of encapsulating structure 1.
As shown in Figures 1 and 2, encapsulating structure 1 include a crystal grain 10, it is one first insulating layer 11, one first conductive layer 12, more
A electric conductor 14 and multiple engagement pads 16.Electric conductor 14 is connecting crystal grain 10 and the first conductive layer 12.In the present embodiment,
Electric conductor 14 can be Solder Bumps, and but not limited to this.In addition, the first conductive layer 12 can be the reassignment on circuit board
Layer.Crystal grain 10 includes one first pair of bit patterns 100 and a third to bit patterns 102, and the first conductive layer 12 includes one second
To bit patterns 120 and one the 4th pair of bit patterns 122, set wherein first pair of bit patterns 100 is corresponding with second pair of bit patterns 120
It sets, and third is to the setting corresponding with the 4th pair of bit patterns 122 of bit patterns 102.In the present embodiment, first pair of bit patterns 100
Size be less than the size of second pair of bit patterns 120, and third is less than the 4th pair of bit patterns 122 to the sizes of bit patterns 102
Size.However, in other embodiments, the size of first pair of bit patterns 100 is also greater than the size of second pair of bit patterns 120,
And third is also greater than the size of bit patterns 102 size of the 4th pair of bit patterns 122.In other words, first pair of bit patterns
100, second pair of bit patterns 120, third can determine to bit patterns 102 and the size of the 4th pair of bit patterns 122 according to practical application
Fixed, as long as the size of first pair of bit patterns 100 is different from the size of second pair of bit patterns 120, and third is to the ruler of bit patterns 102
The very little size difference with the 4th pair of bit patterns 122.In the present embodiment, the first engagement pad 16a in multiple engagement pads 16
Neighbouring first pair of bit patterns 100, and the second engagement pad 16b in multiple engagement pads 16 adjacent to third to bit patterns 102.
First insulating layer 11 includes one first opening 110, and the first conductive layer 12 further includes one first conductive pattern 123,
Wherein the first conductive pattern 123 is located at the first opening 110, and second pair of bit patterns 120 and the 4th pair of bit patterns 122 are located at first
On insulating layer 11.In the present embodiment, can the first opening 110 first be formed in the first insulating layer 11, then by the first conductive pattern 123
The first opening 110 of filling.
In the present embodiment, encapsulating structure 1 can be fabricated by flip chip packaging technologies.It first, can connecing in crystal grain 10
Electric conductor 14 is generated in touch pad 16, then crystal grain 10 is overturn, and crystal grain 10 is made to be aligned with the first conductive layer 12.At this point, this hair
100, second pairs of bit patterns 120 of bright available first pair of bit patterns, third carry out bit patterns 102 and the 4th pair of bit patterns 122
The contraposition of crystal grain 10 and the first conductive layer 12.After contraposition, in the first pair of bit patterns 100 and the first conductive layer 12 on crystal grain
Second pair of bit patterns 120 can be overlapped, and the third on crystal grain is to the 4th pair of bitmap in bit patterns 102 and the first conductive layer 12
Case 122 can be overlapped.The present invention can simultaneously be measured according to the overlapping cases to bit patterns on crystal grain 10 and the first conductive layer 12
The overlay errors of X-direction and Y-direction, to promote measurement efficiency.
After the completion of contraposition, electric conductor 14 can rely on the engagement pad of low temperature ultrasonic or anisotropic conductive adhesive paste connection crystal grain 10
16 and first conductive layer 12 the first conductive pattern 123, generated in high temperature process to avoid crystal grain 10 and the first conductive layer 12
Thermally expand and/or reduce reliability.
In the present embodiment, it is micro- can be greater than or equal to 20 by first between of bit patterns 100 distance D1 with the first engagement pad 16a
Rice and it is less than or equal to 200 microns so that measurement equipment is overlapping with second pair of bit patterns 120 for first pair of bit patterns 100
Situation has preferable identification.Similarly, between bit patterns 102, the distance D2 with the second engagement pad 16b can be greater than or equal to third
20 microns and it is less than or equal to 200 microns so that measurement equipment is for third to bit patterns 102 and the 4th pair of bit patterns 122
Overlapping cases have preferable identification.It should be noted that distance D1, D2 above-mentioned can by center to center or while to while mode
It measures.
A to Fig. 3 C is please referred to Fig.3, Fig. 3 A are another schematic diagrames of first pair of bit patterns 100 and second pair of bit patterns 120,
Fig. 3 B are another schematic diagrames of first pair of bit patterns 100 and second pair of bit patterns 120, and Fig. 3 C are first pair of bit patterns 100 and
Another schematic diagram of two pairs of bit patterns 120.
As shown in Fig. 3 A to Fig. 3 C, the shape of first pair of bit patterns 100 and second pair of bit patterns 120 can be according to practical application
And have different designs, as long as first pair of bit patterns 100 and second pair of bit patterns 120 can be overlapped with Y-direction in X-direction.
It should be noted that third can also have different set from the shape of the 4th pair of bit patterns 122 to bit patterns 102 according to practical application
Meter, details are not described herein.In addition, first pair of bit patterns 100 and third can be the extension of the circuit of crystal grain 10 to bit patterns 102
Section, and second pair of bit patterns 120 and the 4th pair of bit patterns 122 can be the extensions of section of the circuit of the first conductive layer 12, but
It is not limited.It should be noted that when the insufficient space on crystal grain 10, the present invention is also using the engagement pad 16 on crystal grain 10
As first pair of bit patterns 100 above-mentioned and third to bit patterns 102.
A to Fig. 4 C is please referred to Fig.4, Fig. 4 A are the schematic diagrames that test pattern 124 corresponds to an engagement pad 16, and Fig. 4 B are tests
Pattern 124 corresponds to another schematic diagram of an engagement pad 16, and Fig. 4 C are that two the another of engagement pad 16 of correspondence of test pattern 124 show
It is intended to.
In the present embodiment, the first conductive layer 12 above-mentioned may also include the test pattern 124 in Fig. 4 A to Fig. 4 C.This hair
It is bright test pattern 124 to be formed on the first conductive layer 12 when making the first conductive layer 12.In crystal grain 10 and the first conductive layer
After the completion of 12 engagements, the engagement pad 16 of crystal grain 10 can be electrically connected the test pattern 124 of the first conductive layer 12 by electric conductor 14.
Test pattern 124 in Fig. 4 A is two point form and is electrically connected an engagement pad 16.Test pattern 124 in Fig. 4 B is four-point
And it is electrically connected an engagement pad 16.Therefore, the present invention directly measures crystalline substance using the test pattern 124 on the first conductive layer 12
Electrical (for example, impedance) of grain 10 and the first conductive layer 12.In addition, as shown in Figure 4 C, the present invention can make test pattern 124 electrical
Two engagement pads 16 are connected, to test electrical (for example, voltage, electric current, impedance etc.) between two engagement pads 16.Confirming electricity
Property after there is no problem, then pressing mold is carried out to encapsulating structure 1, to promote the yield of encapsulating structure 1.
In the present embodiment, the engagement pad 16 being electrically connected with test pattern 124 can be the first engagement pad above-mentioned
16a, but not limited to this.In addition, test pattern 124 can be the extension of section of the engagement pad on the first conductive layer 12.It is preferred that
The line width on ground, test pattern 124 is smaller than 20 microns, and the line length of test pattern 124 can be more than 50 microns.In addition, first connects
The area of touch pad 16a can be greater than or equal to 400 square microns and be less than or equal to 106Square micron, and the face of test pattern 124
Product can be greater than or equal to 400 square microns and be less than or equal to 106Square micron.
Referring to FIG. 5, Fig. 5 is the sectional view of the encapsulating structure 1' of another embodiment of the present invention.Encapsulating structure 1' with it is aforementioned
Encapsulating structure 1 main difference in place of be, encapsulating structure 1' further includes a second insulating layer 17 and one second conductive layer
18.As shown in figure 5, the second conductive layer 18 is between crystal grain 10 and the first conductive layer 12, and electric conductor 14 connect crystal grain 10 with
Second conductive layer 18.In other words, crystal grain 10 is engaged with the second conductive layer 18, and second pair of bit patterns 120 and the 4th pair of bitmap
Case 122 is located at the first conductive layer 12 of 18 lower section of the second conductive layer.Second insulating layer 17 includes one second opening 170, and second
Conductive layer 18 further includes one second conductive pattern 180, wherein the second conductive pattern 180 is located at the second opening 170.In the present embodiment
In, can the second opening 170 first be formed in second insulating layer 17, then the second conductive pattern 180 is inserted into the second opening 170.At this
In embodiment, electric conductor 14 can rely on the engagement pad 16 and the second conduction of low temperature ultrasonic or anisotropic conductive adhesive paste connection crystal grain 10
Second conductive pattern 180 of layer 18 generates thermal expansion and/or drop to avoid crystal grain 10 and the second conductive layer 18 in high temperature process
Low reliability.In addition, the first conductive layer 12 and the second conductive layer 18 can be the reassignment layers on circuit board.
Fig. 6 A to Fig. 6 I are please referred to, Fig. 6 A to Fig. 6 I are the processing procedure schematic diagrames of the encapsulating structure 1 in Fig. 1.First, in glass
Release layer 22 is formed on substrate 20, as shown in Figure 6A.Then, weld pad 24 is formed on release layer 22, as shown in Figure 6B.Then,
Third insulating layer 26 is formed on release layer 22, and forms third opening 260 in third insulating layer 26, as shown in Figure 6 C.Then,
Third conductive pattern 280 is inserted into third opening 260, and forms the second conductive pattern 180 on third insulating layer 26, such as Fig. 6 D
It is shown.Then, second insulating layer 17 is formed on third insulating layer 26, as illustrated in fig. 6e.Then, the shape in second insulating layer 17
The first opening 110 is formed at the first insulating layer 11, and in the first insulating layer 11, as fig 6 f illustrates.Then, by the first conductive pattern
123 the first openings 110 of filling, and second pair of bit patterns 120 and the 4th pair of bit patterns 122 are formed on the first insulating layer 11, such as
Shown in Fig. 6 G.Then, electric conductor 14 is formed on the first conductive pattern 123, as shown in figure 6h.Then, first pair of bitmap is utilized
100, second pairs of bit patterns 120 of case, third carry out crystal grain 10 and the first conductive layer to bit patterns 102 and the 4th pair of bit patterns 122
12 contraposition engages crystal grain 10 with the first conductive layer 12.Thereby, you can complete the manufacture of encapsulating structure 1.
Therefore, according to preceding solution, encapsulating structure of the invention at least has following advantages and advantageous effect：This hair
Bright to be respectively set to bit patterns on crystal grain and conductive layer, therefore, the present invention can carry out crystal grain and conductive layer using to bit patterns
Contraposition.After contraposition, crystal grain on conductive layer to bit patterns i.e. can be overlapped.The present invention can be according on crystal grain and conductive layer
To the overlapping cases of bit patterns, while the overlay errors of X-direction and Y-direction are measured, to promote measurement efficiency.In addition, of the invention
Test pattern can be formed on the electrically conductive when making conductive layer.After the completion of crystal grain is engaged with conductive layer, using conductive layer
On test pattern directly measure the electrical of crystal grain and conductive layer.It is carried out after confirming that electrically there is no problem, then to encapsulating structure
Pressing mold, to promote the yield of encapsulating structure.
Described above to be merely exemplary for the purpose of the present invention, and not restrictive, those of ordinary skill in the art understand,
In the case where not departing from spirit and scope defined by claim, can many modifications may be made, variation or equivalent, but will all fall
Enter within protection scope of the present invention.
Claims (10)
1. a kind of encapsulating structure, which is characterized in that the encapsulating structure includes：
One crystal grain, including one first pair of bit patterns；
One first insulating layer, including one first opening；And
One first conductive layer, including one first conductive pattern and one second pair of bit patterns, first conductive pattern are located at described
First opening, second pair of bit patterns are located on first insulating layer；
Wherein, first pair of bit patterns setting corresponding with second pair of bit patterns.
2. encapsulating structure as described in claim 1, which is characterized in that the crystal grain further includes a third to bit patterns, described
First conductive layer further includes one the 4th pair of bit patterns, and the 4th pair of bit patterns are located on first insulating layer, and described
The setting corresponding with the 4th pair of bit patterns of three pairs of bit patterns.
3. encapsulating structure as described in claim 1, which is characterized in that the encapsulating structure further includes an electric conductor, and described
Electric conductor connects the crystal grain and first conductive layer.
4. encapsulating structure as claimed in claim 3, which is characterized in that the electric conductor is led by low temperature ultrasonic or anisotropy
Crystal grain described in electric glue connection and first conductive layer.
5. encapsulating structure as described in claim 1, which is characterized in that the encapsulating structure further includes an electric conductor and one
Two conductive layers, second conductive layer between the crystal grain and first conductive layer, and the electric conductor connection described in
Crystal grain and second conductive layer.
6. encapsulating structure as claimed in claim 5, which is characterized in that the electric conductor is led by low temperature ultrasonic or anisotropy
Crystal grain described in electric glue connection and second conductive layer.
7. encapsulating structure as described in claim 1, which is characterized in that the crystal grain further includes one first engagement pad, and described
One engagement pad adjacent to first pair of bit patterns, and first between of bit patterns with first engagement pad at a distance from be more than or
Equal to 20 microns and it is less than or equal to 200 microns.
8. encapsulating structure as claimed in claim 7, which is characterized in that the area of first engagement pad is greater than or equal to 400
Square micron and be less than or equal to 106Square micron.
9. encapsulating structure as described in claim 1, which is characterized in that first conductive layer further includes a test pattern, institute
The area for stating test pattern is greater than or equal to 400 square microns and is less than or equal to 106Square micron.
10. encapsulating structure as described in claim 1, which is characterized in that the crystal grain further includes one first engagement pad, and described
One conductive layer further includes a test pattern, and first engagement pad is electrically connected the test pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/889,216 US20180254257A1 (en) | 2017-03-06 | 2018-02-06 | Package structure and method of manufacturing package structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762467254P | 2017-03-06 | 2017-03-06 | |
| US62/467,254 | 2017-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108538812A true CN108538812A (en) | 2018-09-14 |
Family
ID=63488687
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710702304.6A Pending CN108538812A (en) | 2017-03-06 | 2017-08-16 | Encapsulating structure |
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| CN101297394A (en) * | 2005-11-10 | 2008-10-29 | 株式会社瑞萨科技 | Semiconductor device manufacturing method and semiconductor device |
| CN101800215A (en) * | 2009-02-11 | 2010-08-11 | 日月光半导体制造股份有限公司 | Wireless communication module package structure |
| CN102263084A (en) * | 2010-05-31 | 2011-11-30 | 海力士半导体有限公司 | Semiconductor chip and semiconductor package with stack chip structure |
| US20140252604A1 (en) * | 2013-03-07 | 2014-09-11 | Tohoku-Microtec Co., Ltd | Stacked device and method of manufacturing the same |
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2017
- 2017-08-16 CN CN201710702304.6A patent/CN108538812A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101297394A (en) * | 2005-11-10 | 2008-10-29 | 株式会社瑞萨科技 | Semiconductor device manufacturing method and semiconductor device |
| CN101800215A (en) * | 2009-02-11 | 2010-08-11 | 日月光半导体制造股份有限公司 | Wireless communication module package structure |
| CN102263084A (en) * | 2010-05-31 | 2011-11-30 | 海力士半导体有限公司 | Semiconductor chip and semiconductor package with stack chip structure |
| US20140252604A1 (en) * | 2013-03-07 | 2014-09-11 | Tohoku-Microtec Co., Ltd | Stacked device and method of manufacturing the same |
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Application publication date: 20180914 |