CN108511443A - Address wire contains the compact three-dimensional storage of semiconductor portions - Google Patents
Address wire contains the compact three-dimensional storage of semiconductor portions Download PDFInfo
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- CN108511443A CN108511443A CN201710105760.2A CN201710105760A CN108511443A CN 108511443 A CN108511443 A CN 108511443A CN 201710105760 A CN201710105760 A CN 201710105760A CN 108511443 A CN108511443 A CN 108511443A
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- address wire
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/50—ROM only having transistors on different levels, e.g. 3D ROM
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Abstract
The present invention proposes a kind of compact three-dimensional storage（3D‑MC）.It its storage array and is formed in same accumulation layer higher than substrate decoder stage.In memory device in storage array, the lap of x address wires and non-overlapping part are good conductor.In the decoding device of decoder stage, the non-overlapping part of x address wires is still good conductor, and lap is semiconductor.
Description
Technical field
The present invention relates to integrated circuit memory fields, more precisely, being related to three-dimensional storage（3D-M）.
Background technology
Three-dimensional storage（3D-M）It is a kind of monomer（monolithic）Semiconductor memory, it contains multiple be stacked with
Storage member（Also referred to as memory device）.3D-M includes 3 D ROM（3D-ROM）Memory is read with three-dimensional random
（3D-RAM）.3D-ROM can be further divided into three-dimensional masking film program read-only memory（3D-MPROM）Only with three-dimensional electric programming
Read memory（3D-EPROM）.Based on its programming mechanism, 3D-M can contain memristor, resistive random-
access memory（RRAM or ReRAM）、phase-change memory（PCM）、programmable
metallization memory（PMM）Or conductive-bridging random-access memory（CBRAM）
Deng.
United States Patent (USP) 5,835,396 discloses a kind of 3D-M（3D-ROM）（Figure 1A）.It contain semi-conductive substrate 0 and
Substrate circuitry 0K disposed thereon.The dielectric 0d covering substrate circuitries 0K of one planarizing layers.On insulating medium layer 0d
The first accumulation layer 10 is formed, then forms the second accumulation layer 20 on the first accumulation layer 10.First and second accumulation layers 10,
20 are coupled by contacting access opening 13a, 23a with substrate circuitry 0K.Each accumulation layer（Such as 10,20）Contain a plurality of top address line
（That is y address wires, such as 12a-12d, 22a-22d）, a plurality of bottom address wire（That is x address wires, such as 11a, 21a）It is located at top ground with multiple
The memory device of location line and bottom address wire infall（Such as 1aa-1ad, 2aa-2ad）.
Each accumulation layer（Such as 20）Contain an at least storage array（Such as 200A）.Storage array 200A is in accumulation layer 20
At least share the set of all memory device 2aa-2ad of an address wire.In a storage array 200A, all address wires
21a, 22a-22d are continuous；In adjacent storage array, address wire is discontinuous.On the other hand, a 3D-M chip contains
Multiple memory blocks 100.Structure in Figure 1A is exactly a part for memory block 100.100 uppermost accumulation layer of memory block only contains
One storage array 200A.In other words, in the most top accumulation layer 20 of memory block 100, all address wires 21a, 22a-22d are equal
It is continuous, edge is in the adjacent edges of memory block 100.
Each memory device is a kind of Two-port netwerk device containing at least two states.Common memory device includes two poles
Pipe or class diode component.Particularly, memory device 1aa contains a programmable film and a diode film（Figure 1A）.It is programmable
The state of film can change in the fabrication process or after the completion of manufacture；The electric characteristic and diode-like of diode film are seemingly.Pay attention to
It arrives, programmable film and diode can be merged into a tunic（Referring to United States Patent (USP) 8,071,972）.The symbol of memory device 1aa
It is indicated in fig. ib with diode and capacitance.Since memory device 1aa is formed in the infall of address wire 11a, 12a, storage
Array 100A is a crosspoint array.
In the present specification, diode refers to any Two-port netwerk device with the following characteristics：When the number of its applied voltage
When value is opposite with read voltage less than the direction of read voltage or applied voltage, resistance is much larger than its resistance under read voltage.Two
Pole pipe is otherwise known as quasi- conductive membrane in United States Patent (USP) 5,835,396.The example of diode includes semiconductor diode（Such as p-i-
N silicon diodes etc., referring to works such as Crowley《512Mb PROM with 8 Layers of Antifuse/Diode
Cells》, International Solid State Circuits Conference in 2003, Figure 16 .4.1）And MOS diode（Such as titanium oxide diode, oxidation
Nickel diode etc., referring to works such as Chevallier《A 0.13um 64Mb Multi-Layered Conductive Metal-
Oxide Memory》, International Solid State Circuits Conference in 2010, Figure 14 .3.1）Deng.Although the metal oxide in Chevallier
Film has almost symmetrical I-V characteristic（Metal oxide film can be conductive in positive and negative both direction）, since its I-V characteristic is
Exponential type, which is still considered as diode.
Substrate circuitry 0K contains the first and second decoders 14,24 of respectively the first and second accumulation layers 10,20 service.
Each decoder 14,24 contains multiple decoding devices.Decoding device is the basic building block of decoder 14,24, it is storage array
Realization is at least partially decoded function.Decoding device contains a conduction mode and a blocking mode：In the conduction mode, with decoder
The associated address wire energy conducting electric current of part；In blocking mode, which is unable to conducting electric current.Common decoding device includes crystalline substance
Body pipe or transistorlike device, they are typically all three port devices.Decoding device is also referred to as in other patent application
Switching device.
The personage for being familiar with this profession knows that the manufacturing process of diode is simpler than transistor very much.In order to reduce tradition
The manufacturing cost of 3D-M only forms memory device in each accumulation layer 10（Diode or class diode component）, without shape
At decoding device（Transistor or transistorlike device）.Due to can not achieve decoding in accumulation layer 10,20, all decoding functions are all
It is formed in substrate circuitry 0K, contact access opening 13a and substrate circuitry 0K must be used alone by oneself in every address wire 11a
Coupling.In other words, contact access opening 13a cannot share between address wire.In this case, contact access opening 13a,
The period of 13c（pitch）pcMost multipotency is loosened to twice of address wire period p（pc=2p）.This needs to carry out contact access opening
Interlaced arrangement（Fig. 1 C）：Contact access opening 13a, 13c of x address wires 11a, 11c are formed in the right（The directions+x）, and they are adjacent
Contact access opening 13b, 13d of x address wires 11b, 11d are then formed in the left side（The directions-x）（It is not drawn into）.Here, the period refers to two
A adjacent contact access opening（Or two address wires）The distance between center.In most cases, address wire period p is address wire
Twice of line width f（p=2f）.It is obvious that the size d of contact access openingcWith spacing gcIt is twice of x address wire line widths f（dc=2f、
gc=2f）（Fig. 1 D）.Even if in this way, since address wire line width f can be accomplished the half of minimum lithographic dimensions F by the prior art（f=
F/2）Or it is lower, it contacts the size of access opening and is spaced still equal to minimum lithographic dimensions F（dc=F、gc=F）.Due to contacting access opening
Need high-resolution（F nodes）Mask plate, this will lead to higher manufacturing process cost.
In the present specification, all contact access openings of an accumulation layer form one group of contact access opening（Fig. 1 E）.For example,
All contact access openings of accumulation layer 10（Such as 13a-13z）The first contact access opening of composition group 13, all contacts of accumulation layer 20
Access opening（Such as 23a-23z）The second contact access opening of composition group 23.Since each accumulation layer is required for the contact of own logical
Road hole group（Figure 1A）, a multigroup contact access opening of 3D-M needs containing multiple accumulation layers, this can further increase manufacture work
Skill cost.
Due to contacting the spacing very little of access opening（gc=2f）, contact access opening（Such as 13a, 13c, 13e）For dense channels
Hole.They constitute the fence for being difficult to pass through together, and the interconnection line of substrate circuitry 0K is made to cannot pass through its interval 04g（Fig. 1 D）.
This causes many restrictions to the wiring of substrate circuitry 0K.Due to dense channels hole by the first and second decoders 14,24 completely every
From the second decoder 24 cannot share any component with the first decoder 14, it must be a complete decoder（Fig. 1 E）.
This requires the x address wires 21a of accumulation layer 20 to extend very long range LpxTo reach contact access opening 23a（Figure 1A）.Long LpxIt will reduce
Array efficiency reduces storage density.Related LpxDetails paragraph below in further disclose.
The extended distance L of x address wirespxThe x peripheral lengths that are otherwise known as Lpx, it is defined as x address wires 21a from storage array
The last one memory device 2ad of 200A to contact access opening 23a（Or the edges x address wire 21a）Length（Figure 1A）.Due to
Highest accumulation layer 20 has longest address wire and determines the size of memory block 100（footprint）, LpxIt need to only be deposited in highest
Defined in reservoir 20.Y peripheral lengths LpyIt also can similar definition.For a storage array 200A containing N*N, the addresses x
The effective length L of line 21am（It is used for the address line length of storage）It is N*p, and its total length is Lt=N*p+2Lpx.Correspondingly,
X efficiency Ex（Percentage i.e. in x address wires 21a total lengths for storage）For：Ex=Lm/Lt=(1+2Lpx/N/p)-1.Array efficiency
EA（Percentage in i.e. entire storage array 200A for storage）For：EA=Ex*Ey= (1+2Lpx/N/p) -1 (1+2Lpy/N/p
) -1。
In order to accommodate entire decoder 24 between access opening 13a and 23a contacting, the x address wires 21a in accumulation layer 20 must
The width W of at least decoder 24 must be extended in the x directionD, i.e. Lpx>WD（Figure 1A and Fig. 1 E）.Y address wires 22a is also required to similar
Extension.Long LpxWith long LpyThe size of storage array will be greatly increased, array efficiency is reduced and reduces storage density.
Other than leading to drawbacks described above, three dimensional integrated circuits are returned in dense channels hole（3D-IC）Realization bring very much
It is difficult.When the line width of transistor is close to its physics limit, 3D-IC is conventional two-dimensional integrated circuit（2D-IC）It is natural extension.
It can be used for being formed the circuit unit of such as processor etc, 3D- since the accumulation layer of 3D-M is not take up Substrate Area, its substrate
M is most suitable for realizing 3D-IC, such as network-on-chip based on 3D-M（SoC）.But since dense channels hole cuts off into substrate
The wiring of multiple area of isolation, substrate circuitry becomes extremely difficult.
Invention content
The main object of the present invention is to reduce three-dimensional storage（3D-M）Cost.
It is another object of the present invention to increase the design flexibility of 3D-M substrate circuitries.
It is another object of the present invention to help to realize three dimensional integrated circuits（3D-IC）.
It is another object of the present invention to help to realize the network-on-chip based on 3D-M（SoC）.
It is another object of the present invention to simplify the design of 3D-M decoders.
It is another object of the present invention to improve the array efficiency of 3D-M.
It is another object of the present invention to improve the storage density of 3D-M.
In order to realize that these and other purpose, the present invention propose a kind of compact three-dimensional storage（3D-MC）.The 3D-MC
Containing there are one the accumulation layers stacked on a semiconductor substrate.The accumulation layer contains an at least storage array and at least one and is higher than substrate
Decoder stage.Storage array contains multiple memory devices, and each memory device contains a diode or class diode component, it is usually
It is a two end device for being formed in an x address wires and a y address wire intersections.Contain multiple decodings higher than substrate decoder stage
Device, each decoding device contain a transistor or transistorlike device, it be typically one be formed in an x address wires and one control
Line（A kind of special y address wires, for decoding）Three port devices of intersection.Decoding device provides at least for storage array
Partial decoding of h function.The example of decoding device includes mosfet transistor or JFET.Decoding device has conduction mode and blocks mould
Formula：In conduction mode, decoding device is connected and electric current is allowed to be flowed in x address wires；In blocking mode, decoding device disconnects simultaneously
Electric current is blocked to be flowed in x address wires.
Although memory device and decoding device are all located at two address wire infalls, they have different electrical characteristics.
In memory device, lap and non-overlapping the part electrical characteristic having the same of x address wires and y address wires：They are
For good conductor.On the other hand, in decoding device, x address wires have different from the lap of control line and non-overlapping part
Electrical characteristic：Although non-overlapping part is still good conductor, lap is only semiconductor.
Can be decoder stage in layer, room decipherer grade or their combination higher than substrate decoder stage.Decoder stage is to same in layer
Address wire in one accumulation layer is decoded, and the address wire in accumulation layer same in this way can share same contact access opening.Layer
Between decoder stage the address wire in different accumulation layers is decoded, the address wire in accumulation layers different in this way can share same connect
Touch access opening.The shared size and spacing that can increase contact access opening, contact access opening at this moment is sparse channels hole（Relatively
In the prior art）.Sparse channels hole can reduce the group number of contact access opening（As an extreme example, eight accumulation layers can be total to
Enjoy one group of contact access opening）, reduce manufacturing process cost.Further, since sparse channels hole allows interconnection line to pass through, difference storage
The decoder of layer may be implemented to share.This can shorten peripheral length Lpx、Lpy, improve array efficiency（Up to ~ 95%）, and increase
Storage density.Importantly, sparse channels hole makes 3D-M and substrate circuitry component（Such as processor）Between be integrated into can
Can, this is to three dimensional integrated circuits（3D-IC）- for example say, the network-on-chip based on 3D-M（SoC）- realization have it is extremely heavy
The meaning wanted.
In order to avoid introducing extra processing step, decoding device is preferably provided with very simple structure, and key is in x
One section of semiconductor is formed in the lap of address wire and control line.In the first embodiment, x address wires contain the half of heavy doping
Conductor material.The lap of x address wires and control line is set to become semi-conducting material by counter-doping.In second embodiment
In, address wire contains a low layer semiconductive thin film and a high-rise conductor thin film.In the lap of x address wires and control line,
High-rise conductor thin film is etched away, low layer semiconductive thin film has been left behind.In the third embodiment, address wire contains metal material.
In the lap of x address wires and control line, metal material is etched away, and fill out with semi-conducting material.
Description of the drawings
Figure 1A is a kind of three-dimensional storage in the prior art（3D-M）Sectional view；Figure 1B is the circuit diagram of accumulation layer 10；
Fig. 1 C are the top views of accumulation layer 10；Fig. 1 D be in Fig. 1 C structure along the sectional view of AA '；Fig. 1 E are the circuit blocks of substrate circuitry 0K
Figure, it includes the decoder 14,24 of accumulation layer 10,20.
Fig. 2A is the first compact three-dimensional storage（3D-MC）The circuit diagram of middle accumulation layer 10, it includes being solved in one layer
Code grade；Fig. 2 B are the circuit block diagrams of its substrate circuitry 0K；Fig. 2 C are the 3D-MCSectional view；Fig. 2 D are the top views of accumulation layer 10
Figure；Fig. 2 E be in Fig. 2 D structure along the sectional view of BB '.
Fig. 3 A are second of 3D-MCSectional view, it include a room decipherer grade；Fig. 3 B are the top views of accumulation layer 10；
Fig. 3 C are the circuit diagrams of its accumulation layer 10；Fig. 3 D are the circuit diagrams of its accumulation layer 20.
Fig. 4 A are the third 3D-MCSectional view, it include one higher than substrate share decoder stage；Fig. 4 B are its accumulation layers
10,20 circuit diagram.
Fig. 5 is the sectional view of the first MOSFET type decoding device 3aa and a memory device 1aa.
Fig. 6 A and Fig. 6 B describe two kinds of methods for forming the first MOSFET type decoding device 3aa.
Fig. 7 is the sectional view of second MOSFET type decoding device 3aa and a memory device 1aa.
Fig. 8 A- Fig. 8 D describe to form four steps of second of MOSFET type decoding devices 3aa.
Fig. 9 is the sectional view of the third MOSFET type decoding device 3aa and a memory device 1aa.
Figure 10 A- Figure 10 C describe to form three steps of the third MOSFET type decoding device 3aa.
Figure 11 A are the sectional views of the first JFET type decoding device 3aa；Figure 11 B describe to form this kind of JFET type decoder
The method of part.
Figure 12 A are the sectional views of second of JFET type decoding devices 3aa；Figure 12 B describe to form this kind of JFET type decoder
The method of part.
Figure 13 A are the sectional views of the third JFET type decoding device 3aa；Figure 13 B describe to form this kind of JFET type decoder
The method of part.
Figure 14 A- Figure 14 C are the sectional views of three kinds of MOSFET types decoding devices and 4 3D-MPROM memory devices.
Figure 15 is a kind of 3D-MCThe sectional view of accumulation layer, it includes a memory device, a decoding device and an invalidator
Part.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.x（Such as x address wires）And y（Such as y address wires）Only indicate relative direction：X address wires and y address wires only indicate this two
Address wire direction is different.
Specific implementation mode
Figure 15 is described first.The figure illustrates a kind of 3D-MCAccumulation layer 10, it includes a memory device 1aa, a decoder
The invalid device 3ab of part 3aa and one.Accumulation layer 10 is stacked in semiconductor substrate 0, it is by contacting access opening 13a and substrate coupling
It closes.Accumulation layer 10 also contains an at least storage array 100A and one and is higher than substrate decoder stage 100P.Storage array 100A contains more
X address wires 11a, a plurality of y address wires 12a and multiple memory device 1aa.Every x address wires 11a extends from storage array 100A
To decoder stage 100P.Every y address wires 12a intersects with x address wires 11a.Each memory device 1aa is one and is located at x address wires
The two end device of 11a and y address wire 12a infalls, it contains a diode or class diode component, and by symbol（a）Table
Show.Memory device 1aa includes one layer of memory films 130, which contains a programmable film and a diode film.It can
Programming the state of film can change in the fabrication process or after the completion of manufacture.Diode film has following electric characteristic：When outside it
When alive numerical value is opposite with read voltage less than the direction of read voltage or applied voltage, resistance is much larger than it under read voltage
Resistance.In certain embodiments, memory films 130（Or a part of memory films 130）With being naturally formed at x address wires and y
The infall of location line.At this moment, memory device 1aa is without there are one individual memory films 130.In some other embodiment,
Memory device 1aa is free of may be programmed film or diode film there are one individual.
In the prior art, all decoder stages are formed in substrate in the decoder of storage array 100A.With existing skill
Art is different, is located in same accumulation layer 10 higher than substrate decoder stage 100P and storage array 100A.Higher than substrate decoder stage 100P
Contain an at least control line（A kind of special y address wires, for decoding）A 17a and decoding device 3aa.Every control line 17a with
A plurality of x address wires 11a intersections.Decoding device is three port devices positioned at x address wires 11a and control line 17a infalls, it is wrapped
Transistor or transistorlike device are included, and by symbol（c）It indicates.Decoding device 3aa is located at memory device 1aa and contact access opening
Between 13a, at least partly decoding function is provided for storage array 100A.The example of decoding device include mosfet transistor or
JFET.Decoding device has conduction mode and blocking mode：In conduction mode, decoding device is connected and allows electric current in x address wires
Middle flowing；In blocking mode, decoding device disconnects and electric current is blocked to be flowed in x address wires.
Although memory device 1aa and decoding device 3aa are all located at two address wire infalls, they have different electrical
Characteristic.In memory device 1aa, the lap 140 and non-overlapping part 140A, 140B of x address wires 11a and y address wires 12a
Electrical characteristic having the same：They are good conductor（They have identical structure, and use same material）.On the other hand,
In decoding device 3aa, the lap 160 and non-overlapping part 160A, 160B of x address wires 11a and control line 17a have not
Same electrical characteristic：Although the non-overlapping part 160A, 160B is still good conductor, lap 160 is only semiconductor.
It is higher than in substrate decoder stage 100P above-mentioned, in addition to the infall shape in x address wires 11a and the first control line 17a
Outside at decoding device 3aa, also an invalid device 3ab is formd in the infall of x address wires 11a and the second control line 17b.With
Decoding device 3aa is different, and the lap 190 and non-overlapping 190A, 190B of invalid device 3ab are good conductor.This and storage
Device 1aa is similar.But the operation of invalid device 3ab is different from memory device 1aa：Invalid device 3ab is usually reverse bias
, electric current flows in x address wires 11a when function is only, and x address wires and the second control line 17b are isolated.Except this it
Outside, invalid device 3ab is without any function.
Fig. 2A-Fig. 2 E describe the first compact three-dimensional storage（3D-MC）, it includes decoder stage in one layer.The 3D-
MCContaining there are two the accumulation layers 10,20 being stacked on substrate 0（Fig. 2 C）.Accumulation layer 10 contains decoding in storage array 100A and layer
Grade 100P（Referring to the top view of circuit diagram and Fig. 2 D in Fig. 2A）.Storage array 100A contain a plurality of x address wires 11a-11h,
A plurality of y address wires 12a-12d and multiple memory device 1aa-1ad（Fig. 2A）.X address wires are extended to from storage array 100A
Decoder stage 100P in layer, and it is divided into several right, each pair of x address wires share same contact in layer with the help of decoder stage 100P logical
Road hole（It is coupled with same contact access opening, Fig. 2A and Fig. 2 D）.For example, the first x address wires of x address wires 11a, 11c composition
To shared first contact access opening 13ac；2nd x address wires of x address wires 11e, 11g composition are to shared second contact access opening
13eg。
Decoder stage 100P selects an address wire from two address wires of same accumulation layer in layer.In this embodiment,
Decoder stage 100P contains two control line 17a, 17b in layer, and the first decoding device 3aa is formed in control line 17a and x address wire
The infall of 11a, the second decoding device 3cb are formed in the infall of control line 17b and x address wire 11c.It is noted that in the addresses x
That the infall of line 11a and control line 17b are formed is invalid device 3ab.Based on the voltage on control line 17a, 17b, contact is logical
Road hole 13ac may be selected to couple with x address wires 11a or 11c.When Voltage On state decoding device 3aa, the control line on control line 17a
When voltage on 17b disconnects decoding device 3cb, contact access opening 13ac is coupled with x address wires 11a；Electricity on control line 17a
When breaking out the Voltage On state decoding device 3cb on decoding device 3aa, control line 17b, contact access opening 13ac and x address wires
11c is coupled.Contact the shared of access opening makes its dimension DcWith spacing GcIt doubles（Dc=4f=2p, Gc=4f=2p）（Fig. 2 D）, and reduce
Their manufacturing process cost.
Substrate circuitry 0K contains the common decoder 06 of accumulation layer 10,20（Fig. 2 B）.The contact channel of it and accumulation layer 10
Contact access opening 23ac, 23eg coupling of hole 13ac, 13eg and accumulation layer 20.It is noted that will contact access opening 23ac（Or
23eg）The interconnection line 06i coupled with common decoder 06 must be by contacting the gap 06G between access opening 13ac, 13eg（Figure
2B and Fig. 2 E）.The prior art is due to the spacing g between contact access opening 13a, 13cc（=1p）Too small, common decoder 06 can not
It realizes, each accumulation layer（Such as 10）Individual decoder must be used（Such as 24）（Fig. 1 C and Fig. 1 E）.With spacing Gc（=2p）Add
Greatly, will contact the interconnection line 06i that are coupled with common decoder 06 of access opening 23ac can by contact access opening 13ac, 13eg it
Between gap 06G（Fig. 2 E）.Therefore, most of decoder 24 can move on to other one side of contact access opening group 13, and with deposit
The decoder 14 of reservoir 10 is shared.Compared with Figure 1A, x peripheral lengths L in Fig. 2 CpxReduce very much, therefore memory block 100 has more
High array efficiency.
Fig. 3 A- Fig. 3 D indicate second of 3D-MC, it includes a room decipherer grade.The 3D-MCContaining there are two be stacked on substrate 0
On accumulation layer 10,20（Fig. 3 A）.First part 110P of the accumulation layer 10 containing storage array 100A and room decipherer grade（Fig. 3 B
With Fig. 3 C）.Storage array 100A contains a plurality of x address wires 11a-11h, a plurality of y address wires 12a-12d and multiple memories
Part 1aa-1ad（Fig. 2A）.Second part 210P of the accumulation layer 20 containing storage array 200A and room decipherer grade（Fig. 3 D）.Storage
Array 200A contains a plurality of x address wires 21a-21h, a plurality of y address wires 22a-22d and multiple memory device 2aa-2ad.It deposits
Reservoir 10,20 shares same contact access opening group.Particularly, the x address wires in different accumulation layers 10,20 are divided into several right,
Each pair of x address wires share same contact access opening, i.e., are coupled with same contact access opening（Fig. 3 A）.For example, x address wires 11a,
First x address wires pair of 21a compositions, and shared first contact access opening 5a；2nd x address wires of x address wires 11c, 21c composition
It is right, and shared second contact access opening 5c（Fig. 3 C and Fig. 3 D）.
Room decipherer grade selects an address wire from two address wires of different accumulation layers.In this embodiment, interlayer
The first part 110P of decoder stage contains the first control line 17, and decoding device 3a is formed in the first control line 17 and x address wires 11a
Infall；Second part 210P contains the second control line 27, and decoding device 4a is formed in the second control line 27 and x address wires
The infall of 21a.Based on the voltage on control line 17,27, contact access opening 5a selectively with x address wire 11a or 21a couplings
It closes.For example, when the Voltage On state decoding device 3a on control line 17, the voltage on control line 27 disconnect decoding device 4a, connect
Access opening 5a is touched to couple with the x address wires 11a in accumulation layer 10；When the voltage on control line 17 disconnects decoding device 3a, control
When Voltage On state decoding device 4a on line 27, contact access opening 5a is coupled with the x address wires 21a in accumulation layer 20.In interlayer
With the help of decoder stage, the common decoder 08 in accumulation layer 10,20 shared substrate circuitry 0K.Due to the peripheral length in Fig. 3 A
LpxThan reducing much in Figure 1A, memory block 100 has higher array efficiency.
The shared contact access opening of accumulation layer can greatly simplify 3D-MCManufacturing process.Figure 1A in the prior art,
Since each accumulation layer has its respective contact access opening, it needs to form many group contact access openings.Reality in figure 3 a
It applies in example, all accumulation layers（Such as all eight accumulation layers）Same group of contact access opening can be shared.The group contacts access opening can
With in all accumulation layers（10 and 20）It is once formed after formation, therefore manufacturing process cost can be reduced.Particularly, when all storages
Layer（10 and 20）After formation, it is being close to x address wires（11a and 21a）End make a call to a contact hole, and fill out with conductor material.In this way,
It may be implemented to being in electrical contact while x address wires in all accumulation layers.
Fig. 4 A and Fig. 4 B indicate the third 3D-MC, it includes one higher than the shared decoder stage of substrate.The 3D-MCContaining there are two heaps
The accumulation layer 10,20 being stacked on substrate 0（Fig. 4 A）.These accumulation layers 10,20 are staggeredly their i.e. shared y address wires 12a-
12d.Accumulation layer 10 contains multiple memory device 1aa-1ad；Accumulation layer 20 contains multiple memory device 2aa-2ad（Fig. 4 B）.
It is formed between accumulation layer 10,20 and shares decoder stage 120P, it is both decoder stage and room decipherer grade in layer.Shared decoder stage
120P contains two control lines 17x, 17y and multiple decoding device 3ax, 4ay etc..First decoding device 3ax is formed in control line
The infall of 17x and x address wires 11a；Second decoding device 4ay is formed in the infall of control line 17y and x address wire 21a.Base
Voltage on control line 17x, 17y, contact access opening 5a is with the x address wires 11a in the accumulation layer 10 or x in accumulation layer 20
Location line 21a is coupled.When the voltage on Voltage On state decoding device 3ax, the control line 17y on control line 17x disconnects decoding device
When 4ay, contact access opening 5a is coupled with x address wires 11a；When the voltage on control line 17x disconnects decoding device 3ax, control line
When Voltage On state decoding device 4ay on 17y, contact access opening 5a is coupled with x address wires 21a.
Various designs in Fig. 2A-Fig. 4 B are combined, a 3D-M with superelevation array efficiency may be implementedC.With
One 3D-M containing 8 stored interleaved layersC（Containing x address wires and the 4 layers of y address wires of being of five storeys）For.Along the directions+x, the 3D-MCContain
There is the control line of the control line and 5 room decipherer grades of decoder stage in 7 control lines, including 2 layers.Each contact access opening quilt
10 x address wires（5 layers of x address wires, every layer includes 2 x address wires）It is shared.Therefore, x peripheral lengths are Lpx=7PL+Pc=18p,
Wherein, PLIt is the period of control line（PL=2p, referring to Fig. 4 A）；PcIt is the period for contacting access opening（Pc=4p, referring to Fig. 2 D）.It is false
If array size is 1000*1000（That is N=1000）, x efficiency Ex=1/(1+2*18p/1000p) ≈96.4%.It, should along the directions+y
3D-MCControl line containing decoder stage in 2 layers, y peripheral lengths are Lpy=2PL+Pc=8p, y efficiency Ey=1/(1+2*8p/
1000p) ≈98.4%.Array efficiency is EA=Ex*Ey≈95%。
In 3D-MCIn, decoding device can be MOSFET（Fig. 5-Figure 10 C）Or JFET（Figure 11 A- Figure 13 B）.In order to realize
Decoding device, x address wires need to redesign.In the embodiment of Fig. 5-Fig. 6 B and Figure 11 A- Figure 11 B, x address wires contain weight
The semi-conducting material of doping.In the lap of x address wires and control line, make what it became to be lightly doped partly to lead by counter-doping
Body material.In the embodiment of Fig. 7-Fig. 8 D and Figure 12 A- Figure 12 B, x address wires contain a low layer semiconductive thin film and a height
Layer conductor thin film.In the lap of x address wires and control line, high-rise conductor thin film is etched away, and has been left behind low layer and has partly been led
Body thin film.In the embodiment of Fig. 9-Figure 10 C and Figure 13 A- Figure 13 B, x address wires contain metal material.In x address wires and control
The lap of line, metal material are etched away, and are filled out with semi-conducting material.
Fig. 5 is the sectional view of the first MOSFET type decoding device 3aa and memory device 1aa.Memory device 1aa is located at x
The infall of address wire 11a and y address wire 12a, it contains top electrode 120, storage film 130 and hearth electrode 110.Top electrode 120
It is a part of y address wires 12a.Hearth electrode 110 is a part of x address wires 11a, it contains the semi-conducting material of heavy doping,
With good electric conductivity.Decoding device 3aa is located at x address wires 11a and control line 17a infalls, it contain grid 170, in
Between film 180, Modulated Films 160 and source/drain 160A, 160B.Grid 170 is identical as the top electrode 120 of memory device 1aa, it is
A part of control line 17a.Intermediate coat 180 is isolated by grid 170 with Modulated Films 160.Modulated Films 160 are x address wires 11a and control
The lap of line 17a processed.It is semiconductor, and conductivity can pass through the voltage modulated on grid 17a.Source/drain 160A,
160B is the non-overlapping part of x address wires 11a and control line 17a, it is good conductor.
The present embodiment carries out counter-doping by the lap to x address wires 11a and control line 17a, make the part at
For semiconductor.Such as it says, x address wires（The hearth electrode 110 of memory device 1aa）It is the n-type semiconductor of heavy doping, Modulated Films
160 are reversed and are doped to low-doped n-type semiconductor.Correspondingly, decoding device 3aa is a depletion type MOS FET.
If adding sufficiently large negative voltage on control line 17a, Modulated Films 160 can block electric current in x address wires 11a.In addition, decoding
Device 3aa can also be enhanced MOSFET.
Fig. 6 A and Fig. 6 B describe two kinds of methods for forming the first MOSFET type decoding device 3aa.In the embodiment of Fig. 6 A
In, it is initially formed a hearth electrode 110 containing heavily-doped semiconductor, then forms hole 165 in photoresist 150, and to this
The hearth electrode 110 of 165 lower section of hole carries out counter-doping（The hearth electrode 110 at non-porous place is not reversed doping）.Remove photoresist
After 150, storage film 130 and intermediate coat 180 are formed on hearth electrode 110.Storage film 130 and hearth electrode 110 are etched with forming x
Location line 11a re-forms top electrode 120 and defines y address wires 12a and control line 17a.In this embodiment, each accumulation layer
It needs to carry out a counter-doping（Fig. 6 A）.In order to reduce manufacturing process cost, can all be formd in all accumulation layers 10,20
Counter-doping is carried out later（Fig. 6 B）.
Fig. 7 is the sectional view of second MOSFET type decoding device 3aa and memory device 1aa.It is similar with Fig. 5, memory
Part 1aa contains top electrode 120, storage film 130 and hearth electrode 110.Decoding device 3aa contains grid 170, intermediate coat 180, modulation
Film 160 and source/drain 160A, 160B.Unlike Fig. 5, the address wire 110 of memory device 1aa contains a low layer semiconductor
Film 116 and a high-rise conductor thin film 112；The Modulated Films 160 of decoding device 3aa contain only low layer semiconductive thin film 116.Phase
Ying Di, decoding device 3aa are a depletion type MOS FET.If adding sufficiently large negative voltage, Modulated Films on control line 17a
160 can block electric current in x address wires 11a.
Fig. 8 A- Fig. 8 D describe to form four steps of second of MOSFET type decoding devices 3aa.Low layer is initially formed partly to lead
Body thin film 116 and a high-rise conductor thin film 112（Fig. 8 A）, high-rise conductor is then removed at the position of decoding device 3aa 165
Film 112（Fig. 8 B）, storage film 130 is formed later and defines x address wires 11a（Fig. 8 C）.Finally, it forms top electrode 120 and determines
Adopted y address wires 12a and control line 17a（Fig. 8 D）.
Fig. 9 is the sectional view of the third MOSFET type decoding device 3aa and memory device 1aa.It is similar with Fig. 5, memory
Part 1aa contains top electrode 120, storage film 130 and hearth electrode 110.Decoding device 3aa contains grid 170, intermediate coat 180, modulation
Film 160 and source/drain 160A, 160B.Unlike Fig. 5, hearth electrode 110 contains metal material, and the tune of decoding device 3aa
Film 160 contains semi-conducting material.Correspondingly, decoding device 3aa is a depletion type MOS FET.If on control line 17a
In addition sufficiently large negative voltage, Modulated Films 160 can block electric current in x address wires 11a.
Figure 10 A- Figure 10 C describe to form three steps of the third MOSFET type decoding device 3aa.It is initially formed hearth electrode
110, hearth electrode 110 is then removed at the position of decoding device 3aa to form hole 165（Figure 10 A）, semi-conducting material is used later
Hole 165 is filled up, and is planarized（Figure 10 B）.Then it forms storage film 130 and defines x address wires 11a.Finally, top electrode is formed
120 and define y address wires 12a and control line 17a（Figure 10 C）.
Figure 11 A and Figure 11 B indicate the first JFET type decoding device 3aa.Compared with Fig. 5, during decoding device 3aa is not contained
Between film 180（Figure 11 A）.Therefore, top electrode 120 and Modulated Films 160 form a Schottky diode（Or P-N diode）, decoding
Device 3aa is JFET.Its manufacturing process is similar with Fig. 6 A- Fig. 6 B, and the difference between them is hearth electrode 110 and storage film 130
It is formed in before photoresist 150, and eliminates storage film 130 in hole 165（Figure 11 B）.
Figure 12 A and Figure 12 B indicate second of JFET type decoding devices 3aa.Compared with Fig. 7, during decoding device 3aa is not contained
Between film 180（Figure 12 A）.Therefore, top electrode 120 and Modulated Films 160 form a Schottky diode（Or P-N diode）, decoding
Device 3aa is JFET.Its manufacturing process is similar with Fig. 8 A- Fig. 8 D, and the difference between them is that storage film 130 and high-rise conductor are thin
Film 112 is formed simultaneously, and storage film 130 and high-rise conductor thin film 112 are eliminated in hole 165（Figure 12 B）.
Figure 13 A and Figure 13 B indicate the third JFET type decoding device 3aa.Compared with Fig. 9, during decoding device 3aa is not contained
Between film 180（Figure 13 A）.Therefore, top electrode 120 and Modulated Films 160 form a Schottky diode（Or P-N diode）, decoding
Device 3aa is JFET.Its manufacturing process is similar with Figure 10 A- Figure 10 C, and the difference between them is storage film 130 and hearth electrode
110 are formed simultaneously, and eliminate storage film 130 and hearth electrode 110 in hole 165, and Modulated Films 160 and storage film 130 together by
Planarization（Figure 13 B）.
Figure 14 A- Figure 14 C are section of three kinds of MOSFET type decoding device 3aa and 4 3D-MPROM memory devices 12a-12d
Face figure.Decoding device 3aa in Figure 14 A is similar in Fig. 5；Decoding device 3aa in Figure 14 B is similar in Fig. 7；Figure
Decoding device 3aa in 14C is similar in Fig. 9.It is different from 3D-EPROM, represent the 3D-MPROM storages of different digital information
Device 12a-12d has different storage films.Such as say, in a 2 bit 3D-MPROM（I.e. a memory device stores 2
Digit order number）In, the memory device 12a for representing " 00 " has most thin storage film 130a；The memory device 12b for representing " 01 " has
Secondary thin storage film 130b；Represent the storage film 130c that the memory device 12c of " 10 " has third thin；Represent the memory of " 11 "
Part 12d has most thick storage film 130d.In order to effectively block the electric current in x address wires 11a, decoding device 3aa's
Most thin storage film 130a is preferred in intermediate coat 180（Figure 14 A- Figure 14 C）.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to the form and details of the present invention
It is modified, this does not interfere the spirit of their application present invention.Therefore, in addition to the spirit according to appended claims,
The present invention does not answer any way limited.
Claims (10)
1. a kind of compact three-dimensional storage（3D-MC）, it is characterised in that contain：
One semiconductor substrate (0) containing transistor；One is stacked on accumulation layer (10) in the semiconductor substrate (0), the accumulation layer
(10) contain an at least storage array (100A) and at least one and be higher than substrate decoder stage (100P)；One by the accumulation layer (10) and should
The contact access opening (13a) of substrate (0) coupling；
Wherein, which extends to this higher than substrate decoder stage (100P) containing one from the storage array (100A)
The first address wire (11a)；One the second address wire (12a) intersected with first address wire (11a)；One is located at first He
The memory device (1aa) of second address wire infall, the memory device (1aa) contain a diode or a kind of diode component；
A control line (17a) intersected with first address wire (11a) should be contained higher than substrate decoder stage (100P)；One is located at this
The decoding device (3aa) of first address wire (11a) and control line (17a) infall, the decoding device (3aa) contain a crystal
Pipe or a kind of transistor device；The decoding device (3aa) has a conduction mode and a blocking mode：In conduction mode, the solution
Code device is connected and allows electric current flowing in first address wire (11a)；In blocking mode, which disconnects and blocks
Electric current flowing in first address wire (11a)；
The memory device (1aa) and the decoding device (3aa) are located at same accumulation layer (10).
2. memory according to claim 1, it is further characterized in that：The memory device (1aa) is a Two-port netwerk device.
3. memory according to claim 1, it is further characterized in that：The decoding device (3aa) is one or three port devices.
4. a kind of compact three-dimensional storage（3D-MC）, it is characterised in that contain：
One semiconductor substrate (0) containing transistor;One is stacked on accumulation layer (10) in the semiconductor substrate (0), the accumulation layer
(10) contain an at least storage array (100A) and at least one and be higher than substrate decoder stage (100P)；One by the accumulation layer (10) and should
The contact access opening (13a) of substrate (0) coupling；
Wherein, which extends to this higher than substrate decoder stage (100P) containing one from the storage array (100A)
The first address wire (11a)；One the second address wire (12a) intersected with first address wire (11a)；One is located at first He
The memory device (1aa) of second address wire infall, the overlapping portion of first address wire (11a) and second address wire (12a)
Divide (140) and non-overlapping part (140A, 140) that there is identical electrical characteristic；
A control line (17a) intersected with first address wire (11a) should be contained higher than substrate decoder stage (100P)；One is located at this
The decoding device (3aa) of first address wire (11a) and control line (17a) infall, first address wire (11a) and the control
The lap (160) of line (17a) and non-overlapping part (140A, 140) have different electrical characteristics；The decoding device (3aa)
With a conduction mode and a blocking mode：In conduction mode, which connects and allows electric current in first address wire
Flowing in (11a)；In blocking mode, which disconnects and blocks electric current flowing in first address wire (11a)；
The memory device (1aa) and the decoding device (3aa) are located at same accumulation layer (10).
5. memory according to claim 4, it is further characterized in that：In the memory device (1aa), first address wire
(11a) and the lap (140) and non-overlapping part (140A, 140) of second address wire (12a) are a good conductor.
6. memory according to claim 4, it is further characterized in that：In the decoding device (3aa), first address wire
The lap (160) of (11a) and the control line (17a) is a good conductor, and non-overlapping part (160A, 160) is one good to lead
Body.
7. memory according to claim 1 or 4, it is further characterized in that：The three-dimensional storage is that a three-dimensional random accesses
Memory（3D-RAM）.
8. memory according to claim 1 or 4, it is further characterized in that：The three-dimensional storage is a three-dimensional read-only storage
Device（3D-ROM）.
9. memory according to claim 1 or 4, it is further characterized in that：The decoding device (3aa) is a MOSFET.
10. memory according to claim 1 or 4, it is further characterized in that：The decoding device (3aa) is a JFET.
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| CN201710105760.2A CN108511443A (en) | 2017-02-27 | 2017-02-27 | Address wire contains the compact three-dimensional storage of semiconductor portions |
| US15/487,378 US10304495B2 (en) | 2014-04-14 | 2017-04-13 | Compact three-dimensional memory with semi-conductive address line portion |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108511444A (en) * | 2017-02-28 | 2018-09-07 | 成都海存艾匹科技有限公司 | Compact three-dimensional masking film program read-only memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978990A (en) * | 2014-04-14 | 2015-10-14 | 成都海存艾匹科技有限公司 | Compact three-dimensional memory |
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| CN104978990A (en) * | 2014-04-14 | 2015-10-14 | 成都海存艾匹科技有限公司 | Compact three-dimensional memory |
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|---|---|---|---|---|
| CN108511444A (en) * | 2017-02-28 | 2018-09-07 | 成都海存艾匹科技有限公司 | Compact three-dimensional masking film program read-only memory |
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