CN108509375A - Processor array chip multiplexing method based on the comprehensive most short connection of effective node - Google Patents
Processor array chip multiplexing method based on the comprehensive most short connection of effective node Download PDFInfo
- Publication number
- CN108509375A CN108509375A CN201810340885.8A CN201810340885A CN108509375A CN 108509375 A CN108509375 A CN 108509375A CN 201810340885 A CN201810340885 A CN 201810340885A CN 108509375 A CN108509375 A CN 108509375A
- Authority
- CN
- China
- Prior art keywords
- row
- array
- node
- effective node
- effective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Processor array chip multiplexing method based on the comprehensive most short connection of effective node belongs to processor array reconfiguration technique field, more particularly to the multiplexing technology field of processor array chip, it is characterized in that, for the failing processor cell array fired in processor array chip, priority first use is from left to right, then greedy row routing algorithm program again from right to left respectively obtains two on a logical row left side, Target Aerial Array mutually complementary on right distributing position, then again on same processor cell array, that is, physical array by the coordinate position that device unit is effectively treated, mark out two complementary Target Aerial Arrays obtained, it can be obtained a complete Target Aerial Array.The present invention has speed fast, the advantages of being easy to popularize.
Description
Technical field
The present invention relates to restructuring array fields, and in particular to the processor array based on the comprehensive most short connection of effective node
Chip multiplexing method.
Background technology
Reconfigurable Computation is a kind of combined calculation of the high efficiency by the flexibility of software and hardware, such as
Field programmable gate array (FPGA, Field Programmable Gate Array).It is between common microprocessor
Difference lies in can not only change control stream, can with the structure of change data access (Data Path), have high-performance,
The advantages of low hardware spending and power consumption, flexibility be good, favorable expandability.It utilizes the dynamic restructuring characteristic of reconfigurable logic device,
By different configuration files, it will be run in specific command mappings to reconfigurable arrays, can make full use of hardware concurrent
The characteristics of execution, improve computational efficiency, with embeded processor common demands shorten the design cycle, reduce design and develop at
This, in addition the uncertainty of final market and technology is increasing, and reconfigurable processing gradually becomes the embeded processor world and sends out
The trend of exhibition；
In recent years, with the raising of the integrated level of large scale integrated circuit, the processor list in reconfigurable processor array
The possibility of member damage also gradually increases, therefore also becomes a hot spot to the research of reconfigurable processor array reconfiguration technique,
In general there is the method that two major classes reconstruct：Redundancy method (redundancy approach) and the method (degradation that lowers one's standard or status
Approach), redundancy method substitutes the impairment unit in reconfigurable processor array by the way that additional non-break treat with device is added,
Had much using the technology of redundancy method, such as：Super large-scale integration fault-tolerance (I.Koren and A.D.Singh,
" Fault Tolerance in VLSI Circuits, " Computer, vol.23, no.7, pp.73-83, July 1990),
Method of lowering one's standard or status simultaneously does not use additional processor unit, but utilizes the non-damaging processor list in processor array as far as possible more
Member forms a new subarray, is also had much using the technology for the method for lowering one's standard or status, such as：Using short chain fetch structure can lower one's standard or status it is super
Subarray (Wu Jigang, the Thambipillai Srikanthan, Jiang of vlsi processor array
Guiyuan,and Wang Kai:“Constructing sub-arrays with shortinterconnects from
degradable VLSI arrays”,IEEE Trans.Parallel Distrib.Syst,vol.25,pp.929–938,
2014), carry out restructing algorithm (the Wu Jigang and of high-performance super large-scale integration subarray using four port switch
Thambipillai Srikanthan:“Reconfiguration algorithms for power efficient VLSI
subarrays with four-port switches”,IEEE Trans.Computers,vol.55,pp.243–253,
2006) what the technology for method of, lowering one's standard or status at present used is all based on didactic method, although these technologies can reduce long link
Number, but have no idea to ensure that the long linking number of Target Aerial Array after reconstruct is minimum.
Invention content
In order to overcome the deficiencies of the prior art, the invention discloses the processor battle arrays based on the comprehensive most short connection of effective node
Row chip multiplexing method,
The present invention adopts the following technical scheme that achieve the above object：
It is a feature of the present invention that be realize according to the following steps successively in a computer (inventive method schematic diagram and
The program flow diagram difference of greedy row routing algorithm from left to right is as shown in Figure 2 and Figure 4)：
Step (1), computer initialization；Input the processor unit array on chip；
Waited on the chip multiplex processor cell array be a size be M × N, using processor unit as node structure
At physical array, m=1,2 ..., m, M, M is line number, and m is row serial number, and n=1,2 ..., n, N, N is columns, and n is row sequence
Number, wherein whether the processor unit is effectively known, is referred to as effective node and failure node,
Logical row refers to：On the chip in the first row of physical array to be multiplexed, along row sequence since n=1
First effective node that number increased direction is found is starting point, then along the increased direction of row serial number and position since m=1
Effective node in next line at row serial number minimum position connects, and one constituted is from the starting point
, effective sequence node of most short connection distance between effective node with neighbouring relationship；
Step (2) finds out the first logical row T as Target Aerial Array according to the following stepslWith the second logic array Tr, subscript
" l " is indicated since left, and subscript " r " is indicated since right
Step (2.1) uses greedy row routing algorithm GCR from left to right to the physical array that size is M × N, obtains
Size is Ml×KlTarget Aerial Array, KlFor the columns of Target Aerial Array, 1≤kl≤Nl, kl=1,2 ..., kl,Nl,Nl≤ (N-1),
MlFor the line number of Target Aerial Array, 1≤ml≤Ml, ml=1,2 ..., ml,...,Ml, mlFor row serial number, Ml≤ (M-1) (Target Aerial Arrays
TlAs shown in Fig. 1 (a)),
Step (2.1.1), in the m=1 rows of physical array, from left to right judge m=1 in physical array, n=1
Whether the processor unit at place is effective node,
If effective node, then first logical row k is used as1, start element, enter step (2.1.2),
If invalid unit, then m=1 in physical array is judged, whether the processor unit at n=2 is effective node,
So repeat, until finding first effective node in m=1 rows,
Step (2.1.2) judges the physical array m+1 rows n-th1Whether the processor unit at row is effectively to save
Point,
If effective node, then by m+1, n1Effective node at place is connected with the start element, is co-located at first k1
On logical row, step (2.1.3) is executed
If invalid node, then follow the steps (2.1.4)
Step (2.1.3) judges m+2 rows i.e. m3Row first row i.e. n-th1Whether the processor unit at row is effective
Node：
If effective node, then by the m3Row n-th1Effective node at row and the m2Row n-th1Having at row
It imitates node to be connected, is co-located at kth1It on logical row, so repeats, until the processor unit at M-1 row N-1 row
Until, forming one has M-1 rows, n-th1First logical row that effect node is constituted is shown,
Step (2.1.4) judges the physical array m2Row, n-th2Whether the processor unit at row is effective node：
If effective node, then the m described in step (2.1.1)1Row, n-th1Effective node at row and step
M described in (2.1.4)2Row, n-th2Effective node at row is connected, and is co-located on first logical row, so repeats
Step (2.1.4), always until an effective node at last M-1 row N-1 row,
If invalid node, (2.1.5) is thened follow the steps,
Step (2.1.5), then m in return to step (2.1.2)2Row n-th1That original effective node at row, and mark
For dead unit, indicate that described effective node is logical row k where it1The last one effective node；
Step (2.1.6) repeats step (2.1.1) and arrives step (2.1.5), obtains a left side by the physical array
Side is to right edge by KlThe Target Aerial Array T of logical row composition1, every logical row is all in each row of the physical array
One effective node, and whether intersect with each logical row unrelated, allow a plurality of logical row to pass through jointly same common
Effective node；The intersection of existence anduniquess；
Step (2.2) uses greedy row routing algorithm GCR' from right to left to the physical array that size is M × N, obtains
Size is Mr×Kr, 1≤kr≤Mr,MrThe Target Aerial Array T of≤(M-1)r, method is identical described in step (2.1), but sequence
Increase (Target Aerial Array T number from right to leftrAs shown in Fig. 1 (b)),
Step (3), due to Target Aerial Array TlAnd TrSize is not necessarily the same, but is all in same processor unit array core
Distributed left and right complementation that on piece is realized and the two logical row, therefore on same processor unit chip, mesh
Mark array TlWith Target Aerial Array TrIn logical row mark out to come by respective processor unit position, just obtain one it is complete
Target Aerial Array (Target Aerial Array is as shown in Figure 4).
Preferably, in the step (2.1), Target Aerial Array T is being calculated using greedy row routing algorithm from left to rightl
When, if node (m1, N-1) i.e. and when being invalid node, then otherwise program determination will repeat to walk for nodes of last row of the first row
Suddenly (2.1).
Preferably, in the step (2.2), Target Aerial Array T is being calculated using greedy row routing algorithm from right to leftr
When, if node (m1, N-1) i.e. and when being invalid node, then otherwise program determination will repeat to walk for nodes of last row of the first row
Suddenly (2.2).
Compared with prior art, the beneficial effects of the invention are as follows：Processor based on the comprehensive most short connection of effective node
Array chip multiplexing method is calculated using greedy row routing algorithm from left to right and greed row routing from right to left respectively first
Method obtains two logic array, later, since the two logic array are complementary, just by effectively place on a physical array
The coordinate position for managing device unit marks out two complementary Target Aerial Arrays obtained, you can obtain a complete target array
Row, the algorithm have great benefit for the reconstruct of processor array and the multiplexing of processor array chip.
Description of the drawings
Fig. 1 logic array TlAnd TrSchematic diagram：Fig. 1 (a), logic array Tl；Fig. 1 (b), logic array Tr, the grey in figure
Unit indicate invalid unit, remaining unit for being not coated with grey indicates normal unit.
Fig. 2 the method for the present invention schematic diagrames.
Fig. 3 Target Aerial Array schematic diagrames.
The program flow diagram of the greedy row routing algorithms of Fig. 4 from left to right.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with specific embodiment, to this
Invention is further elaborated, and the specific embodiments described herein are merely illustrative of the present invention, is not used to limit
The present invention.
Based on the processor array chip multiplexing method of the comprehensive most short connection of effective node, include the following steps：
Step (1), computer initialization；Input the processor unit array on chip；
Waited on the chip multiplex processor cell array be a size be M × N, using processor unit as node structure
At physical array, m=1,2 ..., m, M, M is line number, and m is row serial number, and n=1,2 ..., n, N, N is columns, and n is row sequence
Number, wherein whether the processor unit is effectively known, is referred to as effective node and failure node,
Logical row refers to：On the chip in the first row of physical array to be multiplexed, along row sequence since n=1
First effective node that number increased direction is found is starting point, then along the increased direction of row serial number and position since m=1
Effective node in next line at row serial number minimum position connects, and one constituted is from the starting point
, effective sequence node of most short connection distance between effective node with neighbouring relationship；
Step (2) finds out the first logical row T as Target Aerial Array according to the following stepslWith the second logic array Tr, subscript
" l " is indicated since left, and subscript " r " is indicated since right
Step (2.1) uses greedy row routing algorithm GCR from left to right to the physical array that size is M × N, obtains
Size is Ml×KlTarget Aerial Array, KlFor the columns of Target Aerial Array, 1≤kl≤Nl, kl=1,2 ..., kl,Nl,Nl≤ (N-1),
MlFor the line number of Target Aerial Array, 1≤ml≤Ml, ml=1,2 ..., ml,...,Ml, mlFor row serial number, Ml≤ (M-1),
Step (2.1.1), in the m=1 rows of physical array, from left to right judge m=1 in physical array, n=1
Whether the processor unit at place is effective node,
If effective node, then first logical row k is used as1, start element, enter step (2.1.2),
If invalid unit, then m=1 in physical array is judged, whether the processor unit at n=2 is effective node,
So repeat, until finding first effective node in m=1 rows,
Step (2.1.2) judges the physical array m+1 rows n-th1Whether the processor unit at row is effectively to save
Point,
If effective node, then by m+1, n1Effective node at place is connected with the start element, is co-located at first k1
On logical row, step (2.1.3) is executed
If invalid node, then follow the steps (2.1.4)
Step (2.1.3) judges m+2 rows i.e. m3Row first row i.e. n-th1Whether the processor unit at row is effective
Node：
If effective node, then by the m3Row n-th1Effective node at row and the m2Row n-th1Having at row
It imitates node to be connected, is co-located at kth1It on logical row, so repeats, until the processor unit at M-1 row N-1 row
Until, forming one has M-1 rows, n-th1First logical row that effect node is constituted is shown,
Step (2.1.4) judges the physical array m2Row, n-th2Whether the processor unit at row is effective node：
If effective node, then the m described in step (2.1.1)1Row, n-th1Effective node at row and step
M described in (2.1.4)2Row, n-th2Effective node at row is connected, and is co-located on first logical row, so repeats
Step (2.1.4), always until an effective node at last M-1 row N-1 row,
If invalid node, (2.1.5) is thened follow the steps,
Step (2.1.5), then m in return to step (2.1.2)2Row n-th1That original effective node at row, and mark
For dead unit, indicate that described effective node is logical row k where it1The last one effective node；
Step (2.1.6) repeats step (2.1.1) and arrives step (2.1.5), obtains a left side by the physical array
Side is to right edge by KlThe Target Aerial Array T of logical row composition1, every logical row is all in each row of the physical array
One effective node, and whether intersect with each logical row unrelated, allow a plurality of logical row to pass through jointly same common
Effective node；The intersection of existence anduniquess；
Step (2.2) uses greedy row routing algorithm GCR' from right to left to the physical array that size is M × N, obtains
Size is Mr×Kr, 1≤kr≤Mr,MrThe Target Aerial Array T of≤(M-1)r, method is identical described in step (2.1), but sequence
Number increase from right to left,
Step (3), due to Target Aerial Array TlAnd TrSize is not necessarily the same, but is all in same processor unit array core
Distributed left and right complementation that on piece is realized and the two logical row, therefore on same processor unit chip, mesh
Mark array TlWith Target Aerial Array TrIn logical row mark out to come by respective processor unit position, just obtain one it is complete
Target Aerial Array.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
Understanding without departing from the principles and spirit of the present invention can carry out these embodiments a variety of variations, modification, replace
And modification, the scope of the present invention is defined by the appended.
Claims (3)
1. the processor array chip multiplexing method based on the comprehensive most short connection of effective node, which is characterized in that be to calculate
It is realized according to the following steps successively in machine：
Step (1), computer initialization；Input the processor unit array on chip；
Waited on the chip multiplex processor cell array be a size be M × N, constituted using processor unit as node
Physical array, m=1,2 ..., m, M, M are line number, and m is row serial number, and n=1,2 ..., n, N, N is columns, and n is row serial number,
In, whether the processor unit is effectively known, is referred to as effective node and failure node,
Logical row refers to：On the chip in the first row of physical array to be multiplexed, increase along row serial number since n=1
First effective node that the direction added is found is starting point, then since m=1 along the increased direction of row serial number and under being located at
Effective node in a line at row serial number minimum position connects, and one constituted has from the starting point
There is effective sequence node of most short connection distance between effective node of neighbouring relationship；
Step (2) finds out the first logical row T as Target Aerial Array according to the following stepslWith the second logic array Tr, subscript " l " table
Show since left, subscript " r " is indicated since right
Step (2.1) uses greedy row routing algorithm GCR from left to right to the physical array that size is M × N, obtains size
For Ml×KlTarget Aerial Array, KlFor the columns of Target Aerial Array, 1≤kl≤Nl, kl=1,2 ..., kl,Nl,Nl≤ (N-1), MlFor
The line number of Target Aerial Array, 1≤ml≤Ml, ml=1,2 ..., ml,...,Ml, mlFor row serial number, Ml≤ (M-1),
Step (2.1.1), in the m=1 rows of physical array, m=1 in physical array is from left to right judged, at n=1
Whether processor unit is effective node,
If effective node, then first logical row k is used as1Start element, enter step (2.1.2),
If invalid unit, then m=1 in physical array is judged, whether the processor unit at n=2 is effective node, so
It repeats, until finding first effective node in m=1 rows,
Step (2.1.2) judges the physical array m+1 rows n-th1Whether the processor unit at row is effective node,
If effective node, then by m+1, n1Effective node at place is connected with the start element, is co-located at first k1Logic
On row, step (2.1.3) is executed
If invalid node, then follow the steps (2.1.4)
Step (2.1.3) judges m+2 rows i.e. m3Row first row i.e. n-th1Whether the processor unit at row is effective node：
If effective node, then by the m3Row n-th1Effective node at row and the m2Row n-th1Effective node at row
It is connected, is co-located at kth1On logical row, so repeat, until processor unit at M-1 row N-1 row,
Forming one has M-1 rows, n-th1First logical row that effect node is constituted is shown,
Step (2.1.4) judges the physical array m2Row, n-th2Whether the processor unit at row is effective node：
If effective node, then the m described in step (2.1.1)1Row, n-th1Effective node at row and step (2.1.4)
Described in m2Row, n-th2Effective node at row is connected, and is co-located at first logical row k1On, so repeat step
(2.1.4), always until an effective node at last M-1 row N-1 row,
If invalid node, (2.1.5) is thened follow the steps,
Step (2.1.5), then m in return to step (2.1.2)2Row n-th1That original effective node at row, and labeled as dead
Unit is died, indicates that described effective node is logical row k where it1The last one effective node；
Step (2.1.6) repeat step (2.1.1) arrive step (2.1.5), obtain a left side by the physical array to
Right edge by KlThe Target Aerial Array T of logical row composition1, every logical row all pass through each row of the physical array in one
Effective node, and whether intersect with each logical row unrelated, allow a plurality of logical row to pass through jointly same common effective
Node；The intersection of existence anduniquess；
Step (2.2) uses greedy row routing algorithm GCR' from right to left to the physical array that size is M × N, obtains size
For Mr×Kr, 1≤kr≤Mr,MrThe Target Aerial Array T of≤(M-1)r, method is identical described in step (2.1), but serial number by
The left increase of dextrad,
Step (3), due to Target Aerial Array TlAnd TrSize is not necessarily the same, but is all on same processor unit array chip
Distributed left and right complementation realize and the two logical row, therefore on same processor unit chip, target array
Arrange TlWith Target Aerial Array TrIn logical row by respective processor unit position mark out come, just obtain a complete target
Array.
2. the processor array chip multiplexing method according to claim 1 based on the comprehensive most short connection of effective node its
It is characterized in that, Target Aerial Array T is being calculated using greedy row routing algorithm from left to rightlWhen, if：Node (m1, N-1) i.e. first
When the node of last row of row is invalid node, then otherwise program determination will repeat step (2.1).
3. the processor array chip multiplexing method according to claim 1 based on the comprehensive most short connection of effective node its
It is characterized in that, Target Aerial Array T is being calculated using greedy row routing algorithm from right to leftrWhen, if：Node (m1, N-1) i.e. first
When the node of last row of row is invalid node, then otherwise program determination will repeat step (2.2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810340885.8A CN108509375A (en) | 2018-04-17 | 2018-04-17 | Processor array chip multiplexing method based on the comprehensive most short connection of effective node |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810340885.8A CN108509375A (en) | 2018-04-17 | 2018-04-17 | Processor array chip multiplexing method based on the comprehensive most short connection of effective node |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108509375A true CN108509375A (en) | 2018-09-07 |
Family
ID=63382109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810340885.8A Pending CN108509375A (en) | 2018-04-17 | 2018-04-17 | Processor array chip multiplexing method based on the comprehensive most short connection of effective node |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108509375A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2363812A1 (en) * | 2010-03-04 | 2011-09-07 | Karlsruher Institut für Technologie | Reconfigurable processor architecture |
| CN102650980A (en) * | 2012-04-09 | 2012-08-29 | 清华大学 | Method and device for generating configuration information with multi-core dynamic reconfigurable processor |
| CN106201979A (en) * | 2016-06-27 | 2016-12-07 | 广东工业大学 | Algorithm towards the multi-processor array reconstruct that communication synchronizes |
| CN106201988A (en) * | 2016-08-03 | 2016-12-07 | 桂林电子科技大学 | A kind of method reconstructing high performance objectives array |
| CN106250352A (en) * | 2016-08-03 | 2016-12-21 | 桂林电子科技大学 | A kind of abstract model method of reconfigurable processor array |
-
2018
- 2018-04-17 CN CN201810340885.8A patent/CN108509375A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2363812A1 (en) * | 2010-03-04 | 2011-09-07 | Karlsruher Institut für Technologie | Reconfigurable processor architecture |
| CN102650980A (en) * | 2012-04-09 | 2012-08-29 | 清华大学 | Method and device for generating configuration information with multi-core dynamic reconfigurable processor |
| CN106201979A (en) * | 2016-06-27 | 2016-12-07 | 广东工业大学 | Algorithm towards the multi-processor array reconstruct that communication synchronizes |
| CN106201988A (en) * | 2016-08-03 | 2016-12-07 | 桂林电子科技大学 | A kind of method reconstructing high performance objectives array |
| CN106250352A (en) * | 2016-08-03 | 2016-12-21 | 桂林电子科技大学 | A kind of abstract model method of reconfigurable processor array |
Non-Patent Citations (1)
| Title |
|---|
| 胡佳: "基于SAT的高性能子阵列重构算法研究", 《万方数据》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10282338B1 (en) | Configuring routing in mesh networks | |
| US8737392B1 (en) | Configuring routing in mesh networks | |
| US8265070B2 (en) | System and method for implementing a multistage network using a two-dimensional array of tiles | |
| US8151088B1 (en) | Configuring routing in mesh networks | |
| US10979366B1 (en) | Optimization of multi-stage hierarchical networks for practical routing applications | |
| US20200076744A1 (en) | Fast scheduling and optmization of multi-stage hierarchical networks | |
| EP3742485B1 (en) | Layered super-reticle computing: architectures and methods | |
| US10965618B1 (en) | Automatic multi-stage fabric generation for FPGAs | |
| US9374322B2 (en) | Optimization of multi-stage hierarchical networks for practical routing applications | |
| Ranade et al. | The communication efficiency of meshes, boolean cubes and cube connected cycles for wafer scale integration | |
| US20210349847A1 (en) | Embedding Rings on a Toroid Computer Network | |
| US20200311017A1 (en) | Partitionable Networked Computer | |
| SAMI et al. | Fault tolerant computing approaches | |
| Yunus et al. | Shuffle Exchange Network in Multistage InterconnectionNetwork: A Review and Challenges | |
| CN103164386A (en) | Synchronization performance optimization method for large scale integrated circuit reconfigurable processor array | |
| CN108509375A (en) | Processor array chip multiplexing method based on the comprehensive most short connection of effective node | |
| CN106201979B (en) | Method towards the synchronous multi-processor array reconstruct of communication | |
| Bogdanski et al. | Achieving predictable high performance in imbalanced fat trees | |
| CN113159302B (en) | Routing structure for reconfigurable neural network processor | |
| CN109117318A (en) | TSV based on subregion clusters Fault-Tolerant System and method | |
| CN107403028B (en) | Fault point driven V L SI array reconstruction method | |
| Oruç | One-sided binary tree-crossbar switching for on-chip networks | |
| Wu et al. | Shortest partial path first algorithm for reconfigurable processor array with faults | |
| EP3948562A1 (en) | Embedding rings on a toroid computer network | |
| Wang et al. | Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180907 |
|
| WD01 | Invention patent application deemed withdrawn after publication |