CN108509223B

CN108509223B - Data processing method, device and system and storage medium

Info

Publication number: CN108509223B
Application number: CN201810214030.0A
Authority: CN
Inventors: 王海涛
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2018-03-15
Filing date: 2018-03-15
Publication date: 2021-09-14
Anticipated expiration: 2038-03-15
Also published as: CN108509223A

Abstract

The invention discloses a data processing method, which is applied to a Baseboard Management Controller (BMC), wherein the BMC comprises two or more CHIPs (CHIPs); the method comprises the following steps: generating a first instruction when the first operation is detected; determining a first function corresponding to the first instruction according to the first instruction; finding a CHIP supporting the first function among the more than two CHIPs; sending the first instruction to at least one of the found CHIPs that support the first function, such that the at least one of the first CHIPs executes the first instruction to implement the first function. The invention also discloses a data processing device, a system and a storage medium.

Description

Data processing method, device and system and storage medium

Technical Field

The present invention relates to data processing technologies, and in particular, to a data processing method, apparatus, system, and storage medium.

Background

The Baseboard Management Controller (BMC) is a remote Management Controller for executing a server, and can perform operations such as firmware upgrade and device check on a device in a state where the device is not powered on. However, no matter the CHIP or the BMC software of the BMC is currently, the system becomes larger and larger, the power is more and more, and the system is overstaffed, the response is slow, the boot time is long, and the user experience is poor.

Disclosure of Invention

In view of this, embodiments of the present invention are expected to provide a data processing method, an apparatus, a system, and a storage medium, which can solve the problems of slow system response and long boot time caused by a large system volume in the prior art.

In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:

according to an aspect of the embodiments of the present invention, a data processing method is provided, where the method is applied to a BMC, where the BMC includes two or more CHIP CHIPs; the method comprises the following steps:

generating a first instruction when the first operation is detected;

determining a first function corresponding to the first instruction according to the first instruction;

finding a CHIP supporting the first function among the more than two CHIPs;

sending the first instruction to at least one of the found CHIPs that support the first function, such that the at least one of the first CHIPs executes the first instruction to implement the first function.

In the above scheme, the method further comprises:

determining that implementing the first function is premised on implementing a second function first, searching for a CHIP supporting the second function among the two or more CHIPs;

sending a second instruction to at least one of the found CHIPs that support the second function, such that the at least one of the second CHIPs executes the second instruction, to implement the second function.

In the above scheme, the method further comprises:

controlling the more than two CHIPs to send heartbeat messages to each other in a preset period;

and when at least one CHIP of the more than two CHIPs is determined not to receive the heartbeat message in the preset period, determining that the BMC is in fault.

In the above scheme, the method further comprises:

generating a third instruction when the second operation is detected;

when the third instruction is determined to be a program updating instruction in the CHIP, analyzing the third instruction to obtain program version information carried in the third instruction;

determining a CHIP to be updated among the more than two CHIPs according to the program version information;

sending the third instruction to the CHIP to be updated, such that the CHIP to be updated executes the third instruction to complete a program update operation.

In the above solution, after the third instruction is sent to the CHIP to be updated, so that the CHIP to be updated executes the third instruction to complete the program update operation, the method further includes:

controlling other CHIPs of the two or more CHIPs except the CHIP to be updated to maintain a current operating state when it is determined that the other CHIPs are in a task execution state.

According to another aspect of the embodiments of the present invention, there is provided a data processing apparatus, including: the device comprises a generating unit, a determining unit, a searching unit and a sending unit;

the generating unit is used for generating a first instruction when a first operation is detected;

the determining unit is used for determining a first function corresponding to the first instruction according to the first instruction;

the searching unit is used for searching CHIPs supporting the first function from more than two CHIPs in the BMC;

the transmitting unit is configured to transmit the first instruction to at least one of the found CHIPs that support the first function, so that the CHIP of the at least one first CHIP executes the first instruction to implement the first function.

In the above scheme, the apparatus further comprises: a control unit;

the control unit is configured to control the more than two CHIPs to send heartbeat messages to each other within a preset period;

the determining unit is further configured to determine that the BMC fails when at least one CHIP of the more than two CHIPs does not receive the heartbeat message within the preset period.

According to a third aspect of embodiments of the present invention, there is provided a data processing apparatus, the apparatus comprising: memory, a processor and an executable program stored in the memory for movement by the processor, wherein the processor executes the executable program to perform the method steps of any of the above data processing methods.

According to a fourth aspect of embodiments of the present invention, there is provided a storage medium having an executable program stored thereon, wherein the executable program, when executed by a processor, implements the method steps of any of the above-mentioned data processing methods.

According to a fifth aspect of embodiments of the present invention, there is provided a data processing system, comprising more than two CHIPs; a CHIP of the more than two CHIPs that supports a first function, upon receiving a first instruction, executes the first instruction to implement the first function.

According to the data processing method, the device, the system and the storage medium provided by the invention, the CHIP in the BMC system is divided into more than two CHIPs according to the function, each CHIP supports one function, when the BMC system detects that the first collective generation instruction is operated, the generated first instruction is sent to the CHIP supporting the first function corresponding to the generated first instruction, and the CHIP supporting the first function executes the first instruction to realize the first function, so that the function of each CHIP is clear, the BMC system is stable, the starting time is accelerated, and the customer experience is improved.

Drawings

Fig. 1 is a schematic flow chart of a data processing method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the BMC system according to the embodiment of the invention;

FIG. 3 is a first block diagram illustrating a data processing apparatus according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.

Detailed Description

So that the manner in which the features and aspects of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.

Fig. 1 is a schematic flow chart of a data processing method according to an embodiment of the present invention, as shown in fig. 1, the method includes the following steps:

step 101, generating a first instruction when a first operation is detected;

in this embodiment of the present invention, the first operation may be an operation generated when a user touches a physical key of the device. For example, the physical key is a power-on key on the device, and when the power-on key is triggered by a user, the device can detect a power-on operation generated by the user touching the power-on key, and then generate a power-on instruction according to the detected power-on operation.

On the other hand, the first operation may also be an operation generated by a user touching a function module in an application installed on the device. For example, an application having an information search function is installed on a device, and when a user searches for information through the application, information to be searched for is input in an information input box of the application, and then, information search is performed by clicking an information search icon of the application. Therefore, the information searching module in the application program can detect the information searching operation generated by the user touching the information searching icon, and then generate the information searching instruction according to the detected information searching operation.

Here, the device may specifically be a device installed with a BMC system, for example, the device may be a desktop computer, a laptop computer, a PAD, or other terminals.

Step 102, determining a first function corresponding to the first instruction according to the first instruction;

in the embodiment of the invention, after the device generates the first instruction according to the detected first operation, the first instruction is analyzed to obtain the first function corresponding to the first instruction. For example, when the first instruction is a boot instruction, it is determined that the function corresponding to the boot instruction is a boot function by analyzing the boot instruction. And when the first instruction is an information searching instruction, determining that the function corresponding to the information searching instruction is a network searching function by analyzing the information searching instruction.

Step 103 of searching for a CHIP supporting the first function among the two or more CHIPs;

in the embodiment of the present invention, the BMC system in the device has two or more CHIPs divided according to different functions, and therefore, after the device determines the first function corresponding to the first instruction according to the first instruction, it is necessary to search for a CHIP supporting the first function in a CHIP set in the BMC system.

Here, the CHIP set includes at least two CHIPs, and the two CHIPs support different functions. For example, one CHIP supports the internet access function, and another CHIP supports the video playback function.

Specifically, two CHIPs with different functions are interconnected by using a communication interface to form a complete BMC system. For example, when the device generates a video playback instruction according to the operation of the user, it is necessary to search for a CHIP having a video playback function in the CHIP set.

Here, the communication interface for interconnecting two CHIPs with different functions may be a serial port or a parallel port, and the type of the specific communication interface is not limited as long as the connection between two different CHIPs can be realized. And each CHIP does not need to adopt a complex linux operating system, and can adopt some OS operating systems with better real-time performance, such as uc/cos, FreeRTOS, RT-thread and the like.

Step 104 of sending the first instruction to at least one of the found CHIPs supporting the first function, so that the CHIP of the at least one first CHIP executes the first instruction to implement the first function.

In the embodiment of the present invention, each CHIP stores Firmware (FW). FW is a "driver" stored in the CHIP, and an operating system in the device can realize the operation of a specific device according to a standard device driver by firmware, and for example, an optical disc drive, a recorder, and the like have internal firmware.

Here, when the device finds a CHIP having the first function in the set of CHIPs, the first instruction triggered by the user is transmitted only to CHIPs supporting the first function, and the CHIPs supporting the first function execute the first instruction to implement the first function upon receiving the first instruction. CHIPs other than the CHIP having the first function in the CHIP set do not execute the first instruction. Therefore, each CHIP in the CHIP set can clearly know the function supported by each CHIP, and the condition that the BMC system is unstable due to too much load of each CHIP is avoided, so that the boot time of the BMC can be shortened, and the use experience of a user is improved.

In the embodiment of the present invention, when the device determines that implementing the first function is premised on implementing a second function first, a CHIP supporting the second function is searched for among the more than two CHIPs; and then sends a second instruction corresponding to a second function to at least one of the found CHIPs supporting the second function, so that the CHIP of the at least one second CHIP executes the second instruction to implement the second function.

For example, the first function is a video playing function, and when it is determined that networking is necessary to implement the video playing function through a video resource searched by a user, it is determined that implementing the first function is premised on implementing the second function first, that is, it is determined that implementing the video playing function requires implementing a network connection function first.

In the embodiment of the invention, the equipment also can control more than two CHIPs in the BMC system to send heartbeat messages to each other in a preset period; and when at least one CHIP of the more than two CHIPs is determined not to receive the heartbeat message in the preset period, determining that the BMC is in fault. As shown in particular in fig. 2.

Fig. 2 is a schematic structural diagram of a BMC system according to an embodiment of the present invention, and as shown in fig. 2, the BMC system includes three CHIPs, and the three CHIPs are divided into a first CHIP 201 that processes network and web portions according to functions, the first CHIP 201 may be represented by network/web, a second CHIP202 that processes information such as video, LPC, mouse, and keyboard, the second CHIP202 may be represented by KVM/KCS, sensor monitor \ log, and a third CHIP 203 that processes sensor and log, and the third CHIP 203 may be represented by sensor monitor \ log.

Specifically, after the device controls three CHIPs (CHIP 201, CHIP202, and CHIP 203) to send heartbeat messages to each other according to a preset period, for example, 5 seconds, if the CHIP 201(network/web) does not receive the heartbeat message sent by the CHIP 203(sensor monitor \ log) within 5 seconds of the preset period, it is determined that the BMC system fails. Thus, by mutual supervision (monitor) between CHIPs, the occurrence of hang machine in the BMC system can be avoided.

In the embodiment of the invention, when the device detects the second operation, a third instruction is generated; when the third instruction is determined to be a program updating instruction in the CHIP, analyzing the third instruction to obtain program version information carried in the third instruction; determining a CHIP to be updated among the more than two CHIPs according to the program version information; and send the third instruction to the CHIP to be updated, such that the CHIP to be updated executes the third instruction to complete a program update operation.

Here, the program version information includes: program version model, CHIP model, etc.

Specifically, when the device obtains the program update instruction, the device may compare the CHIP type carried in the program update instruction with the types of the CHIPs in the BMC system to obtain a comparison result, and when the comparison result indicates that a CHIP of the same type as the CHIP in the program update instruction has been found in the BMC system, determine the found CHIP as the CHIP to be updated.

In the embodiment of the present invention, the apparatus is further configured to determine the operating states of CHIPs other than the CHIP to be updated among the two or more CHIPs, after sending the third instruction to the CHIP to be updated so that the CHIP to be updated performs the third instruction to complete the program update operation. And controlling the other CHIPs to maintain the current operating states when determining that the other CHIPs are in the task execution state according to the operating states of the other CHIPs. In this manner, even during FW update (update) of each CHIP, other CHIPBNs in the CHIP set can continue to operate and provide service to the outside.

Fig. 3 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention, as shown in fig. 3, the apparatus includes: a generating unit 301, a determining unit 302, a searching unit 303 and a sending unit 304;

the generating unit 301 is configured to generate a first instruction when a first operation is detected;

the determining unit 302 is configured to determine, according to the first instruction, a first function corresponding to the first instruction;

the finding unit 303, configured to find a CHIP supporting the first function among the more than two CHIPs;

the sending unit 304 is configured to send the first instruction to at least one of the found CHIPs that support the first function, so that the CHIP of the at least one first CHIP executes the first instruction to implement the first function.

In the embodiment of the present invention, the device may specifically be a desktop computer, a notebook computer, and a PAD, and a BMC system is installed in the device, and the BMC system includes two or more CHIPs divided according to different functions.

In this embodiment of the present invention, if the determining unit 302 determines that the first function is realized on the premise that the second function is realized first, the searching unit 303 is triggered to search for a CHIP supporting the second function from among the more than two CHIPs; when the finding unit 303 finds a CHIP supporting the second function, a second instruction is sent to at least one second CHIP of the found CHIPs supporting the second function, so that the CHIP of the at least one second CHIP executes the second instruction to implement the second function.

In the embodiment of the present invention, the apparatus further includes: a control unit 305;

the control unit 305 is configured to control the more than two CHIPs to send heartbeat messages to each other within a preset period, so as to obtain a data receiving result for the heartbeat messages;

the determining unit 302 is further configured to determine that the BMC fails when at least one CHIP of the more than two CHIPs does not receive the heartbeat message within the preset period according to the data receiving result for the heartbeat message.

In the embodiment of the present invention, the apparatus further includes: an analysis unit 306;

the generating unit 301 is further configured to generate a third instruction when the second operation is detected;

the parsing unit 306 is configured to, when it is determined that the third instruction is a program update instruction in the CHIP, parse the third instruction to obtain program version information carried in the third instruction;

the determining unit 302 is configured to determine a CHIP to be updated among the more than two CHIPs according to the program version information;

the sending unit 304 sends the third instruction to the CHIP to be updated, so that the CHIP to be updated executes the third instruction to complete the program update operation.

In the embodiment of the present invention, the sending unit 304 triggers the determining unit 302 to determine the operating states of CHIPs other than the CHIP to be updated among the two or more CHIPs after sending the third instruction to the CHIP to be updated so that the CHIP to be updated performs the third instruction to complete the program update operation. When the determining unit 302 determines that the other of the more than two CHIPs other than the CHIP to be updated is in the task execution state, it triggers the controlling unit 305 to control the other CHIPs to maintain the current operating state.

It should be noted that: in the data processing apparatus provided in the above embodiment, when performing data processing, only the division of each program module is exemplified, and in practical applications, the processing may be distributed to different program modules according to needs, that is, the internal structure of the data processing apparatus may be divided into different program modules to complete all or part of the processing described above. In addition, the data processing apparatus and the data processing method provided by the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments and are not described herein again.

FIG. 4 is a second schematic diagram illustrating a structure of a data processing apparatus according to an embodiment of the present invention; as shown in fig. 4, the data processing apparatus 400 may be a mobile phone, a computer, a digital broadcast terminal, an information transceiver device, a game console, a tablet device, a personal digital assistant, an information push server, a content server, an authentication server, and the like. The data processing apparatus 400 shown in fig. 4 includes: at least one processor 401, memory 402, at least one network interface 404, and a user interface 403. The various components in the data processing device 400 are coupled together by a bus system 405. It is understood that the bus system 405 is used to enable connection communication between these components. The bus system 405 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 405 in fig. 4.

The user interface 403 may include, among other things, a display, a keyboard, a mouse, a trackball, a click wheel, a key, a button, a touch pad, or a touch screen.

It will be appreciated that the memory 402 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 402 described in connection with the embodiments of the invention is intended to comprise, without being limited to, these and any other suitable types of memory.

The memory 402 in the embodiments of the present invention is used to store various types of data to support the operation of the data processing apparatus 400. Examples of such data include: any computer program for operating on the data processing apparatus 400, such as an operating system 4021 and application programs 4022; the operating system 4021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, and is configured to implement various basic services and process hardware-based tasks. The application 4022 may include various applications such as a Media Player (Media Player), a Browser (Browser), and the like for implementing various application services. A program for implementing the method according to the embodiment of the present invention may be included in the application 4022.

The method disclosed in the above embodiments of the present invention may be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 401. The Processor 401 described above may be a general purpose Processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. Processor 401 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed by the embodiment of the invention can be directly implemented by a hardware decoding processor, or can be implemented by combining hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 402, and the processor 401 reads the information in the memory 402 and performs the steps of the aforementioned methods in conjunction with its hardware.

In an exemplary embodiment, the data processing apparatus 400 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, Programmable Logic Devices (PLDs), Complex Programmable Logic Devices (CPLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, Micro Controllers (MCUs), microprocessors (microprocessors), or other electronic components for performing the foregoing methods.

Specifically, when the processor 401 runs the computer program, it executes: generating a first instruction when the first operation is detected;

searching for a CHIP supporting the first function among more than two CHIPs in the BMC;

When the processor 401 runs the computer program, it further executes: determining that implementing the first function is premised on implementing a second function first, searching for a CHIP supporting the second function among the two or more CHIPs;

When the processor 401 runs the computer program, it further executes: controlling the more than two CHIPs to send heartbeat messages to each other in a preset period;

When the processor 401 runs the computer program, it further executes: generating a third instruction when the second operation is detected;

When the processor 401 runs the computer program, it further executes: controlling other CHIPs of the two or more CHIPs except the CHIP to be updated to maintain a current operating state when it is determined that the other CHIPs are in a task execution state.

In an exemplary embodiment, the present invention further provides a computer readable storage medium, such as a memory 402, comprising a computer program, which is executable by a processor 401 of the data processing apparatus 400 to perform the steps of the aforementioned method. The computer readable storage medium can be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM; or may be a variety of devices including one or any combination of the above memories, such as a mobile phone, computer, tablet device, personal digital assistant, etc.

A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, performs: generating a first instruction when the first operation is detected;

The computer program, when executed by the processor, further performs: determining that implementing the first function is premised on implementing a second function first, searching for a CHIP supporting the second function among the two or more CHIPs;

The computer program, when executed by the processor, further performs: controlling the more than two CHIPs to send heartbeat messages to each other in a preset period;

The computer program, when executed by the processor, further performs: generating a third instruction when the second operation is detected;

The computer program, when executed by the processor, further performs: controlling other CHIPs of the two or more CHIPs except the CHIP to be updated to maintain a current operating state when it is determined that the other CHIPs are in a task execution state.

The embodiment of the invention also provides a data processing system, which can be specifically a BMC system, wherein the BMC system comprises more than two CHIPs divided according to different functions; a CHIP of the more than two CHIPs that supports a first function, upon receiving a first instruction, executes the first instruction to implement the first function. Reference may be made in particular to the description of the method embodiment described above with respect to fig. 2. And will not be described in detail herein.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A data processing method is applied to a Baseboard Management Controller (BMC), wherein the BMC comprises more than two CHIPs (CHIPs); the method comprises the following steps:

generating a first instruction when the first operation is detected;

finding a CHIP supporting the first function among the more than two CHIPs;

sending the first instruction to at least one of the found CHIPs that support the first function, such that the at least one of the first CHIPs executes the first instruction to implement the first function;

wherein, on the premise that it is determined that the first function is realized by first realizing a second function, finding a CHIP supporting the second function among the two or more CHIPs; sending a second instruction to at least one of the found CHIPs that support the second function, such that the at least one of the second CHIPs executes the second instruction, to implement the second function.

2. The method of claim 1, further comprising:

3. The method of claim 1, further comprising:

generating a third instruction when the second operation is detected;

4. The method of claim 3, wherein after sending the third instruction to the CHIP to be updated such that the CHIP to be updated performs the third instruction to complete a program update operation, the method further comprises:

5. A data processing apparatus, the apparatus comprising: the device comprises a generating unit, a determining unit, a searching unit and a sending unit;

the transmitting unit is configured to transmit the first instruction to at least one of the found CHIPs that support the first function, so that the CHIP of the at least one first CHIP executes the first instruction to implement the first function;

6. The apparatus of claim 5, further comprising: a control unit;

7. A data processing apparatus, the apparatus comprising: memory, processor and executable program stored in the memory for execution by the processor, characterized in that the steps of the control method according to any of claims 1 to 4 are performed when the processor executes the executable program.

8. A storage medium having stored thereon an executable program, characterized in that the executable program, when executed by a processor, implements the steps of the control method according to any one of claims 1 to 4.

9. A BMC system comprising more than two CHIPs; when a CHIP supporting a first function among the more than two CHIPs receives a first instruction, executing the first instruction to realize the first function; wherein, on the premise that it is determined that the first function is realized by first realizing a second function, finding a CHIP supporting the second function among the two or more CHIPs; sending a second instruction to at least one of the found CHIPs that support the second function, such that the at least one of the second CHIPs executes the second instruction, to implement the second function.