CN108470745A - Imaging sensor and forming method thereof - Google Patents
Imaging sensor and forming method thereof Download PDFInfo
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- CN108470745A CN108470745A CN201810399604.6A CN201810399604A CN108470745A CN 108470745 A CN108470745 A CN 108470745A CN 201810399604 A CN201810399604 A CN 201810399604A CN 108470745 A CN108470745 A CN 108470745A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000003384 imaging method Methods 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 183
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 239000004065 semiconductor Substances 0.000 claims abstract description 82
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000005336 cracking Methods 0.000 abstract description 8
- 230000004907 flux Effects 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- 229910018503 SF6 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
Abstract
A kind of imaging sensor and forming method thereof, the method includes：Semiconductor substrate is provided, the back side of the semiconductor substrate is formed with hard mask layer, and the front of the semiconductor substrate is formed with Facad structure；Form patterned mask layer, the hard mask layer is performed etching according to the mask layer, to form etching groove, the etching groove runs through the hard mask layer, the side wall of the etching groove includes the upper side wall to connect up and down and lower wall, and the upper side wall and the angle on the hard mask layer surface are obtuse angle；Using the mask layer as mask, the semiconductor substrate is etched, so that the etching groove runs through the semiconductor substrate；Dielectric layer is formed, the dielectric layer covers the bottom and side wall of the etching groove, and covers the hard mask layer.The present invention program can reduce the possibility that hard mask layer problem of Cracking occurs.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of imaging sensor and forming method thereof.
Background technology
In existing semiconductor fabrication process, there are the techniques of filled media layer in the trench, such as in one kind
In the manufacturing process of cmos image sensor (CMOS Image Sensors, CIS) device, can first semiconductor substrate just
Face forms logical device, pixel device and metal interconnection structure etc., then using carrying wafer and the semiconductor substrate
Front bonding, and then form reach through hole (Through Silicon Via, TSV), filter at the back side of semiconductor substrate
(Filter) structures such as.
Specifically, in the existing technique for forming TSV, hard mask layer usually is formed on the surface of semiconductor substrate, into
And the hard mask layer is etched, to be formed in the etching groove perpendicular to the extension of the direction of the semiconductor substrate, and then formed
Cover the dielectric layer of the etching groove, wherein the material of the hard mask layer for example can be silica, the dielectric layer
Material for example can be silicon nitride.
However, in the prior art, the hard mask layer described in the open top position of etching groove is susceptible to cracking and asks
Topic influences subsequent technique and product quality, and the dielectric layer is easy to occur to be closed now in the top position of etching groove
As forming the medium hole in etching groove, also can further be had an impact to subsequent technique and product quality.
Invention content
The technical problem to be solved by the present invention is to provide a kind of imaging sensors and forming method thereof, can make the medium to be formed
Pattern of the layer in the open top position of etching groove is more gentle, reduces the possibility that hard mask layer problem of Cracking occurs.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of imaging sensor, including：It provides
The back side of semiconductor substrate, the semiconductor substrate is formed with hard mask layer, and the front of the semiconductor substrate is formed with front
Structure；The hard mask layer is performed etching, to form etching groove, the etching groove runs through the hard mask layer, described
The side wall of etching groove includes the upper side wall to connect up and down and lower wall, the angle of the upper side wall and the hard mask layer surface
For obtuse angle；The semiconductor substrate is etched, so that the etching groove runs through the semiconductor substrate；Dielectric layer is formed, it is described
Dielectric layer covers the bottom and side wall of the etching groove, and covers the hard mask layer.
Optionally, the hard mask layer is performed etching, includes to form etching groove：In the table of the hard mask layer
Face, forms patterned mask layer, and the patterned mask layer has opening；Using the first etching technics, with the figure
The mask layer of change is hard mask layer described in mask etching, and to form etching groove, the etching groove runs through the hard mask layer；
Using the second etching technics, the patterned mask layer is performed etching, to expand the width of the opening, and exposes institute
State a part for hard mask layer；Using third etching technics, using the patterned mask layer as mask, the hard mask is etched
Layer, so that the upper side wall of the etching groove and the angle on the hard mask layer surface are obtuse angle.
Optionally, first etching technics is anisotropic dry etch process.
Optionally, the third etching technics is isotropic etching technics.
Optionally, the imaging sensor forming method further includes：Before the formation dielectric layer, covered described in removal
Film layer.
Optionally, the hard mask layer includes the silicon nitride layer and silicon oxide layer stacked.
Optionally, the material of the dielectric layer includes silicon nitride.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of imaging sensor, including：Semiconductor substrate, institute
The front for stating semiconductor substrate is formed with Facad structure；Hard mask layer is located at the back side of the semiconductor substrate；Etching groove,
The etching groove runs through the hard mask layer and the semiconductor substrate, and the side wall of the etching groove includes connecting up and down
Upper side wall and lower wall, the angle on the upper side wall and the hard mask layer surface is obtuse angle；Dielectric layer covers the etching
The bottom and side wall of groove, and cover the hard mask layer.
Optionally, the hard mask layer includes the silicon nitride layer and silicon oxide layer stacked.
Optionally, the material of the dielectric layer includes silicon nitride.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In embodiments of the present invention, semiconductor substrate is provided, the back side of the semiconductor substrate is formed with hard mask layer, institute
The front for stating semiconductor substrate is formed with Facad structure；The hard mask layer is performed etching, to form etching groove, the quarter
Etched groove slot runs through the hard mask layer, and the side wall of the etching groove includes the upper side wall to connect up and down and lower wall, it is described on
Side wall and the angle on the hard mask layer surface are obtuse angle；The semiconductor substrate is etched, so that the etching groove runs through institute
State semiconductor substrate；Dielectric layer is formed, the dielectric layer covers the bottom and side wall of the etching groove, and covers and described cover firmly
Film layer.Using the above scheme, by formation through the etching groove of hard mask layer, and the side wall of the etching groove includes up and down
The upper side wall and lower wall to connect, the upper side wall and the angle on the hard mask layer surface are obtuse angle, make the dielectric layer to be formed
Pattern in the open top position of etching groove is more gentle, and middle etching groove is perpendicular to described half compared with the prior art
The direction of conductor substrate extends, and using the scheme of the embodiment of the present invention, can reduce the possibility that hard mask layer problem of Cracking occurs
Property, and since the open-topped width of the etching groove is more than the width of bottom opening, the dielectric layer can be reduced
Have to avoid the formation of the medium hole in etching groove in the possibility that closed-ended question occurs for the top position of etching groove
Help avoid having an impact subsequent technique, improves product quality.
Further, in embodiments of the present invention, expand the width of the opening by being performed etching to mask layer, and
A part for the hard mask layer is exposed, and then makes upper side wall and the institute of the etching groove by etching the hard mask layer
The angle for stating hard mask layer surface is obtuse angle, contributes to the pattern for the open top position for making dielectric layer in etching groove more flat
It is slow.
Further, first etching technics is anisotropic dry etch process.In embodiments of the present invention, pass through
Using the first etching technics, anisotropic etching effect may be implemented, help to make the etching groove perpendicular to described
The direction of semiconductor substrate extends, and helps to make the bottom size of etching groove to meet process requirements.
Further, the third etching technics is isotropic etching technics.In embodiments of the present invention, by using
Isotropic etching effect may be implemented in third etching technics, to make the upper side wall of the etching groove be covered firmly with described
The angle of film surface is obtuse angle, to realize that pattern of the dielectric layer in the open top position of etching groove is more gentle, drop
The possibility of the top position closed-ended question of low generation hard mask layer problem of Cracking and dielectric layer in etching groove.
Description of the drawings
Fig. 1 to Fig. 4 is the corresponding device profile knot of each step in a kind of forming method of imaging sensor in the prior art
Structure schematic diagram；
Fig. 5 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention；
Fig. 6 to Figure 11 is that the corresponding device of each step cuts open in a kind of forming method of imaging sensor in the embodiment of the present invention
Face structural schematic diagram.
Specific implementation mode
In the prior art, a kind of technique of filled media layer generally includes following steps in the trench：It is served as a contrast in semiconductor
The surface at bottom forms hard mask layer, and then etches the hard mask layer, to be formed in perpendicular to the direction of the semiconductor substrate
The etching groove of extension, and then form the dielectric layer for covering the etching groove.
Referring to figs. 1 to Fig. 4, Fig. 1 to Fig. 4 is that each step corresponds in a kind of forming method of imaging sensor in the prior art
Device profile structural schematic diagram.
Referring to Fig.1, semiconductor substrate 100 is provided, the back side of the semiconductor substrate 100 is formed with hard mask layer 110, institute
The front for stating semiconductor substrate 100 is formed with Facad structure 102, is formed with graphically on the surface of the semiconductor substrate 100
Mask layer 120.
In specific implementation, the Facad structure 102 can be fitted according to what the type of specific imaging sensor determined
When semiconductor devices and structure.Such as in rear illuminated image sensor (Back-side Illumination CMOS Image
Sensors, BSI CIS) in, logical device, pixel device and metal can be formed by the front in semiconductor substrate 100
Then interconnection structure is bonded using carrying wafer with the front of the semiconductor substrate, to form the Facad structure 102.
It should be pointed out that the material of the hard mask layer 110 can be selected from：The silicon nitride of silicon nitride, silica, stacking
And silica.
It is hard mask layer 110 described in mask etching with the patterned mask layer 120, to form etching ditch with reference to Fig. 2
Slot 130, the etching groove 130 run through the hard mask layer 110, are to cover with the patterned mask layer 120 further
Film etches the semiconductor substrate 100, so that the etching groove 130 runs through the semiconductor substrate 100.
It in specific implementation, can be with by formation through hard mask layer 110, the etching groove 130 of semiconductor substrate 100
In the subsequent process, by filled media layer, metal material in etching groove 130, to form TSV.
With reference to Fig. 3, the patterned mask layer 120 is removed.
With reference to Fig. 4, dielectric layer 140 is formed, the dielectric layer 140 covers the bottom and side wall of the etching groove 130, and
Cover the hard mask layer 110.
In specific implementation, dielectric layer 140 can generate compression to hard mask layer 110, such as position A in Fig. 4 and position B
Shown, compression of the dielectric layer 140 in the open top position of etching groove 130 is easy to cause hard mask layer 110 and cracks,
Influence subsequent technique and product quality.Especially when the material of the dielectric layer 140 be silicon nitride, on the top of etching groove 130
When the material of the hard mask layer 110 of portion's aperture position is silica, the problem of hard mask layer 110 cracks, can hold
Easily occur.
Further, the dielectric layer 140 is easy that closing phenomenon occurs in the top position C of etching groove, forms etching
Medium hole in groove 130, also can further have an impact subsequent technique and product quality.
The present inventor passes through the study found that conventionally, as the etching groove 130 is perpendicular to institute
The direction for stating semiconductor substrate 100 extends, therefore in the open top position of etching groove 130, the hard mask layer 110 it is upper
The angle of the side wall of surface and the etching groove 130 is close to right angle even acute angle, and the compression of dielectric layer 140 is easy to lead
Cause the problem of Cracking of generation hard mask layer 110.And due to the upper surface of the hard mask layer 110 and the etching groove 130
Side wall angle close to right angle even acute angle, lead to the top position in etching groove 130,130 liang of the etching groove
The dielectric layer 140 of side is closer to, and is easy to happen closed-ended question.
In embodiments of the present invention, semiconductor substrate is provided, the back side of the semiconductor substrate is formed with hard mask layer, institute
The front for stating semiconductor substrate is formed with Facad structure；Patterned mask layer is formed, is covered firmly to described according to the mask layer
Film layer performs etching, and to form etching groove, the etching groove runs through the hard mask layer, the side wall packet of the etching groove
The upper side wall to connect up and down and lower wall are included, the upper side wall and the angle on the hard mask layer surface are obtuse angle；It is covered with described
Film layer is mask, etches the semiconductor substrate, so that the etching groove runs through the semiconductor substrate；Dielectric layer is formed,
The dielectric layer covers the bottom and side wall of the etching groove, and covers the hard mask layer.Using the above scheme, pass through shape
Side wall at the etching groove through hard mask layer, and the etching groove includes the upper side wall to connect up and down and lower wall, institute
It is obtuse angle to state upper side wall and the angle on the hard mask layer surface, makes the dielectric layer to be formed in the open top position of etching groove
Pattern it is more gentle, compared with the prior art in etching groove perpendicular to the direction of the semiconductor substrate extend, use
The scheme of the embodiment of the present invention can reduce the possibility that hard mask layer problem of Cracking occurs, and due to the etching groove
Open-topped width be more than bottom opening width, can reduce the dielectric layer etching groove top position occur
The possibility of closed-ended question helps avoid generating shadow to subsequent technique to avoid the formation of the medium hole in etching groove
It rings, improves product quality.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
With reference to Fig. 5, Fig. 5 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention.Described image
The forming method of sensor may include step S21 to step S24：
Step S21：Semiconductor substrate is provided, the back side of the semiconductor substrate is formed with hard mask layer, the semiconductor
The front of substrate is formed with Facad structure；
Step S22：The hard mask layer is performed etching, to form etching groove, the etching groove is through described hard
Mask layer, the side wall of the etching groove include the upper side wall to connect up and down and lower wall, the upper side wall and the hard mask
The angle of layer surface is obtuse angle；
Step S23：The semiconductor substrate is etched, so that the etching groove runs through the semiconductor substrate；
Step S24：Dielectric layer is formed, the dielectric layer covers the bottom and side wall of the etching groove, and described in covering
Hard mask layer.
Above-mentioned each step is illustrated with reference to Fig. 6 to Figure 11.
Fig. 6 to Figure 11 is that the corresponding device of each step cuts open in a kind of forming method of imaging sensor in the embodiment of the present invention
Face structural schematic diagram.
With reference to Fig. 6, semiconductor substrate 200 is provided, the back side of the semiconductor substrate 200 is formed with hard mask layer 210, institute
The front for stating semiconductor substrate 200 is formed with Facad structure 202, is formed with graphically on the surface of the semiconductor substrate 200
Mask layer 220.
In specific implementation, the semiconductor substrate 200 can be silicon substrate or the material of the semiconductor substrate 200
Material can also be the materials appropriate applied to imaging sensor such as germanium, SiGe, silicon carbide, GaAs or gallium indium, described
Semiconductor substrate 200 can also have outside for the silicon substrate of insulator surface or the germanium substrate of insulator surface, or growth
Prolong the substrate of layer (Epitaxy layer, Epi layer).Preferably, the semiconductor substrate 200 can be half be lightly doped
Conductor substrate, and doping type is opposite with drain region.Specifically, can by the semiconductor substrate 200 carry out ion implanting,
Realize deep trap doping (Deep Well Implant).
It should be pointed out that the Facad structure 202 can be fitted according to what the type of specific imaging sensor determined
When semiconductor devices and structure.Such as in BSI CIS, logic device can be formed by the front in semiconductor substrate 200
Then part, pixel device and metal interconnection structure are bonded using carrying wafer with the front of the semiconductor substrate 200, with
Form the Facad structure 202.
Specifically, the material of the hard mask layer (Hard Mask) 210 can be selected from：Silicon nitride, silica, stacking
Silicon nitride and silica.
Preferably, as shown in fig. 6, the hard mask layer 210 may include the silicon nitride layer 211 and silicon oxide layer stacked
212.In embodiments of the present invention, by select stack silicon nitride layer 211 and silicon oxide layer 212 as the hard mask layer
210, stress of the hard mask layer 210 to semiconductor substrate 200 can be reduced, the performance of imaging sensor is improved.
With reference to Fig. 7, the hard mask layer 210 is performed etching according to the mask layer 220, to form etching groove 230,
The etching groove 230 runs through the hard mask layer 210.
Specifically, on the surface of the hard mask layer 210, the mask layer (Mask) 220, the mask layer 220 are formed
With opening 221.Further, it is hard mask layer described in mask etching with the mask layer 220 using the first etching technics
210, to form etching groove 230, the etching groove 230 runs through the hard mask layer 210.
In specific implementation, first etching technics is anisotropic dry etching (Dry-Etch) technique.
In embodiments of the present invention, by using the first etching technics, anisotropic etching effect may be implemented, help
In making the etching groove 230 perpendicular to the direction of the semiconductor substrate 200 extend, help to make etching groove 230
Bottom size meets process requirements.
As a unrestricted example, the etachable material that first etching technics uses includes carbon tetrafluoride
(CF4, also known as tetrafluoromethane), fluoroform (CHF3), oxygen (O2) and argon gas (Ar), compared to only with CF4And
Ar helps to realize anisotropic etching effect.
Further, the technological parameter of first etching technics can be selected from following one or more：
Etching duration can be 50 seconds to 90 seconds；
Etching temperature can be 30 degrees Celsius to 50 degrees Celsius；
Wherein, the CF4Etched flux can be 100sccm to 300sccm, CHF3Etched flux can be
30sccm to 100sccm, O2Etched flux can be 2sccm to 10sccm, the etched flux of Ar can be 50sccm extremely
200sccm。
The mask layer 220 is performed etching using the second etching technics with reference to Fig. 8, to expand the opening 221
Width, and expose a part for the hard mask layer 210.
As a unrestricted example, the technological parameter of second etching technics can be selected from the next item down or more
：
The etachable material of use may include：O2And N2；
Etching duration can be 30 seconds to 60 seconds；
Etching temperature can be 100 degrees Celsius to 200 degrees Celsius；
Wherein, the O2Etched flux can be 100sccm to 300sccm, N2Etched flux can be 50sccm extremely
200sccm。
Reference Fig. 9 is mask with the mask layer 220 using third etching technics, etches the hard mask layer 210, with
The upper side wall for making the etching groove 230 and the angle a on 210 surface of the hard mask layer are obtuse angle.
Specifically, the side wall of the etching groove 230 includes the upper side wall to connect up and down and lower wall, the upper side wall with
The angle a on 210 surface of the hard mask layer is obtuse angle.
In specific implementation, the third etching technics can be isotropic etching technics.
In embodiments of the present invention, by using third etching technics, isotropic etching effect may be implemented, help
It is obtuse angle in making the angle a of the upper side wall of the etching groove 230 with 210 surface of the hard mask layer.
As a unrestricted example, the material of the hard mask layer 210 includes silica, and the third etches work
Etachable material may include CF4 and Ar used by skill performs etching the silica.
Further, the technological parameter of the third etching technics can be selected from following one or more：
Etching duration can be 30 seconds to 90 seconds；
Etching temperature can be 30 degrees Celsius to 60 degrees Celsius；
Wherein, the CF4Etched flux can be 50sccm to 150sccm, the etched flux of Ar be 10sccm extremely
150sccm。
It is formed using atomic layer deposition (Atomic Layer Deposition, ALD) technique it is possible to further use
The silica has many advantages, such as that compactness is high, quality of forming film is good, and step coverage is good.
In embodiments of the present invention, by being performed etching to mask layer 220 to expand the width of the opening 221, and it is sudden and violent
Expose a part for the hard mask layer 210, and then makes the upper of the etching groove 230 by etching the hard mask layer 210
Side wall and the angle on 210 surface of the hard mask layer are obtuse angle, contribute to the dielectric layer for making to be subsequently formed in etching groove 230
The pattern of open top position is more gentle.
Referring to Fig.1 0, the semiconductor substrate 200 is etched, so that the etching groove 230 runs through the semiconductor substrate
200。
Specifically, the 4th etching technics may be used, with the mask layer 220 (with reference to Fig. 9) for mask, etching described half
Conductor substrate 200.
It should be pointed out that since the width of the opening 221 of the mask layer 220 has been extended, and expose and cover firmly
A part for film layer 210, therefore when etching the semiconductor substrate 200, the hard mask layer 210 also generates covering for a part
Film acts on.
As a unrestricted example, the technological parameter of the 4th etching technics can be selected from the next item down or more
：
The etachable material of use may include：Hydrobromic acid (HBR), sulfur hexafluoride (SF6) and O2；
Etching duration can be 60 seconds to 200 seconds；
Etching temperature can be 30 degrees Celsius to 60 degrees Celsius；
Wherein, the etched flux of the HBR can be 50sccm to 150sccm, SF6Etched flux can be 20sccm
To 100sccm, O2Etched flux can be 20sccm to 60sccm.
Further, the patterned mask layer 220 is removed.
Specifically, the 5th etching technics may be used, remove the patterned mask layer 220.
As a unrestricted example, the technological parameter of the 5th etching technics can be selected from the next item down or more
：
The etachable material of use may include：O2And N2；
Etching duration can be 30 seconds to 60 seconds；
Etching temperature can be 100 degrees Celsius to 300 degrees Celsius；
Wherein, the O2Etched flux can be 200sccm to 500sccm, N2Etched flux can be 50sccm extremely
200sccm。
Referring to Fig.1 1, dielectric layer 240 is formed, the dielectric layer 240 covers the bottom and side wall of the etching groove 230,
And cover the hard mask layer 210.
Specifically, the material of the dielectric layer may include silicon nitride.
In embodiments of the present invention, the etching groove 230 of hard mask layer 210, and the etching groove are run through by formation
230 side wall includes the upper side wall to connect up and down and lower wall, and the upper side wall and the angle on 210 surface of the hard mask layer are
Obtuse angle keeps dielectric layer 240 more gentle in the pattern of the open top position of etching groove 230, middle compared with the prior art to carve
Etched groove slot extends perpendicular to the direction of the semiconductor substrate, and using the scheme of the embodiment of the present invention, it is hard can to reduce generation
The possibility of 210 problem of Cracking of mask layer, and since the open-topped width of the etching groove 230 is more than bottom opening
Width, can reduce the dielectric layer 240 etching groove 230 top position occur closed-ended question possibility, to
The medium hole in etching groove 230 is avoided the formation of, helps avoid having an impact subsequent technique, improves product quality.
The embodiment of the present invention additionally provides a kind of imaging sensor, and referring to Fig.1 1, described image sensor may include：
The front of semiconductor substrate 200, the semiconductor substrate 200 is formed with Facad structure 202；
Hard mask layer 210 is located at the back side of the semiconductor substrate 200；
Etching groove 230, the etching groove 230 run through the hard mask layer 210 and the semiconductor substrate 200,
The side wall of the etching groove 230 includes the upper side wall to connect up and down and lower wall, the upper side wall and the hard mask layer 210
The angle on surface is obtuse angle；
Dielectric layer 240, covers the bottom and side wall of the etching groove 230, and covers the hard mask layer 210.
Further, the hard mask layer 210 may include the silicon nitride layer 211 stacked and silicon oxide layer 212.
Further, the material of the dielectric layer 240 may include silicon nitride.
In specific implementation, complete TSV knots can also have been formed by filling metal material in the etching groove 230
Structure and then formation aluminum cushion layer (Pad), metallic grid (Metal Grid), filter structure (Filter), passivation layer
Late stage process such as (Passivation Layer).
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of imaging sensor, which is characterized in that including：
Semiconductor substrate is provided, the back side of the semiconductor substrate is formed with hard mask layer, the positive shape of the semiconductor substrate
At there is Facad structure；
The hard mask layer is performed etching, to form etching groove, the etching groove runs through the hard mask layer, the quarter
The side wall of etched groove slot includes the upper side wall to connect up and down and lower wall, and the upper side wall and the angle on the hard mask layer surface are
Obtuse angle；
The semiconductor substrate is etched, so that the etching groove runs through the semiconductor substrate；
Dielectric layer is formed, the dielectric layer covers the bottom and side wall of the etching groove, and covers the hard mask layer.
2. the forming method of imaging sensor according to claim 1, which is characterized in that it is described to the hard mask layer into
Row etches, and includes to form etching groove：
On the surface of the hard mask layer, patterned mask layer is formed, the patterned mask layer has opening；
Using the first etching technics, using the patterned mask layer as hard mask layer described in mask etching, to form etching ditch
Slot, the etching groove run through the hard mask layer；
Using the second etching technics, the patterned mask layer is performed etching, to expand the width of the opening, and exposure
Go out a part for the hard mask layer；
The hard mask layer is etched using the patterned mask layer as mask using third etching technics, so that the etching
The upper side wall of groove and the angle on the hard mask layer surface are obtuse angle.
3. the forming method of imaging sensor according to claim 2, which is characterized in that first etching technics is each
The dry etch process of anisotropy.
4. the forming method of imaging sensor according to claim 2, which is characterized in that the third etching technics is each
To the etching technics of the same sex.
5. the forming method of imaging sensor according to claim 2, which is characterized in that the formation dielectric layer it
Before, further include：
Remove the mask layer.
6. the forming method of imaging sensor according to any one of claims 1 to 5, which is characterized in that the hard mask
Layer includes the silicon nitride layer and silicon oxide layer stacked.
7. the forming method of imaging sensor according to any one of claims 1 to 5, which is characterized in that the dielectric layer
Material include silicon nitride.
8. a kind of imaging sensor, which is characterized in that including：
The front of semiconductor substrate, the semiconductor substrate is formed with Facad structure；
Hard mask layer is located at the back side of the semiconductor substrate；
Etching groove, the etching groove run through the hard mask layer and the semiconductor substrate, the side of the etching groove
Wall includes the upper side wall to connect up and down and lower wall, and the upper side wall and the angle on the hard mask layer surface are obtuse angle；
Dielectric layer, covers the bottom and side wall of the etching groove, and covers the hard mask layer.
9. imaging sensor according to claim 8, which is characterized in that the hard mask layer includes the silicon nitride layer stacked
And silicon oxide layer.
10. the forming method of imaging sensor according to claim 8, which is characterized in that the material packet of the dielectric layer
Include silicon nitride.
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| CN201810399604.6A CN108470745A (en) | 2018-04-28 | 2018-04-28 | Imaging sensor and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097075A (en) * | 2020-01-08 | 2021-07-09 | 华邦电子股份有限公司 | Semiconductor device and method of forming the same |
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| US20110212616A1 (en) * | 2010-02-26 | 2011-09-01 | Robert Seidel | Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding |
| CN104051423A (en) * | 2013-03-13 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect apparatus and method |
| CN104956468A (en) * | 2013-02-08 | 2015-09-30 | 德克萨斯仪器股份有限公司 | Method of forming metal contact opening |
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| JP2003282700A (en) * | 2002-03-25 | 2003-10-03 | Semiconductor Leading Edge Technologies Inc | Hole forming method |
| US20110212616A1 (en) * | 2010-02-26 | 2011-09-01 | Robert Seidel | Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding |
| CN104956468A (en) * | 2013-02-08 | 2015-09-30 | 德克萨斯仪器股份有限公司 | Method of forming metal contact opening |
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