CN108462170B - Automatic voltage paralleling and switching control method for interval merging unit of intelligent substation - Google Patents
Automatic voltage paralleling and switching control method for interval merging unit of intelligent substation Download PDFInfo
- Publication number
- CN108462170B CN108462170B CN201810295627.2A CN201810295627A CN108462170B CN 108462170 B CN108462170 B CN 108462170B CN 201810295627 A CN201810295627 A CN 201810295627A CN 108462170 B CN108462170 B CN 108462170B
- Authority
- CN
- China
- Prior art keywords
- bus
- input
- voltage
- gate
- mother
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000000926 separation method Methods 0.000 claims description 27
- 238000010586 diagram Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
-
- H02J3/005—
Abstract
The invention relates to an automatic voltage paralleling and switching control method for an interval merging unit of an intelligent substation, which comprises a voltage paralleling module and a voltage switching module, wherein the voltage paralleling module acquires a bus voltage I, a bus voltage II, a bus-coupled bus knife switch I position, a bus-coupled breaker position and a bus-coupled bus knife switch II position, and transmits the paralleled voltage to the voltage switching module after automatic paralleling logic; the voltage switching module receives the parallel I mother voltage and the parallel II mother voltage transmitted by the voltage parallel module, the interval I mother knife switch position and the interval II mother knife switch position, and transmits the switched voltage subjected to automatic switching logic to the protection device. According to the invention, the voltage parallel and switching functions of the intelligent transformer substation are integrated into the respective interval merging units, and the interval merging units are overhauled without influencing the acquisition of other interval voltages and current quantities, so that the overhauling flexibility of the secondary equipment of the power grid is improved.
Description
Technical Field
The invention relates to the technical field of automatic voltage paralleling and switching of intelligent substations, in particular to a method for controlling automatic voltage paralleling and switching of an interval merging unit of an intelligent substation.
Background
At present, a bus merging unit in an intelligent substation provides bus voltage for a plurality of intervals at the same time, so that the bus merging unit is difficult to arrange maintenance work and needs to be operated without being maintained for a long time. Once the bus merging unit breaks down or needs to eliminate defects, voltages at relevant intervals are affected, protection misoperation is easy to occur, the accident range is enlarged, and safe and stable operation of a power grid is threatened. In addition, because the mechanism stroke of the PT disconnecting link is long, the switching time of the on-off state of the disconnecting link is long, and when the voltage is automatically paralleled and switched only by adopting the on-off state of the disconnecting link, the voltage is lost for a long time at relevant intervals, so that the manual parallel mode is mostly adopted at present, and the manual misoperation is easy to occur.
Disclosure of Invention
In view of this, the present invention provides a method for controlling voltage automatic paralleling and switching between interval merging units of an intelligent substation.
In order to achieve the purpose, the invention adopts the following technical scheme:
an automatic voltage paralleling and switching control method for an interval merging unit of an intelligent substation is characterized by comprising the following steps: the voltage parallel module collects a bus voltage I, a bus voltage II, a bus-coupled bus knife switch I position, a bus-coupled breaker position and a bus-coupled bus knife switch II position, and transmits the parallel voltage to the voltage switching module after automatic parallel logic; the voltage switching module receives the parallel I mother voltage and the parallel II mother voltage transmitted by the voltage parallel module, the interval I mother knife switch position and the interval II mother knife switch position, and finally transmits the switched voltage subjected to automatic switching logic to the protection device; the voltage parallel module consists of an I bus voltage automatic parallel logic circuit and an II bus voltage automatic parallel logic circuit.
The I mother voltage automatic parallel logic circuit comprises a double-input OR gate H11, a five-input AND gate Y11, a three-input OR gate H12, a four-input AND gate Y12 and a double-input AND gate Y13, wherein the position separation bit of the I mother PT disconnecting link and the position invalid bit of the I mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of the double-input OR gate H11; the position of the II bus PT disconnecting link is closed, the output end of a double-input OR gate H11, the position of a bus coupler breaker, the position of the I bus disconnecting link of the bus coupler and the position of the II bus disconnecting link of the bus coupler are closed, and the two bus disconnecting links are respectively connected to first to fifth input terminals of a five-input AND gate Y11; the position separation of the bus tie breaker, the position separation of the bus tie I bus bar switch and the position separation of the bus tie II bus bar switch are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H12; the position of the bus tie breaker, the position of the bus knife switch I, the position of the bus knife switch II and the position of the bus PT knife switch I are respectively connected to first to fourth input terminals of a four-input AND gate Y12; the output end of the three-input OR gate H12 and the position of the I mother PT disconnecting link are switched on and respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y13; if two buses run in parallel, the position of the first mother PT disconnecting link is separated or invalid, and the position of the second mother PT disconnecting link is closed, the first mother voltage output after parallel is actually input as a second mother voltage; if two buses run in parallel and the PT disconnecting link of the bus I is in a closed position, the output of the bus I is still the input bus I voltage after the bus I is connected in parallel; if two buses operate in a row and the position of the first bus PT disconnecting link is closed, the first bus voltage output is still the input first bus voltage after the two buses operate in a row.
The II-mother voltage automatic parallel logic circuit comprises a double-input OR gate H21, a five-input AND gate Y21, a three-input OR gate H22, a four-input AND gate Y22 and a double-input AND gate Y23, wherein the position separation position and the position invalid position of the II-mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of the double-input OR gate H21; the position of the I bus PT disconnecting link is closed, the output end of a double-input OR gate H21, the position of a bus coupler breaker, the position of the I bus disconnecting link of the bus coupler and the position of the II bus disconnecting link of the bus coupler are closed, and the I bus disconnecting link and the II bus disconnecting link are respectively connected to first to fifth input terminals of a five-input AND gate Y21; the position separation of the bus tie breaker, the position separation of the bus tie I bus bar switch and the position separation of the bus tie II bus bar switch are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H22; the position of the bus tie breaker, the position of the bus tie I bus knife switch, the position of the bus tie II bus knife switch and the position of the bus PT switch are respectively connected to first to fourth terminals of a four-input AND gate Y22; the output end of the three-input OR gate H22 and the position of the II-mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y23 in a closed position; if two buses run in parallel, the position of the II mother PT disconnecting link is separated or invalid, and the position of the I mother PT disconnecting link is closed, the output of the II mother voltage after the two buses run in parallel is actually the I mother voltage; if two buses run in parallel and the PT disconnecting link of the second bus is in a closed position, the output voltage of the second bus is still the voltage of the second bus after the two buses run in parallel; if the two buses operate in a row and the position of the II-bus PT disconnecting link is closed, the output of the II-bus voltage is still the II-bus voltage after the two buses operate in a row.
The voltage switching module comprises a three-input OR gate H31, a three-input OR gate H32, a two-input AND gate Y31, a two-input AND gate Y32, a three-input AND gate Y33 and a three-input AND gate Y34, wherein an interval II mother blade gate separation bit, an interval II mother blade gate invalid bit and an interval II mother blade gate invalid bit are respectively connected to first, second and third input terminals of the three-input OR gate H31; the closing position of the interval I female knife switch and the output end of a three-input OR gate H31 are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y31; the output ends of the I mother voltage after parallel, the II mother voltage after parallel and the double-input AND gate Y31 are respectively connected to a first input terminal, a second input terminal and a third input terminal of a three-input AND gate Y33; the interval I mother disconnecting link is switched off, the interval I mother disconnecting link invalid bit and the interval I mother disconnecting link invalid bit are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H32; the closing position of the interval II mother knife switch and the output end of a three-input OR gate H32 are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y32; the output ends of the I mother voltage after parallel, the II mother voltage after parallel and the double-input AND gate Y32 are respectively connected to a first input terminal, a second input terminal and a third input terminal of a three-input AND gate Y34; when the logic meets the output of the three-input AND gate Y33, the switched voltage output by the voltage switching module is the I parent voltage after being paralleled; when the logic satisfies the three-input AND gate Y34, the switched voltage output by the voltage switching module is the parallel second-mother voltage.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the voltage parallel and switching functions of the intelligent transformer substation are integrated into the merging units at the intervals, the merging units at the intervals are overhauled without influencing the acquisition of the voltage and current quantities at other intervals, and the overhauling flexibility of the secondary equipment of the power grid is improved.
2. When the interval merging unit of the invention breaks down or needs to eliminate defects, the power failure range is limited to the interval, and the operation of other intervals can not be influenced.
3. The invention can realize the automatic voltage paralleling and switching functions of the intelligent transformer substation, avoids the possibility of manual misoperation, reduces the workload of operation and maintenance personnel and ensures the safe and stable operation of a power grid.
4. The invention introduces the invalid state of the disconnecting link into the criterion, shortens the time of automatic paralleling and switching of the voltage, and solves the problems that the time of on-off state switching of the disconnecting link is longer due to longer stroke of a disconnecting link mechanism, and the voltage is lost for a long time at relevant intervals when the voltage is automatically paralleling and switching only by adopting the on-off state of the disconnecting link.
Drawings
FIG. 1 is a connection diagram of a primary and secondary device according to the present invention
FIG. 2 is a schematic diagram of an I-bus voltage automatic parallel logic circuit of the present invention
FIG. 3 is a schematic diagram of an automatic parallel logic circuit for II bus voltages of the present invention
Fig. 4 is a schematic diagram of the gap voltage switching module of the present invention.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
Referring to fig. 1, the invention provides a method for controlling voltage automatic paralleling and switching of an interval merging unit of an intelligent substation, which is characterized in that: the voltage parallel module collects a bus voltage I, a bus voltage II, a bus-coupled bus knife switch I position, a bus-coupled breaker position and a bus-coupled bus knife switch II position, and transmits the parallel voltage to the voltage switching module after automatic parallel logic; the voltage switching module receives the parallel I mother voltage and the parallel II mother voltage transmitted by the voltage parallel module, the interval I mother knife switch position and the interval II mother knife switch position, and finally transmits the switched voltage subjected to automatic switching logic to the protection device; the voltage parallel module consists of an I bus voltage automatic parallel logic circuit and an II bus voltage automatic parallel logic circuit.
Referring to fig. 2, the i-mother voltage automatic parallel logic module includes a two-input or gate H11, a five-input and gate Y11, a three-input or gate H12, a four-input and gate Y12, and a two-input and gate Y13, wherein the i-mother PT switch position separation bit and the i-mother PT switch position invalid bit are respectively connected to first and second input terminals of the two-input or gate H11; the position of the II bus PT disconnecting link is closed, the output end of a double-input OR gate H11, the position of a bus coupler breaker, the position of the I bus disconnecting link of the bus coupler and the position of the II bus disconnecting link of the bus coupler are closed, and the two bus disconnecting links are respectively connected to first to fifth input terminals of a five-input AND gate Y11; the position separation of the bus tie breaker, the position separation of the bus tie I bus bar switch and the position separation of the bus tie II bus bar switch are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H12; the position of the bus tie breaker, the position of the bus knife switch I, the position of the bus knife switch II and the position of the bus PT knife switch I are respectively connected to first to fourth input terminals of a four-input AND gate Y12; the output end of the three-input OR gate H12 and the position of the I mother PT disconnecting link are switched on and respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y13; if two buses run in parallel, the position of the first mother PT disconnecting link is separated or invalid, and the position of the second mother PT disconnecting link is closed, the first mother voltage output after parallel is actually input as a second mother voltage; if two buses run in parallel and the PT disconnecting link of the bus I is in a closed position, the output of the bus I is still the input bus I voltage after the bus I is connected in parallel; if two buses operate in a row and the position of the first bus PT disconnecting link is closed, the first bus voltage output is still the input first bus voltage after the two buses operate in a row.
Referring to fig. 3, the ii-mother voltage automatic parallel logic includes a two-input or gate H21, a five-input and gate Y21, a three-input or gate H22, a four-input and gate Y22, and a two-input and gate Y23, wherein a ii-mother PT switch position separation bit and a ii-mother PT switch position invalid bit are respectively connected to first and second input terminals of the two-input or gate H21; the position of the I bus PT disconnecting link is closed, the output end of a double-input OR gate H21, the position of a bus coupler breaker, the position of the I bus disconnecting link of the bus coupler and the position of the II bus disconnecting link of the bus coupler are closed, and the I bus disconnecting link and the II bus disconnecting link are respectively connected to first to fifth input terminals of a five-input AND gate Y21; the position separation of the bus tie breaker, the position separation of the bus tie I bus bar switch and the position separation of the bus tie II bus bar switch are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H22; the position of the bus tie breaker, the position of the bus tie I bus knife switch, the position of the bus tie II bus knife switch and the position of the bus PT switch are respectively connected to first to fourth terminals of a four-input AND gate Y22; the output end of the three-input OR gate H22 and the position of the II-mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y23 in a closed position; if two buses run in parallel, the position of the II mother PT disconnecting link is separated or invalid, and the position of the I mother PT disconnecting link is closed, the output of the II mother voltage after the two buses run in parallel is actually the I mother voltage; if two buses run in parallel and the PT disconnecting link of the second bus is in a closed position, the output voltage of the second bus is still the voltage of the second bus after the two buses run in parallel; if the two buses operate in a row and the position of the II-bus PT disconnecting link is closed, the output of the II-bus voltage is still the II-bus voltage after the two buses operate in a row.
Referring to fig. 4, the voltage switching module includes a three-input or gate H31, a three-input or gate H32, a two-input and gate Y31, a two-input and gate Y32, a three-input and gate Y33, and a three-input and gate Y34, wherein the interval ii mother blade gate separation bit, the interval ii mother blade gate invalid bit, and the interval ii mother blade gate invalid bit are respectively connected to the first, second, and third input terminals of the three-input or gate H31; the closing position of the interval I female knife switch and the output end of a three-input OR gate H31 are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y31; the output ends of the I mother voltage after parallel, the II mother voltage after parallel and the double-input AND gate Y31 are respectively connected to a first input terminal, a second input terminal and a third input terminal of a three-input AND gate Y33; the interval I mother disconnecting link is switched off, the interval I mother disconnecting link invalid bit and the interval I mother disconnecting link invalid bit are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H32; the closing position of the interval II mother knife switch and the output end of a three-input OR gate H32 are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y32; the output ends of the I mother voltage after parallel, the II mother voltage after parallel and the double-input AND gate Y32 are respectively connected to a first input terminal, a second input terminal and a third input terminal of a three-input AND gate Y34; when the logic meets the output of the three-input AND gate Y33, the switched voltage output by the voltage switching module is the I parent voltage after being paralleled; when the logic satisfies the three-input AND gate Y34, the switched voltage output by the voltage switching module is the parallel second-mother voltage.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (1)
1. An automatic voltage paralleling and switching control method for an interval merging unit of an intelligent substation is characterized by comprising the following steps: the voltage parallel module collects a bus voltage I, a bus voltage II, a bus-coupled bus knife switch I position, a bus-coupled breaker position and a bus-coupled bus knife switch II position, and transmits the parallel voltage to the voltage switching module after automatic parallel logic; the voltage switching module receives the parallel I bus voltage and the parallel II bus voltage transmitted by the voltage parallel module, the position of the interval I bus switch and the position of the interval II bus switch, and finally transmits the switched voltage subjected to automatic switching logic to the protection device; the voltage parallel module consists of an I bus voltage automatic parallel logic circuit and an II bus voltage automatic parallel logic circuit;
the I mother voltage automatic parallel logic circuit comprises a double-input OR gate H11, a five-input AND gate Y11, a three-input OR gate H12, a four-input AND gate Y12 and a double-input AND gate Y13, wherein the position separation bit of the I mother PT disconnecting link and the position invalid bit of the I mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of the double-input OR gate H11; the position of the II bus PT disconnecting link is closed, the output end of a double-input OR gate H11, the position of a bus coupler breaker, the position of the I bus disconnecting link of the bus coupler and the position of the II bus disconnecting link of the bus coupler are closed, and the two bus disconnecting links are respectively connected to first to fifth input terminals of a five-input AND gate Y11; the position separation of the bus tie breaker, the position separation of the bus tie I bus bar switch and the position separation of the bus tie II bus bar switch are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H12; the position of the bus tie breaker, the position of the bus knife switch I, the position of the bus knife switch II and the position of the bus PT knife switch I are respectively connected to first to fourth input terminals of a four-input AND gate Y12; the output end of the three-input OR gate H12 and the position of the I mother PT disconnecting link are switched on and respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y13; if two buses run in parallel, the position of the first mother PT disconnecting link is separated or invalid, and the position of the second mother PT disconnecting link is closed, the first mother voltage output after parallel is actually input as a second mother voltage; if two buses run in parallel and the PT disconnecting link of the bus I is in a closed position, the output of the bus I is still the input bus I voltage after the bus I is connected in parallel; if the two buses operate in a row and the PT disconnecting link of the first bus is in a closed position, the output of the first bus voltage after the two buses are connected in parallel is still the input first bus voltage;
the II-mother voltage automatic parallel logic circuit comprises a double-input OR gate H21, a five-input AND gate Y21, a three-input OR gate H22, a four-input AND gate Y22 and a double-input AND gate Y23, wherein the position separation position and the position invalid position of the II-mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of the double-input OR gate H21; the position of the I bus PT disconnecting link is closed, the output end of a double-input OR gate H21, the position of a bus coupler breaker, the position of the I bus disconnecting link of the bus coupler and the position of the II bus disconnecting link of the bus coupler are closed, and the I bus disconnecting link and the II bus disconnecting link are respectively connected to first to fifth input terminals of a five-input AND gate Y21; the position separation of the bus tie breaker, the position separation of the bus tie I bus bar switch and the position separation of the bus tie II bus bar switch are respectively connected into a first input terminal, a second input terminal and a third input terminal of a three-input OR gate H22; the position of the bus tie breaker, the position of the bus tie I bus knife switch, the position of the bus tie II bus knife switch and the position of the bus PT switch are respectively connected to first to fourth terminals of a four-input AND gate Y22; the output end of the three-input OR gate H22 and the position of the II-mother PT disconnecting link are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y23 in a closed position; if two buses run in parallel, the position of the II mother PT disconnecting link is separated or invalid, and the position of the I mother PT disconnecting link is closed, the output of the II mother voltage after the two buses run in parallel is actually the I mother voltage; if two buses run in parallel and the PT disconnecting link of the second bus is in a closed position, the output voltage of the second bus is still the voltage of the second bus after the two buses run in parallel; if the two buses operate in a row and the PT disconnecting link of the second bus is in a closed position, the output voltage of the second bus is still the voltage of the second bus after the two buses are connected in parallel;
the voltage switching module comprises a three-input OR gate H31, a three-input OR gate H32, a two-input AND gate Y31, a two-input AND gate Y32, a three-input AND gate Y33 and a three-input AND gate Y34, wherein the local interval II mother blade gate separation bit, the local interval II mother blade gate invalid bit and the local interval II mother blade gate invalid bit are respectively connected to a first input terminal, a second input terminal and a third input terminal of the three-input OR gate H31; the closing position of the female knife switch at the interval I and the output end of a three-input OR gate H31 are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y31; the output ends of the I mother voltage after parallel, the II mother voltage after parallel and the double-input AND gate Y31 are respectively connected to a first input terminal, a second input terminal and a third input terminal of a three-input AND gate Y33; the first input terminal, the second input terminal and the third input terminal of the three-input OR gate H32 are respectively connected with the first disconnecting link of the interval I, the second disconnecting link invalid bit of the interval I and the third disconnecting link invalid bit of the interval I; the closing position of the interval II mother knife switch and the output end of a three-input OR gate H32 are respectively connected to a first input terminal and a second input terminal of a double-input AND gate Y32; the output ends of the I mother voltage after parallel, the II mother voltage after parallel and the double-input AND gate Y32 are respectively connected to a first input terminal, a second input terminal and a third input terminal of a three-input AND gate Y34; when the logic meets the output of the three-input AND gate Y33, the switched voltage output by the voltage switching module is the I parent voltage after being paralleled; when the logic satisfies the three-input AND gate Y34, the switched voltage output by the voltage switching module is the parallel second-mother voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810295627.2A CN108462170B (en) | 2018-04-04 | 2018-04-04 | Automatic voltage paralleling and switching control method for interval merging unit of intelligent substation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810295627.2A CN108462170B (en) | 2018-04-04 | 2018-04-04 | Automatic voltage paralleling and switching control method for interval merging unit of intelligent substation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108462170A CN108462170A (en) | 2018-08-28 |
| CN108462170B true CN108462170B (en) | 2021-05-14 |
Family
ID=63234708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810295627.2A Active CN108462170B (en) | 2018-04-04 | 2018-04-04 | Automatic voltage paralleling and switching control method for interval merging unit of intelligent substation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108462170B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109660020B (en) * | 2018-11-09 | 2022-09-20 | 国网江苏省电力有限公司检修分公司 | Bus voltage intelligent selection and switching device and method |
| CN112965021A (en) * | 2021-02-05 | 2021-06-15 | 西安热工研究院有限公司 | Transformer substation bus PT voltage-passing system and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400524A (en) * | 2013-08-05 | 2013-11-20 | 国家电网公司 | Method and system for realizing relay protection and secondary circuit debugging visualization |
| JP2014093823A (en) * | 2012-11-01 | 2014-05-19 | Mitsubishi Electric Corp | Merging unit and analysis system |
| CN104993572A (en) * | 2015-05-12 | 2015-10-21 | 国家电网公司 | Novel voltage paralleling switching handle and method for using same |
| CN105071383A (en) * | 2015-08-07 | 2015-11-18 | 国家电网公司 | Automatic voltage switching control circuit for merging unit of intelligent substation |
| CN106254124A (en) * | 2016-08-17 | 2016-12-21 | 许继集团有限公司 | A kind of Intelligent substation merging unit collocation method improved based on short address |
| CN107273643A (en) * | 2017-07-18 | 2017-10-20 | 国网福建省电力有限公司 | A kind of intelligent substation interval runs software realistically displayed method |
-
2018
- 2018-04-04 CN CN201810295627.2A patent/CN108462170B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014093823A (en) * | 2012-11-01 | 2014-05-19 | Mitsubishi Electric Corp | Merging unit and analysis system |
| CN103400524A (en) * | 2013-08-05 | 2013-11-20 | 国家电网公司 | Method and system for realizing relay protection and secondary circuit debugging visualization |
| CN104993572A (en) * | 2015-05-12 | 2015-10-21 | 国家电网公司 | Novel voltage paralleling switching handle and method for using same |
| CN105071383A (en) * | 2015-08-07 | 2015-11-18 | 国家电网公司 | Automatic voltage switching control circuit for merging unit of intelligent substation |
| CN106254124A (en) * | 2016-08-17 | 2016-12-21 | 许继集团有限公司 | A kind of Intelligent substation merging unit collocation method improved based on short address |
| CN107273643A (en) * | 2017-07-18 | 2017-10-20 | 国网福建省电力有限公司 | A kind of intelligent substation interval runs software realistically displayed method |
Non-Patent Citations (1)
| Title |
|---|
| 智能变电站扩建间隔合并单元同步测试方法研究;罗志平等;《湖南电力》;20161231;第36卷(第6期);第21-25页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108462170A (en) | 2018-08-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9941739B2 (en) | Process bus associated protective control system, merging unit, and calculation device | |
| CN108462170B (en) | Automatic voltage paralleling and switching control method for interval merging unit of intelligent substation | |
| CN102801207A (en) | Backup auto-switching voltage loss start interlocking method for multi-power double-bus substation | |
| CN106532904A (en) | Double bus-powered PT secondary voltage switching circuit and protection circuit thereof | |
| CN204481568U (en) | A kind of power plant is standby throws protective device | |
| CN106712017B (en) | Double-bus secondary voltage switching circuit and self-holding circuit thereof | |
| CN105044430A (en) | Branch current detection method and system of double-bus distribution equipment parallel outlet wires | |
| CN202363966U (en) | Automatic switching device for emergency power supply | |
| CN105006881B (en) | One kind hauling oneself willingly into runback control system | |
| CN204886396U (en) | Haul oneself willingly into runback control system | |
| CN101860075A (en) | Three-power supply automatic switching device | |
| CN103647280A (en) | Intelligent two-circuit feeding connection controller and control method | |
| CN103972865A (en) | Control method for preventing motor from being switched into short-circuit fault | |
| CN103941155B (en) | High-voltage switch gear control loop template domain identification circuit and discrimination method | |
| EP2500208B2 (en) | Protective circuit assembly | |
| CN204794329U (en) | Single -phase electric dual supply automatic switching control equipment | |
| CN210724305U (en) | Fault guiding safety device, power utilization safety system, multi-path power utilization safety system and automatic bus transfer interlocking control system | |
| CN108695968B (en) | Bus PT parallel system | |
| CN105021853B (en) | Adjustable jump closes the fast of time and tests analog switch device conscientiously | |
| CN103728529B (en) | A kind of switch gap condition discrimination method | |
| CN110729716B (en) | Circuit for sharing auxiliary contact for double-bus inverted bus operation | |
| CN102437520B (en) | Control circuit board of power distribution cabinet | |
| CN106026348B (en) | Low voltage liaison net circuit system and its operating method | |
| CN203759172U (en) | Switch gap status discrimination device | |
| CN204992551U (en) | Network reconsitution equipment during 10kV feeder trouble |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |