CN108449109B - Slave control interface device for radio frequency front-end device - Google Patents
Slave control interface device for radio frequency front-end device Download PDFInfo
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- CN108449109B CN108449109B CN201810465503.4A CN201810465503A CN108449109B CN 108449109 B CN108449109 B CN 108449109B CN 201810465503 A CN201810465503 A CN 201810465503A CN 108449109 B CN108449109 B CN 108449109B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
Abstract
The invention discloses a slave control interface device of a radio frequency front end device, which is based on MIPI RFFE v2.0 protocol and can be integrated on a whole chip, and the invention is fully built by adopting a digital logic unit and a basic circuit element, so that the on-chip integration of a slave controller circuit is easy to realize, the slave controller can be integrated into the radio frequency front end element chip, and the flexible control of the radio frequency front end element can be realized only through three signal wires VIO, SCLK, SDAT of a MIPI RFFE interface. The invention has the advantages that the output pins of the processor are fewer, so that the area of the printed circuit board occupied by the control signals is also fewer, and additional board-level components are not needed, so that the invention has lower cost for implementing the invention, occupies smaller equipment space, is beneficial to the miniaturization and low-cost design of mobile equipment, and is very suitable for controlling various radio frequency front-end devices in the mobile industry.
Description
Technical Field
The invention belongs to the technical field of mobile communication, and particularly relates to a design of a slave control interface device of a radio frequency front-end device.
Background
With the rapid development of mobile communication technology, modern mobile products such as mobile phones, mobile computers, and the like are being developed toward lighter and thinner devices. In addition to the use of radio frequency transceivers, radio frequency front end devices such as power amplifiers, low noise amplifiers, filters, switches, power management modules, and antenna tuners are widely used in these modern mobile communication devices. Most of these rf front-end devices are controlled and mode configured by the master via a digital bus.
In order to unify industry specifications, many standardization organizations have established communication standards for mobile devices. Of these, the most attractive and widely used is the radio frequency front end (Radio Frequency Front End, RFFE) control interface established by the mobile industry processor interface (Mobile Industry Processor Interface, MIPI) alliance. The MIPI PFFE interface is a simple interface for a radio frequency system, and can be integrated by a small number of logic devices so as to reduce the investment of cost. The MIPI RFFE control interface uses three signal lines, where SCLK is the bus clock signal line, SDAT is the bus data signal line, VIO is the bus voltage reference/supply line. The interface can realize high-speed data transmission, is simple and easy to use, and is widely applied to radio frequency front-end devices in the mobile industry at present.
In order to realize the control of the radio frequency front-end device through the MIPI RFFE interface, methods such as direct control or control through programmable logic devices such as FPGA and the like can be adopted. As shown in fig. 1, the control of the rf front-end device may be directly implemented by a mobile device processor, where the processor outputs a series of control signals CTRL1, CTRL2, CTRL3, …, CTRLN-1, CTRLN to directly control the rf front-end devices such as a power management module, a rf switch, a filter, a low noise amplifier, and a power amplifier in the mobile device. The direct control method is simple and easy to use, but consumes a large number of processor output pins, and also consumes a large area of printed circuit board for signal routing, which is obviously not feasible today when mobile devices gradually tend to be miniaturized, and is costly due to the large printed circuit board area.
As shown in fig. 2, the control of the radio frequency front end device may also be indirectly controlled by the FPGA through the MIPI RFFE interface. The processor of the mobile device controls the FPGA via three signal lines VIO, SCLK, SDAT of the MIPI RFFE interface, which outputs a series of control signals CTRL1, CTRL2, CTRL3, …, CTRLN-1, CTRLN to control radio frequency front end devices such as power management modules, radio frequency switches, filters, low noise amplifiers and power amplifiers inside the mobile device. Compared with the method of directly controlling the processor, the method consumes fewer output pins of the processor, thus consuming fewer processor resources and occupying fewer printed circuit board areas by the signal wiring. However, this method needs to occupy additional printed circuit board area to place programmable logic devices such as FPGAs and provide control signal wiring from FPGAs to rf front-end devices, and consumes more circuit board area. And the use of additional FPGA devices increases the cost and is also disadvantageous for the miniaturization of the mobile device.
In addition, in order to achieve the output of 32 8-bit register data (from REGDATA0[7:0] to REGDATA31[7:0 ]) as shown in FIG. 3, a conventional configurable register scheme requires the use of 32 output registers, as shown by D1 through D32 in FIG. 3. Whether or not the internal register data is output and the number of outputs are selected by controlling the enable pin ENA of each output register. If the data of the internal 32 registers needs to be all output, 32 output registers need to be used, and there are 32 groups of 8-bit output pins (from OUT0[7:0] to OUT31[7:0 ]). So in the conventional scheme, if data of 32 8-bit registers is to be output, 32 sets of 8-bit output pins, that is, 256 output pins, are required. Therefore, the conventional configurable register scheme consumes more output pin resources when more register data is required to be output, and therefore occupies more chip area, which is not beneficial to the requirement of device miniaturization.
Disclosure of Invention
The invention aims to solve the problems in the prior art, and provides a slave control interface device of a radio frequency front end device, which is based on the MIPI RFFE v2.0 protocol, can be integrated on a whole chip, does not need to use additional board-level components, occupies smaller equipment space and is beneficial to miniaturization and low-cost design of mobile equipment.
The technical scheme of the invention is as follows: a slave control interface device of a radio frequency front-end device comprises an interface logic module, a data decoding module and a configurable register module which are connected in sequence. The input end of the interface logic module is the input end of the slave control interface device and is respectively connected with the bus clock signal line SCLK, the bus data signal line SDAT and the bus voltage reference/power supply line VIO. The data decoding module is used for decoding the received bus data, the input end of the data decoding module is connected with the output end of the interface logic module, and the output end of the data decoding module is connected with the input end of the configurable register module. The configurable register module is used for configuring the output end of the slave control interface device, and the output end of the configurable register module is used as the output end of the slave control interface device and is connected with the radio frequency front-end device.
The beneficial effects of the invention are as follows: the invention provides a specific scheme of a slave control interface device of a radio frequency front end device based on MIPI RFFE v2.0 protocol, which is particularly suitable for the radio frequency front end device using the interface protocol in industry. The invention is built by all digital logic basic units, thereby being easy to realize the on-chip integration of the slave controller circuit, having small occupied space and being very suitable for controlling various radio frequency front-end devices in the mobile industry.
Further, the interface logic module comprises a dual-mode reset sub-module, a bus clock SCLK input driving sub-module and a bus data SDAT bidirectional driving sub-module. The input end of the dual-mode resetting sub-module is connected with a bus voltage reference/power line VIO and is used for detecting the state of the bus input/output voltage reference/power signal and the state of the power supply of the controller, outputting an RSEN signal to reset the slave control interface device, and respectively placing the slave control interface device in an off state, an on state or an existing state. The input terminal of the bus clock SCLK input driving sub-module is connected to the bus clock signal line SCLK for driving the internal clock line SCLK of the slave interface device. The input end of the bus data SDAT bidirectional driving submodule is connected with the bus data signal line SDAT and is used for selecting the input or output state of the bus data signal line SDAT so as to respectively put the bus data into a high-resistance input or output state.
Further, the dual-mode reset sub-module comprises a power-on detection circuit, a VIO signal state switching detection circuit, a first inverter circuit, a second inverter circuit, an exclusive OR gate circuit and a first AND gate circuit. The power-on detection circuit comprises a field effect tube M1, a resistor R1 and a capacitor C1, wherein the source electrode of the field effect tube M1 is connected with a power supply, the grid electrode and the drain electrode of the field effect tube M are connected with one end of the resistor R1, one end of the capacitor C1, the input end of the first inverter circuit and the second input end of the exclusive-OR gate circuit respectively, the other end of the resistor R1 is connected with the power supply, and the other end of the capacitor C1 is connected with the ground. The output end of the first inverter circuit is connected with the input end of the second inverter circuit, the output end of the second inverter circuit is connected with the first input end of the exclusive-or gate circuit, and the output end of the exclusive-or gate circuit is connected with the first input end of the first AND gate circuit. The VIO signal state switching detection circuit comprises a resistor R2, a resistor R3, a resistor R4, a capacitor C2, a transistor Q1 and a hysteresis comparator, wherein one end of the resistor R2 is connected with one end of the resistor R3 to serve as an input end of the dual-mode resetting submodule, the other end of the resistor R2 is respectively connected with a collector of the transistor Q1, a base of the transistor Q1 and a first input end of the hysteresis comparator, an emitting electrode of the transistor Q1 is connected with ground, the other end of the resistor R3 is respectively connected with one end of the resistor R4, one end of the capacitor C2 and a second input end of the hysteresis comparator, the other end of the resistor R4 and the other end of the capacitor C2 are both connected with ground, and an output end of the hysteresis comparator is connected with a second input end of the first AND gate circuit to serve as an output end of the dual-mode resetting submodule.
The beneficial effects of the above-mentioned further scheme are: the invention adopts the dual-mode reset sub-module, and quickly resets and enables the slave control interface device when the slave control interface device is powered on and the VIO signal state changes, thereby realizing the stable control of the slave control interface device on the radio frequency front-end element and preventing the occurrence of control disorder when the system is powered on and the VIO signal state is switched. Compared with the traditional POR power-on reset module, the dual-mode reset submodule adopted by the invention integrates the power-on reset function and the interface state jump function controlled by the VIO signal, and can better realize the response of the slave control interface device to state switching and system power-on.
Further, the data decoding module comprises a state machine sub-module, an SSC detection sub-module and a data output sub-module. The state machine sub-module is used for controlling the state of the data decoding module, and the state of the control data decoding module comprises a RST interface default state, an ADD1 command frame data accumulation storage state, an ACK1 command frame response state, an ADD2 data frame accumulation storage state, an ACK2 data frame response state, an ACK3 data frame response jump state, an ACK4 read operation response state, an ACK5 read operation end response state and a NUL redundancy operation state. The input end of the SSC detection sub-module is respectively connected with the output end of the bus clock SCLK input driving sub-module and the output end of the bus data SDAT bidirectional driving sub-module, and is used for detecting the starting sequence of the RFFE bus data signal. The input end of the data output sub-module is respectively connected with the output end of the dual-mode reset sub-module and the output end of the bus clock SCLK input driving sub-module, and is used for outputting the data to be read out by the RFFE bus to the bus data signal line SDAT one by one from high to low when the data decoding module is in the ACK4 read operation response state.
The beneficial effects of the above-mentioned further scheme are: the invention adopts the state machine sub-module to control the slave control interface device and perform state switching corresponding to different states of the bus, thereby enhancing the response of the slave control interface device to the MIPI RFFE interface bus state and enhancing the reliability of the slave control interface device.
Further, the SSC detection submodule includes a D trigger D1, a D trigger D2, and a second and gate, the Clk pin of the D trigger D1 and the Clk pin of the D trigger D2 are both connected to the output end of the bus data SDAT bidirectional driving submodule, the ENA pin of the D trigger D1 and the ENA pin of the D trigger D2 are both connected to the MARK signal, the D pin of the D trigger D1 and the D pin of the D trigger D2 are both connected to the output end of the bus clock SCLK input driving submodule, the Q pin of the D trigger D1 is connected to the second input end of the second and gate, the Q pin of the D trigger D2 is connected to the first input end of the second and gate, and the output end of the second and gate serves as the output end of the SSC detection submodule to output SSCDETECT signals.
Further, the data output submodule comprises multiplexers S1 to S6, D triggers D3 to D5, a first multi-input OR gate, a decoder and a second multi-input OR gate; the first input ends of the multiplexers S1-S4 are connected with a power supply and respectively connected with the input end of the decoder, the Q pin of the D trigger D3 and the first input end of the multiplexer S6, the second input ends of the multiplexers S1-S4 are connected with the ground and respectively connected with the input end of the decoder, the Q pin of the D trigger D3 and the first input end of the multiplexer S6, the output ends of the multiplexers S1-S4 are respectively connected with the D pin of the D trigger D3, the output end of the decoder is respectively connected with the input ends of the first multi-input or gate circuit and the first input end of the multiplexer S5, the output end of the multiplexer S5 is connected with the D pin of the D trigger D4, the output ends of the multiplexer S6 are respectively connected with the D pin of the D trigger D5, the Clk pins of the D trigger D3-D5 are respectively connected with the output end of the bus clock K input sub-module, the Reset pins of the D trigger D3-D5 are respectively connected with the second input end of the SCLK, the two-bit clock input SCLK signal is respectively connected with the second input end of the multiplexer S5, and the bit signal of the two-up-clock signal input SCLK is respectively inputted to the two ends of the multiplexer S5.
The beneficial effects of the above-mentioned further scheme are: the invention adopts the data output sub-module to realize the data bidirectional transmission on the MIPI RFFE bus data line SDAT, so that the data can be written into and read out of the slave control interface device, and the flexibility and the reliability of the slave control interface device for the control of a later-stage circuit are increased.
Further, the configurable register module comprises multiplexers S7-S10 and D flip-flops D7-D42, clk pins of the D flip-flops D7-D42 are connected with an internal clock line SCLK of the slave interface device, reset pins of the D flip-flops D7-D42 are connected with RSEN signals, D pins of the D flip-flops D7-D38 are correspondingly connected with output ends of 32 registers in the slave interface device one by one, D pins of the D flip-flops D7-D38 are respectively connected with second input ends of the multiplexers S7-S10, first input ends of the multiplexers S7-S10 are correspondingly connected with output ends of selection registers in the slave interface device, output ends of the multiplexers S7-S10 are correspondingly connected with D pins of the D flip-flops D39-D42 one by one, Q pins of the D flip-flops D39-D42 serve as output ends of the slave interface device, and are connected with a radio frequency front device.
The beneficial effects of the above-mentioned further scheme are: the invention adopts the configurable register module to realize the total output of the control signals of the internal control registers, adopts 4 groups of 8-bit output pins, and outputs 256-bit control signals in the 32 control registers in the slave controller by configuring the internal configurable register module. Compared with the traditional configurable register module, the scheme provided by the invention can realize more control signal output by using fewer output pins, and can flexibly switch the control signals output by the output pins through the MIPI RFFE interface, so that the control signals can be applied to various radio frequency front-end devices with different control requirements.
Drawings
Fig. 1 is a schematic diagram of a prior art mobile device processor directly controlling a rf front-end device.
Fig. 2 is a schematic diagram of a prior art device in which a mobile device processor indirectly controls a radio frequency front end through an FPGA.
FIG. 3 is a schematic diagram of a prior art configurable register structure.
Fig. 4 is a block diagram of a slave control interface device of a radio frequency front end device according to an embodiment of the present invention.
Fig. 5 is a schematic circuit diagram of a dual-mode reset submodule according to an embodiment of the present invention.
Fig. 6 is a schematic state diagram of a state machine submodule according to an embodiment of the present invention.
Fig. 7 is a schematic circuit diagram of an SSC detection submodule and a data output submodule according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a circuit structure of a configurable register module according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of connection and use of a slave control interface device of a radio frequency front end device according to an embodiment of the present invention.
Reference numerals illustrate:
100-interface logic module, 200-data decoding module, 300-configurable register module;
110-dual-mode reset submodule, 120-bus clock SCLK input driving submodule, 130-bus data SDAT bidirectional driving submodule;
111-a first inverter circuit, 112-a second inverter circuit, 113-an exclusive-or not gate circuit, 114-a first and gate circuit, 115-a hysteresis comparator;
a 210-state machine sub-module, a 220-SSC detection sub-module and a 230-data output sub-module;
221-second and-gate, 231-first multiple-input or-gate, 232-decoder, 233-second multiple-input or-gate.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely illustrative of the principles and spirit of the invention and are not intended to limit the scope of the invention.
The embodiment of the invention provides a structure block diagram of a slave control interface device of a radio frequency front end device, as shown in fig. 4, which comprises an interface logic module 100, a data decoding module 200 and a configurable register module 300 which are connected in sequence; the input end of the interface logic module 100 is the input end of the slave control interface device, and is respectively connected with the bus clock signal line SCLK, the bus data signal line SDAT and the bus voltage reference/power line VIO; the data decoding module 200 is configured to decode the received bus data, and has an input end connected to an output end of the interface logic module 100 and an output end connected to an input end of the configurable register module 300; the configurable register module 300 is configured to configure an output terminal of the slave interface device, where the output terminal is used as an output terminal of the slave interface device and connected to the rf front-end device.
The interface logic module 100 includes a dual mode reset sub-module 110, a bus clock SCLK input drive sub-module 120, and a bus data SDAT bidirectional drive sub-module 130. The input end of the dual-mode resetting sub-module 110 is connected to the bus voltage reference/power line VIO, and is used for detecting the state of the bus input/output voltage reference/power signal and the state of the power supply of the controller, and outputting the RSEN signal to reset the slave interface device, and placing the slave interface device in an off state, an on state or an active state respectively. The input end of the bus clock SCLK input driving sub-module 120 is connected with the bus clock signal line SCLK for driving the internal clock line SCLK of the slave interface device; the input terminal of the bus data SDAT bidirectional driving sub-module 130 is connected to the bus data signal line SDAT, and is used for selecting the input or output state of the bus data signal line SDAT, so as to place the bus data into a high-resistance input or output state, respectively.
As shown in fig. 5, the dual mode reset sub-module 110 includes a power-on detection circuit, a VIO signal state switching detection circuit, a first inverter circuit 111, a second inverter circuit 112, an exclusive or gate 113, and a first and gate 114. The first inverter circuit 111, the second inverter circuit 112, and the exclusive or gate circuit 113 constitute a power-on reset pulse generation circuit that generates a pulse signal when the system is powered on. The power-on detection circuit comprises a field effect transistor M1, a resistor R1 and a capacitor C1, wherein a source electrode (i.e. end 1 in the figure) of the field effect transistor M1 is connected with a power supply, a grid electrode (i.e. end 2 in the figure) and a drain electrode (i.e. end 3 in the figure) of the field effect transistor M are respectively connected with one end (i.e. end 2 in the figure) of the resistor R1, one end (i.e. end 1 in the figure) of the capacitor C1, an input end (i.e. end 1 in the figure) of the first inverter circuit 111 and a second input end (i.e. end 2 in the figure) of the exclusive-OR gate circuit 113, the other end (i.e. end 1 in the figure) of the resistor R1 is connected with the power supply, and the other end (i.e. end 2 in the figure) of the capacitor C1 is connected with ground. The output terminal (i.e., terminal 2 in the figure) of the first inverter circuit 111 is connected to the input terminal (i.e., terminal 1 in the figure) of the second inverter circuit 112, the output terminal (i.e., terminal 2 in the figure) of the second inverter circuit 112 is connected to the first input terminal (i.e., terminal 1 in the figure) of the exclusive-or gate 113, and the output terminal (i.e., terminal 3 in the figure) of the exclusive-or gate 113 is connected to the first input terminal (i.e., terminal 1 in the figure) of the first and circuit 114. The VIO signal state switching detection circuit includes a resistor R2, a resistor R3, a resistor R4, a capacitor C2, a transistor Q1, and a hysteresis comparator 115, where one end (i.e., end 1 in the figure) of the resistor R2 is connected to one end (i.e., end 1 in the figure) of the resistor R3 as an input end of the dual-mode resetting submodule 110, the other end (i.e., end 2 in the figure) of the resistor R2 is connected to a collector (i.e., end 1 in the figure) of the transistor Q1, a base (i.e., end 2 in the figure) of the transistor Q1, and a first input end (i.e., end 1 in the figure) of the hysteresis comparator 115, an emitter (i.e., end 3 in the figure) of the transistor Q1 is connected to ground, and the other end (i.e., end 2 in the figure) of the resistor R3 is connected to one end (i.e., end 1 in the figure) of the resistor R4, one end (i.e., end 1 in the figure) of the capacitor C2, and a second input end (i.e., end 2 in the figure) of the hysteresis comparator 115 are respectively connected to a collector (i.e., end 2 in the figure) of the resistor 1, respectively, the other end of the resistor R4 and the other end (i.e., end 2 in the end 2 and the first input end 2 is connected to the first input end of the hysteresis comparator 115 and the first end is connected to the first input end 3 and the first end is respectively.
The first and circuit 114 performs an and operation on the output signals of the exclusive nor circuit 113 and the hysteresis comparator 115, and outputs a system enable reset signal RSEN. The signal RSEN is used as a reset of the slave interface means, enabling and jumping between the off state, the on state and the active state. The slave interface means are in the active state when the signal RSEN is at a high level, in the off state when the signal RSEN is at a low level, and in the on state when a negative going pulse signal appears on the signal RSEN.
In the embodiment of the present invention, the bus clock SCLK input driving sub-module 120 and the bus data SDAT bidirectional driving sub-module 130 may be implemented by using a data buffer structure commonly used in the art, which is not described herein.
The data decoding module 200 includes a state machine sub-module 210, an SSC detection sub-module 220, and a data output sub-module 230. The state machine sub-module 210 is configured to control the state of the data decoding module 200, where the state of the data decoding module 200 includes a RST interface default state, an ADD1 command frame data accumulation storage state, an ACK1 command frame response state, an ADD2 data frame accumulation storage state, an ACK2 data frame response state, an ACK3 data frame response skip state, an ACK4 read operation response state, an ACK5 read operation end response state, and a NUL redundancy operation state.
As shown in fig. 6, the state machine sub-module 210 selects to enter the following states according to the states of the MIPI bus VIO, SCLK, and SDAT, with each circle in fig. 6 corresponding to a separate state and being designated by a capital letter, corresponding to the 4-bit binary code shown below the capital letter. The following is a description of these states:
(1) RST: interface default state. When the output signal RSEN of the dual mode reset sub-module 110 changes from high to low, the state machine sub-module 210 enters this state to perform a reset operation on the slave interface device. In this state, the slave interface device automatically loads the internal registers with corresponding initial values, and sets each output pin of the slave interface device to a default value. After the above operation is completed, the state machine sub-module 210 automatically points the state to ADD1, entering state ADD1 upon the arrival of the next clock falling edge of the SCLK bus clock.
(2) ADD1: command frame data accumulates storage states. After the automatic reset operation is performed on the slave interface device, the state machine sub-module 210 automatically enters the state ADD1. In this state, the state machine sub-module 210 controls the slave interface device to sample SDAT bus data at the arrival of each clock falling edge of the SCLK bus clock, and sequentially stores the sampled data from high to low in the command frame register inside the slave interface device. After sampling the 12 th SDAT bus data, the state machine sub-module 210 clears the count accumulator inside the slave interface device, automatically points the state to ACK1, and enters the state ACK1 when the next clock falling edge of the SCLK bus clock arrives.
(3) ACK1: the command frame responds to the status. After the state machine sub-module 210 controls the slave interface device to sample the command frame on the 12-bit bus data signal line SDAT, the state machine sub-module 210 automatically enters the state ACK1. In this state, the state machine sub-module 210 controls the slave interface device to sample the SDAT bus data when the SCLK clock bus falling edge arrives, and at the same time compares it with the odd parity result of the 12-bit SDAT data bus command frame sampled in the state ADD 1. If the odd parity result of the command frame and the sampled SDAT bus data are not identical, the state machine submodule 210 directs the state to NUL. If the odd check result of the command frame is the same as the sampled SDAT bus data, the state machine sub-module 210 automatically controls the Slave interface device to continue to determine the 4-bit chip Address data segment Slave Address (SA) in the 12-bit SDAT data bus command frame. If the 4-bit chip address data field in the 12-bit SDAT data bus command frame is not identical to the 4-bit chip address data built into the slave interface device, the state machine sub-module 210 directs the state to NUL. If the 4-bit chip address data segment in the 12-bit SDAT data bus command frame is the same as the 4-bit chip address data built in the slave interface device, the state machine sub-module 210 automatically controls the slave interface device to continue to determine the 3-bit read/write command segment in the 12-bit SDAT data bus command frame. If the 3-bit read Write command segment in the 12-bit SDAT data bus command frame is a Write command (Write), the state machine sub-module 210 automatically points the state to ADD2. If the 3-bit Read-write command segment in the 12-bit SDAT data bus command frame is a Read command, the state machine sub-module 210 automatically directs the state to ACK4. If the 3-bit read-write command segment in the 12-bit SDAT data bus command frame is neither a write command nor a read command, the state machine sub-module 210 directs the state to NUL.
(4) ADD2: the data frames accumulate the memory state. After the state machine sub-module 210 determines that the 3-bit read-write command segment in the 12-bit SDAT data bus command frame is a write command, the state machine sub-module 210 automatically enters state ADD2. In this state, the state machine sub-module 210 controls the slave interface device to sample the SDAT bus data at the arrival of each clock falling edge of the SCLK bus clock, and sequentially stores the sampled data from high to low in the data frame register inside the slave controller. After sampling the 8 th SDAT bus data, the state machine sub-module 210 clears the count accumulator inside the slave interface device, automatically points the state to ACK2, and enters the state ACK2 when the next clock falling edge of the SCLK bus clock arrives.
(5) ACK2: the data frame responds to the status. After the state machine sub-module 210 controls the slave interface device to sample the data frame on the 8-bit SDAT data bus, the state machine sub-module 210 automatically enters state ACK2. In this state, the state machine sub-module 210 controls the slave interface device to sample the SDAT bus data when the SCLK clock bus falling edge arrives, and at the same time compares it with the odd parity result of the 8-bit SDAT data bus data frame sampled in the state ADD2. If the odd parity result of the data frame is not the same as the sampled SDAT bus data, the state machine sub-module 210 directs the state to ACK3 directly. If the odd parity result of the data frame is the same as the sampled SDAT bus data, the state machine sub-module 210 determines the value of the 5-bit register Address data segment Address (A) in the 12-bit SDAT data bus command frame, and determines which register from register 0, register 1 to register 30, register 31 is to be written. If the register to be written is the register 28, bit 0 of the data frame register is assigned to the data output flag bit, and the value of the data frame register is assigned to the register 28. If the register to be written is the other of the above-mentioned registers, the value of the data frame register is directly assigned to the corresponding register. Bits 5, 6, 7 of register 28 constitute a select register SEL [2:0], in which state machine submodule 210 is in a state, configurable register module 300 configures data on the slave output ports according to select register SEL [2:0 ]. After the state machine sub-module 210 controls the slave interface device to complete the register write operation described above, the state machine sub-module 210 directs the state to ACK3.
(6) ACK3: the data frame is responsive to the skip state. In this state, state machine submodule 210 points state to ADD1 and enters exit state ACK3 upon the arrival of the next SCLK bus clock falling edge, entering state ADD1.
(7) ACK4: the read operation responds to the status. After the state machine sub-module 210 determines that the 3-bit read-write command segment in the 12-bit SDAT data bus command frame is a read command, the state machine sub-module 210 automatically enters state ACK4. In this state, the state machine sub-module 210 sets the read command flag bit and the data bus status flag bit first, and then the state machine sub-module 210 judges the value of the 5-bit register Address data field Address (a) in the 12-bit SDAT data bus command frame, and judges which register of the registers 0, 1 to 30, 31 the data is to be read. After the state machine sub-module 210 determines that the register to be read out is complete, the data in the corresponding register is loaded into the data frame register, and then the state machine sub-module 210 directs the state to ACK5.
(8) ACK5: the read operation ends detecting the state. After the state machine sub-module 210 loads the corresponding register data to be read into the data frame register, the state machine sub-module 210 automatically enters state ACK5. In this state, the state machine sub-module 210 detects the value of the read command end flag bit upon arrival of each clock falling edge of the SCLK bus clock. If the value of the read command end flag bit is detected to be 1, the read command flag bit and the data bus state flag bit are set to zero and state machine sub-module 210 state is directed to ADD1. If the value of the read command end flag bit is detected to be 0, the state machine sub-module 210 continues to direct state to ACK5 and continues to detect the value of the read command end flag bit upon the arrival of the next SCLK bus clock falling edge until the value bit 1 of the read command end flag bit is detected.
(9) NUL: redundant operating states. In this state, the state machine sub-module 210 detects and counts each clock falling edge of the SCLK bus clock. When the state machine sub-module 210 counts to the 9 th clock falling edge, the state machine sub-module 210 clears the count accumulator inside the slave interface device and automatically directs the state to ACK3.
The input end of the SSC detection sub-module 220 is connected to the output end of the bus clock SCLK input driving sub-module 120 and the output end of the bus data SDAT bidirectional driving sub-module 130, respectively, for detecting the start sequence of the RFFE bus data signal, and when the start sequence of the RFFE bus data signal is detected, the state machine sub-module 210 jumps to the ADD1 command frame data accumulation storage state to start receiving data on the RFFE bus. The input end of the data output sub-module 230 is respectively connected to the output end of the dual-mode reset sub-module 110 and the output end of the bus clock SCLK input driving sub-module 120, and is used for outputting the data to be read out by the RFFE bus onto the bus data signal line SDAT from high order to low order one by one when the data decoding module 200 is in the ACK4 read operation response state.
As shown in fig. 7, the SSC detection sub-module 220 includes a D flip-flop D1, a D flip-flop D2, and a second and gate 221, where the Clk pin of the D flip-flop D1 and the Clk pin of the D flip-flop D2 are connected to the output terminal of the bus data SDAT bidirectional driving sub-module 130, the ENA pin of the D flip-flop D1 and the ENA pin of the D flip-flop D2 are connected to the MARK signal, the D pin of the D flip-flop D1 and the D pin of the D flip-flop D2 are connected to the output terminal of the bus clock SCLK input driving sub-module 120, the Q pin of the D flip-flop D1 is connected to the second input terminal (i.e., 2 terminal in the figure) of the second and gate 221, and the Q pin of the D flip-flop D2 is connected to the first input terminal (i.e., 1 terminal in the figure) of the second and gate 221, and the output terminal (i.e., 3 terminal in the figure) of the second and gate 221 serves as the output terminal of the SSC detection sub-module 220, and outputs SSCDETECT signal.
In the SSC detection sub-module 220, the D flip-flop D1 and the D flip-flop D2 store and output the level value on the bus clock signal line SCLK at that time when the rising edge and the falling edge of the bus data signal line SDAT are detected, respectively, and the output signals of the D flip-flop D1 and the D flip-flop D2 are logically anded by the second and gate 221 to obtain an output signal SSCDETECT. When the SSC detection sub-module 220 detects an SSC sequence start condition, the output signal SSCDETECT is set to 1, otherwise the output signal SSCDETECT remains at 0. The output signal SSCDETECT is used by the state machine sub-module 210 to detect whether the slave interface device receives the SSC start sequence in the ADD1 command frame data accumulation state, if the output signal SSCDETECT is 1, the slave interface device starts receiving command frame data in the state ADD1, and if the output signal SSCDETECT is 0, the slave interface device remains inactive in the state ADD 1.
As shown in fig. 7, the data output sub-module 230 includes multiplexers S1 to S6, D flip-flops D3 to D5, a first multi-input or gate 231, a decoder 232, and a second multi-input or gate 233. The first input terminals (i.e., terminal 1 in the figure) of the multiplexers S1-S4 are all connected to a power supply, and are respectively connected to the input terminal of the decoder 232, the Q pin of the D flip-flop D3, and the first input terminal (i.e., terminal 1 in the figure) of the multiplexer S6, the second input terminals (i.e., terminal 2 in the figure) of the multiplexers S1-S4 are all connected to ground, and are respectively connected to the input terminal of the decoder 232, the Q pin of the D flip-flop D3 and the first input terminal (i.e., terminal 1 in the figure) of the multiplexer S6, the output terminals (i.e., terminals 3 in the figure) of the multiplexers S1-S4 are all connected to the D pin of the D flip-flop D3, the output terminals of the decoder 232 are respectively connected to the respective input terminals of the first multiple-input or gate 231 and the first input terminal (i.e., terminal 1 in the figure) of the multiplexer S5, the output terminal (i.e., terminal 3 in the figure) of the multiplexer S5 is connected to the D pin of the D flip-flop D4, the output terminal (i.e., terminal 3 in the figure) of the multiplexer S6 is connected to the D pin of the D flip-flop D5, the Clk pins of the D flip-flops D3-D5 are all connected to the output terminal of the dual-mode Reset sub-module 110, the Q pin of the D flip-flop D4 is connected to the second input terminal (i.e., terminal 2 in the figure) of the multiplexer S5, and outputs READFIN signals, the Q pin of the D flip-flop D5 is connected with the eight-bit data signal DATAOUT [7:0] input by the rising edge of the SCLK clock, the second input terminal (i.e., terminal 2 in the figure) of the multiplexer S6, and the respective input and output terminals of the second multi-input OR gate 233, respectively, and outputs SDATOUT signals.
In the data output sub-block 230, the multiplexers S1 to S4 and the D flip-flop D3 constitute a counter that counts the clock rising edge on the clock bus clock signal line SCLK, and the eight-bit data to be output is taken out to the input terminal of the multiplexer S6 at the immediately preceding SCLK clock rising edge of the data to be output by the bus data signal line SDAT. The multiplexers S6 and D flip-flop D5 output the input eight-bit data DATAOUT [7:0] to the SDATOUT output sequentially from the most significant bit to the least significant bit on a subsequent SCLK clock rising edge. The multiplexer S5 and the D flip-flop D4 form a counter to count the rising clock edge on the clock bus SCLK, and after the data output sub-module 230 outputs the lowest bit of the eight bits of data DATAOUT [7:0], the output signal READFIN of the data output sub-module 230 is set to 1, indicating that the read operation data output state has ended, and the state machine sub-module 210 will automatically jump to the ACK5 read operation end detection state.
As shown in fig. 8, the configurable register module 300 includes multiplexers S7 to S10 and D flip-flops D7 to D42, wherein Clk pins of the D flip-flops D7 to D42 are all connected to an internal clock line SCLK of the slave interface device, reset pins of the D flip-flops D7 to D42 are all connected to RSEN signals, D pins of the D flip-flops D7 to D38 are connected to output ends of 32 registers in the slave interface device in one-to-one correspondence, D pins of the D flip-flops D7 to D38 are all connected to second input ends (i.e., 2 ends in the drawing) of the multiplexers S7 to S10, first input ends (i.e., 1 end in the drawing) of the multiplexers S7 to S10 are all connected to output ends of the selection registers in the slave interface device, output ends (i.e., 3 ends in the drawing) of the multiplexers S7 to S10 are connected to the D pins of the D flip-flops D39 to D42 in one-to-one correspondence, Q pins of the D flip-flops D39 to D42 are connected to the output ends of the slave interface device as output ends of the slave interface device, and the rf front device.
In configurable register module 300, D flip-flops D7-D38 are used to store and buffer internal register data from REGDATA0[7:0] to REGDATA31[7:0 ]. REGDATA0[7:0], REGDATA1[7:0], …, REGDATA30[7:0], REGDATA31[7:0] are outputs of slave interface device internal registers 0, registers 1, …, registers 30, registers 31. The multiplexers S7-S10 select 4 sets of data from REGDATA0[7:0] to REGDATA31[7:0] according to the configuration value of the selection register SEL [2:0], and output the 4 sets of 8-bit data to the output pins OUT0[7:0], OUT1[7:0], OUT2[7:0] and OUT3[7:0] through the output registers D39-D42. In this way, it is possible to output data of the internal 32-group 8-bit registers with 4-group 8-bit output pins, that is, to output control signals of 256 internal registers only through 32 output pins. The output data on the 4 output pins are determined by the value of the selection register SEL [2:0], and under the condition that the slave interface device is in the data frame response state ACK2, the multiplexers S7-S10 send 4 sets of register data in the corresponding REGDATA0[7:0] to REGDATA31[7:0] to the output ends OUT0[7:0], OUT1[7:0], OUT2[7:0] and OUT3[7:0] through the output registers D39-D42 according to the value of SEL [2:0 ].
The slave control interface device of the radio frequency front end device provided by the embodiment of the invention can be integrated on a whole chip, and is based on the MIPI RFFE v2.0 protocol, as shown in fig. 9, the slave control interface device is built by adopting a digital logic unit and a basic circuit element, so that the on-chip integration of the slave control circuit is easy to realize, and the slave control can be integrated into the radio frequency front end element chip. Flexible control of the rf front-end components can be achieved only through the three signal lines VIO, SCLK, SDAT of the mipirff interface. Therefore, the invention can be integrated in a chip, the output pins of the used processor are fewer, the area of the printed circuit board occupied by the control signals is smaller, and the invention does not need to use additional board-level components. Therefore, the invention has lower cost and smaller occupied equipment space, is beneficial to the miniaturization and low-cost design of the mobile equipment, and is very suitable for controlling various radio frequency front-end devices in the mobile industry.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (4)
1. The radio frequency front-end device slave control interface device is characterized by comprising an interface logic module (100), a data decoding module (200) and a configurable register module (300) which are connected in sequence;
the input end of the interface logic module (100) is the input end of the slave control interface device and is respectively connected with a bus clock signal line SCLK, a bus data signal line SDAT and a bus voltage reference/power line VIO;
the data decoding module (200) is used for decoding the received bus data, the input end of the data decoding module is connected with the output end of the interface logic module (100), and the output end of the data decoding module is connected with the input end of the configurable register module (300);
the configurable register module (300) is used for configuring the output end of the slave control interface device, and the output end of the configurable register module is used as the output end of the slave control interface device and is connected with a radio frequency front-end device;
the interface logic module (100) comprises a dual-mode reset sub-module (110), a bus clock SCLK input driving sub-module (120) and a bus data SDAT bidirectional driving sub-module (130);
the input end of the dual-mode resetting sub-module (110) is connected with a bus voltage reference/power line (VIO) and is used for detecting the state of a bus input/output voltage reference/power signal and the state of a controller power supply, outputting an RSEN signal to reset the slave control interface device and respectively placing the slave control interface device in an off state, an on state or an existing state;
The input end of the bus clock SCLK input driving sub-module (120) is connected with a bus clock signal line SCLK and used for driving an internal clock line SCLK of the slave control interface device;
the input end of the bus data SDAT bidirectional driving submodule (130) is connected with the bus data signal line SDAT and is used for selecting the input or output state of the bus data signal line SDAT so as to respectively put the bus data into a high-resistance input or output state;
the data decoding module (200) comprises a state machine sub-module (210), an SSC detection sub-module (220) and a data output sub-module (230);
the state machine sub-module (210) is configured to control a state of the data decoding module (200), where the state of the control data decoding module (200) includes a RST interface default state, an ADD1 command frame data accumulation storage state, an ACK1 command frame response state, an ADD2 data frame accumulation storage state, an ACK2 data frame response state, an ACK3 data frame response skip state, an ACK4 read operation response state, an ACK5 read operation end response state, and a NUL redundancy operation state;
the input end of the SSC detection sub-module (220) is respectively connected with the output end of the bus clock SCLK input driving sub-module (120) and the output end of the bus data SDAT bidirectional driving sub-module (130) and is used for detecting the starting sequence of the RFFE bus data signal;
The input end of the data output sub-module (230) is respectively connected with the output end of the dual-mode reset sub-module (110) and the output end of the bus clock SCLK input driving sub-module (120) and is used for outputting data to be read out by the RFFE bus onto the bus data signal line SDAT one by one from high to low when the data decoding module (200) is in an ACK4 read operation response state;
the configurable register module (300) comprises multiplexers S7-S10 and D flip-flops D7-D42, wherein Clk pins of the D flip-flops D7-D42 are connected with an internal clock line SCLK of the slave interface device, reset pins of the D flip-flops D7-D42 are connected with RSEN signals, D pins of the D flip-flops D7-D38 are connected with output ends of 32 registers in the slave interface device in a one-to-one correspondence manner, D pins of the D flip-flops D7-D38 are connected with second input ends of the multiplexers S7-S10 respectively, first input ends of the multiplexers S7-S10 are connected with output ends of a selection register in the slave interface device, output ends of the multiplexers S7-S10 are connected with D pins of the D flip-flops D39-D42 in a one-to-one correspondence manner, and Q of the D flip-flops D39-D42 serve as output ends of the slave interface device and are connected with a radio frequency front end device.
2. The radio frequency front end device slave interface apparatus according to claim 1, wherein the dual mode reset sub-module (110) comprises a power-on detection circuit, a VIO signal state switching detection circuit, a first inverter circuit (111), a second inverter circuit (112), an exclusive-or gate circuit (113), and a first and gate circuit (114);
the power-on detection circuit comprises a field effect tube M1, a resistor R1 and a capacitor C1, wherein the source electrode of the field effect tube M1 is connected with a power supply, the grid electrode and the drain electrode of the field effect tube M1 are connected with one end of the resistor R1, one end of the capacitor C1, the input end of a first inverter circuit (111) and the second input end of an exclusive OR gate circuit (113) respectively, the other end of the resistor R1 is connected with the power supply, and the other end of the capacitor C1 is connected with the ground;
the output end of the first inverter circuit (111) is connected with the input end of the second inverter circuit (112), the output end of the second inverter circuit (112) is connected with the first input end of the exclusive-or NOT circuit (113), and the output end of the exclusive-or NOT circuit (113) is connected with the first input end of the first AND circuit (114);
the VIO signal state switching detection circuit comprises a resistor R2, a resistor R3, a resistor R4, a capacitor C2, a transistor Q1 and a hysteresis comparator (115), wherein one end of the resistor R2 is connected with one end of the resistor R3 to serve as an input end of the dual-mode resetting sub-module (110), the other end of the resistor R2 is respectively connected with a collector of the transistor Q1, a base of the transistor Q1 and a first input end of the hysteresis comparator (115), an emitter of the transistor Q1 is connected with ground, the other end of the resistor R3 is respectively connected with one end of the resistor R4, one end of the capacitor C2 and a second input end of the hysteresis comparator (115), the other end of the resistor R4 and the other end of the capacitor C2 are both connected with ground, and an output end of the hysteresis comparator (115) is connected with a second input end of the first AND gate circuit (114), and an output end of the first AND gate circuit (114) serves as an output end of the dual-mode resetting sub-module (110).
3. The radio frequency front end device slave interface apparatus according to claim 1, wherein the SSC detection sub-module (220) includes a D flip-flop D1, a D flip-flop D2, and a second and gate (221), the Clk pin of the D flip-flop D1 and the Clk pin of the D flip-flop D2 are both connected to the output of the bus data SDAT bidirectional driving sub-module (130), the ENA pin of the D flip-flop D1 and the ENA pin of the D flip-flop D2 are both connected to the MARK signal, the D pin of the D flip-flop D1 and the D pin of the D flip-flop D2 are both connected to the output of the bus clock SCLK input driving sub-module (120), the Q pin of the D flip-flop D1 is connected to the second input of the second and gate (221), and the output of the second and gate (221) is the output of the SSC detection sub-module (SSCDETECT).
4. The radio frequency front end device slave interface apparatus according to claim 1, wherein the data output sub-module (230) comprises multiplexers S1 to S6, D flip-flops D3 to D5, a first multi-input or gate (231), a decoder (232) and a second multi-input or gate (233); the first input ends of the multiplexers S1-S4 are connected with a power supply and are respectively connected with the input end of the decoder (232), the Q pin of the D trigger D3 and the first input end of the multiplexer S6, the second input ends of the multiplexers S1-S4 are respectively connected with the ground and are respectively connected with the input end of the decoder (232), the Q pin of the D trigger D3 and the first input end of the multiplexer S6, the output ends of the multiplexers S1-S4 are respectively connected with the D pin of the D trigger D3, the output end of the decoder (232) is respectively connected with the input ends of the first multi-input OR gate (231) and the first input end of the multiplexer S5, the output end of the multiplexer S5 is connected with the D pin of the D trigger D4, the output ends of the multiplexer S6 are respectively connected with the D pin of the D trigger D5, the Clk pins of the D trigger D3-D5 are respectively connected with the D pin of the bus SCLK module, the two input ends of the multiplexer S5 are respectively connected with the two input ends of the two-stage flip-flop S5, the two-stage clock signal input ends of the multiplexer S110 are respectively, and the two stage SCLID trigger D5 are respectively connected with the input ends of the two stage SCLID 5, and the two stage SCLID trigger S110 are respectively.
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| CN110518897B (en) * | 2019-08-26 | 2023-04-18 | 紫光展讯通信(惠州)有限公司 | Method for removing reset and set pins of D flip-flop, D flip-flop and circuit |
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