CN108446420A - A kind of smart television main control chip plate layout methods - Google Patents
A kind of smart television main control chip plate layout methods Download PDFInfo
- Publication number
- CN108446420A CN108446420A CN201810051631.4A CN201810051631A CN108446420A CN 108446420 A CN108446420 A CN 108446420A CN 201810051631 A CN201810051631 A CN 201810051631A CN 108446420 A CN108446420 A CN 108446420A
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- CN
- China
- Prior art keywords
- main control
- control chip
- smart television
- chip plate
- television main
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The invention discloses a kind of smart television main control chip plate layout methods comprising following steps：Step S1 prepares component encapsulation library, draws the circuit diagram of smart television main control chip plate and generates net list；Step S2 creates PCB files, and net list is imported PCB files；The layer structure of pcb board is set as at least 4 layers by step S3；Step S4 is arranged wiring rule, then is laid out and connects up.The present invention can be efficiently applied in portable product, and eliminate the damping resistance of address control data line, and then improve master control borad working efficiency and product yield.
Description
Technical field
The present invention relates to smart television main control chip plate more particularly to a kind of smart television main control chip plate sides layout
Method.
Background technology
In the prior art, Mstar TVs android intellective schemes MSD6A628VX is in the extensive use of smart television market.
The TV smart television schemes of Mstar are widely used in the Intelligent Business in addition to TV and show market, including picture by some well-known manufacturers
The markets such as intelligence projection, advertisement machine, label, electronic whiteboard, wherein MSD6A628VX are exactly one and promote mainly the aobvious platform of quotient, the platform
It it is more than 300,000 sets intelligently projection market to the end of the year 2016 sell nest plate on the market.MSD6A628VX intelligence projection platforms it is hard
Part design has many places innovation relative to hardware design disclosed in the markets TV, wherein in MSD6A628VX and plug-in 2 DDR3 collection
At innovative design has been made on the circuit G- Design and layout frameworks of chip, particular technique point is described as follows：Mstar
The markets MSD6A628VX series TV disclose in hardware resources, and PCB Layout are using 2 laminates, integrated main control chip MSD6A628VX
Between DDR3 layout distance farther out, and this principle diagram design using element it is more, do not have reduce Layout plate faces
Long-pending precondition.And as in such as limitation of the intelligence projection market due to the device space of portable mobile product, it is desirable that have to
The layout distances integrated between main control chip MSD6A628VX and DDR3 are reduced, simultaneously because DLP projection TI driving chips
It is required that plate layer must be modified to 6 laminates, it is therefore necessary to do innovative design to existing technical data, change principle diagram design
The plate layer of principle and method, the plate suqare for reducing Layout, change PCB files.If directly being set using hardware disclosed in the markets TV
If meter, it can be had the following disadvantages when such as intelligence projection market is applied in portable mobile product：
Firstly, since MSD6A628VX main control chip plate layers are 2 layers, with 6 laminates of TI driving chips on not, therefore only
2 blocks of independent plates can be made to dock, it is not possible to be designed directly to one piece of whole plate.
Secondly as being integrated between main control chip MSD6A628VX and DDR3 in hardware design disclosed in the markets TV
Layout distance farther out, the have no idea mold small for meeting customer requirement and portable aesthetic.
In addition, the address control of DDR and data line are connected to a large amount of damping resistance in routine DDRPCB designs, easily cause
First-pass yield declines when volume production, and yield reduces, and produces and processes cost increase.
Invention content
The technical problem to be solved in the present invention is, in view of the deficiencies of the prior art, provides a kind of can be efficiently applied to just
It takes in formula product, and eliminates the damping resistance of address control data line, and then raising master control borad working efficiency and product are good
The smart television main control chip plate layout methods of rate.
In order to solve the above technical problems, the present invention adopts the following technical scheme that.
A kind of smart television main control chip plate layout methods comprising following steps：Step S1 prepares component encapsulation
Library draws the circuit diagram of smart television main control chip plate and generates net list；Step S2, creates PCB files, and by network
Table imports PCB files；The layer structure of pcb board is set as at least 4 layers by step S3；Step S4, setting wiring rule, then into
Row place and route.
Preferably, in the step S3, the size of pcb board is less than or equal to 44.7mm*43.6mm.
Preferably, in the step S4, setting wiring rule includes setting line width and line-spacing.
Preferably, the main control chip plate is the master control borad for including MSD6A628VX chips and DDR3 chips.
Preferably, in the circuit diagram, whole damping build-out resistors in DDR signal are removed.
Smart television main control chip plate layout methods disclosed by the invention, advantageous effect compared to existing technologies
It is, the layout areas between integrated main control chip MSD6A628VX and DDR3 are subtracted by the 66.6x65.2mm of former conventional design
Small is 44.7x43.6mm so that master control borad can be effectively applied in the design application of portable product.In addition, integrated master control
Principle diagram design between chip MSD6A628VX and DDR3 eliminates the damping resistance of address control data line, in portable production
Processing and BOM costs are reduced in product, are improved efficiency, are improved yield.
Description of the drawings
Fig. 1 is the flow chart of smart television main control chip plate layout methods in the preferred embodiment of the present invention.
Fig. 2 is the PCB design figure of main control chip plate in the prior art.
Fig. 3 is the PCB design figure one of main control chip plate of the present invention.
Fig. 4 is the PCB design figure two of main control chip plate of the present invention.
Specific implementation mode
The present invention is described in more detail with reference to the accompanying drawings and examples.
The invention discloses a kind of smart television main control chip plate layout methods, please refer to Fig. 1 comprising following step
Suddenly：
Step S1 prepares component encapsulation library, draws the circuit diagram of smart television main control chip plate and generates net list；
Step S2 creates PCB files, and net list is imported PCB files；
The layer structure of pcb board is set as at least 4 layers by step S3；
Step S4 is arranged wiring rule, then is laid out and connects up.
Further, in the step S3, the size of pcb board is less than or equal to 44.7mm*43.6mm.In the present embodiment,
In the step S4, setting wiring rule includes setting line width and line-spacing.
In a preferred embodiment, the main control chip plate is the master control for including MSD6A628VX chips and DDR3 chips
Plate.
As a preferred method, in the circuit diagram, whole damping build-out resistors in DDR signal are removed.
In conjunction with shown in Fig. 2, Fig. 3 and Fig. 4, in smart television main control chip plate layout methods disclosed by the invention, integrate
Layout areas between main control chip MSD6A628VX and DDR3 are reduced to by the 66.6x65.2mm of former conventional design
44.7x43.6mm so that master control borad can be effectively applied in the design application of portable product.In addition, integrated main control chip
Principle diagram design between MSD6A628VX and DDR3 eliminates the damping resistance of address control data line, in portable product
Processing and BOM costs are reduced, efficiency is improved, improves yield.
The above is preferred embodiments of the present invention, is not intended to restrict the invention, all technology models in the present invention
Interior done modification, equivalent replacement or improvement etc. are enclosed, should be included in the range of of the invention protect.
Claims (5)
1. a kind of smart television main control chip plate layout methods, which is characterized in that include the following steps：
Step S1 prepares component encapsulation library, draws the circuit diagram of smart television main control chip plate and generates net list；
Step S2 creates PCB files, and net list is imported PCB files；
The layer structure of pcb board is set as at least 4 layers by step S3；
Step S4 is arranged wiring rule, then is laid out and connects up.
2. smart television main control chip plate layout methods as described in claim 1, which is characterized in that in the step S3,
The size of pcb board is less than or equal to 44.7mm*43.6mm.
3. smart television main control chip plate layout methods as described in claim 1, which is characterized in that in the step S4,
It includes setting line width and line-spacing that wiring rule, which is arranged,.
4. smart television main control chip plate layout methods as described in claim 1, which is characterized in that the main control chip plate
It is the master control borad for including MSD6A628VX chips and DDR3 chips.
5. smart television main control chip plate layout methods as claimed in claim 4, which is characterized in that the circuit diagram
In, remove whole damping build-out resistors in DDR signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711170011 | 2017-11-17 | ||
| CN2017111700114 | 2017-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108446420A true CN108446420A (en) | 2018-08-24 |
Family
ID=63191055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810051631.4A Pending CN108446420A (en) | 2017-11-17 | 2018-01-19 | A kind of smart television main control chip plate layout methods |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108446420A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060212624A1 (en) * | 2005-03-21 | 2006-09-21 | Pantech Co., Ltd. | Data transceiver using LVDS and a portable terminal employing the same and method therefor |
| CN101840454A (en) * | 2010-04-26 | 2010-09-22 | 南京熊猫数字化技术开发有限公司 | Modularizing design method for circuit system |
| US20130321438A1 (en) * | 2012-05-25 | 2013-12-05 | Huawei Technologies Co., Ltd. | Display control method and system and display device |
| CN105446922A (en) * | 2014-08-11 | 2016-03-30 | 炬力集成电路设计有限公司 | PCB board and device compatible with DDRs of different bit widths |
| CN106982364A (en) * | 2017-03-16 | 2017-07-25 | 天津通信广播集团有限公司 | Laser television ray machine control system based on AML T866SOC chips |
-
2018
- 2018-01-19 CN CN201810051631.4A patent/CN108446420A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060212624A1 (en) * | 2005-03-21 | 2006-09-21 | Pantech Co., Ltd. | Data transceiver using LVDS and a portable terminal employing the same and method therefor |
| CN101840454A (en) * | 2010-04-26 | 2010-09-22 | 南京熊猫数字化技术开发有限公司 | Modularizing design method for circuit system |
| US20130321438A1 (en) * | 2012-05-25 | 2013-12-05 | Huawei Technologies Co., Ltd. | Display control method and system and display device |
| CN105446922A (en) * | 2014-08-11 | 2016-03-30 | 炬力集成电路设计有限公司 | PCB board and device compatible with DDRs of different bit widths |
| CN106982364A (en) * | 2017-03-16 | 2017-07-25 | 天津通信广播集团有限公司 | Laser television ray machine control system based on AML T866SOC chips |
Non-Patent Citations (4)
| Title |
|---|
| CORMANS: ""DDR的PCB设计"", 《HTTPS://BLOG.CSDN.NET/WANGFUZI35/ARTICLE/DETAILS/21389521》 * |
| NANSEN CHEN等: ""Investigation of Low Cost Consumer Electronic System Using 1066-Mb/s DDR2 Interface Design"", 《2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY》 * |
| 于晨光: ""基于AVS标准的移动数字电视终端设计"", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 吴川斌: ""DDR布线规则与过程"", 《HTTPS://WWW.MR-WU.CN/DDR-LAYOUT-RULES-PROCESSES/》 * |
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Application publication date: 20180824 |
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| RJ01 | Rejection of invention patent application after publication |