CN108427584A - The configuration method of the chip and the chip with parallel computation core quickly started - Google Patents
The configuration method of the chip and the chip with parallel computation core quickly started Download PDFInfo
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- CN108427584A CN108427584A CN201810225699.XA CN201810225699A CN108427584A CN 108427584 A CN108427584 A CN 108427584A CN 201810225699 A CN201810225699 A CN 201810225699A CN 108427584 A CN108427584 A CN 108427584A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
Abstract
The present invention provides a kind of configuration method of the chip and the chip with parallel computation core quickly started, the chip includes multiple calculating cores and calculates the one-to-one routing node of core with each, one calculates core and forms a calculate node with a corresponding routing node, and corresponding nonvolatile memory is equipped with for multiple calculating caryogamy；Each configuration information for calculating core is stored in the nonvolatile memory, when the chip starts, each calculating core obtains configuration information from corresponding nonvolatile memory and configured.The present invention is multiple calculating core configuring non-volatile memories of chip, wherein it is stored with each configuration information for calculating core, when powering down chips are restarted, each calculating core in chip directly can obtain configuration information from nonvolatile memory and be configured, without being externally introduced configuration information, quick startup when chip power-down is restarted can be realized.
Description
Technical field
The present invention relates to chip technology fields, more particularly, to a kind of chip and the chip with parallel computation core
Configuration method.
Background technology
Under the trend of big data development, the more and more extensive application of parallel computation, for example, class brain computing platform, possesses very
Multi-neuron, is embodied in class brain computing platform, i.e., has much calculating cores, many calculating nuclear energy enough parallel on computing chip
It calculates while numerous class brain computing platforms are succeeded in developing, much optimizations to class brain computing platform are also carrying out, such as needle
The low precision feasibility for studying hardware system precision deficiency algorithm, is studied non-volatile for the volatibility of hardware memory
The design etc. of property memory class brain computing platform.And class brain computation model large-scale increasingly, class brain computing platform is in order to prop up
Hold large-scale computation model, it is also necessary to have large-scale calculations resource, so as to cause needing to read from outside when starting platform
Configuration information to the internal system of magnanimity is taken to be configured, the time of this configuration is very long for calculating, to shadow
The efficiency of computing system is rung.
Invention content
The present invention, which provides a kind of one kind for overcoming the above problem or solving the above problems at least partly, has parallel meter
The chip of core and the configuration method of the chip are calculated, can be solved the problems, such as slow-footed when chip starts.
According to an aspect of the invention, there is provided a kind of chip of parallel computation core, the chip include multiple calculating
Core and with each calculating one-to-one routing node of core, each calculates core and a corresponding routing node and forms one
A calculate node, multiple calculating caryogamy are equipped with corresponding nonvolatile memory；
Each configuration information for calculating core is stored in the nonvolatile memory, when the chip restarts,
Each calculating core in the chip obtains corresponding configuration information from corresponding nonvolatile memory and is configured.
Based on the above technical solution, the present invention can also improve as follows.
Further, include at least one nonvolatile memory inside each described calculating core；
At least one nonvolatile memory, for storing the corresponding configuration information for calculating core, for opening again
When dynamic, calculating core therefrom obtains configuration information and is configured.
Further, further include at least one volatile memory, cache module, one in each described calculating core
A control module and a capacitance module；
The cache module, for caching the data being passed to by the outside that data/address bus receives；
Critical data is stored in described by the control module, the importance for judging data in the cache module
In nonvolatile memory, non-critical data is stored in volatile memory, the critical data, which includes at least, calculates core
Configuration information；
The volatile memory, for storing non-critical data, the non-critical data includes calculating data, calculating
The result data after intermediate data and calculating in journey；
The capacitance module, in the case of power down, powering for the nonvolatile memory.
Further, at least one nonvolatile memory is configured between multiple calculating cores, multiple calculating cores share institute
State at least one nonvolatile memory；
At least one nonvolatile memory, for storing corresponding multiple configuration informations for calculating core, for institute
When stating chip restarting, each calculating core therefrom obtains corresponding configuration information and is configured.
Further, cache module, a control module and a capacitance there are one being also configured between multiple calculating cores
Module, and it is also configured at least one volatile memory inside each calculating core；
The cache module, for caching the data being passed to by the outside that data/address bus receives；
Critical data is stored in described by the control module, the importance for judging data in the cache module
In nonvolatile memory, non-critical data is stored in volatile memory, the critical data includes at least each meter
Calculate the configuration information of core；
The volatile memory, for the non-critical data in storage computation process, the non-critical data includes meter
Count evidence, the intermediate data in calculating process and the result data after calculating；
The capacitance module, in the case of power down, powering for the nonvolatile memory.
Further, further include computing module, data processing module and on-line study mould inside each described calculating core
Block；
Each calculates core, for obtaining configuration information from corresponding nonvolatile memory, respectively to the calculating
Module, the data processing module and the on-line study module are configured accordingly.
Further, the data processing module is used for from the nonvolatile memory and/or the volatile storage
Device gets data to be treated, is pre-processed to the data；
The computing module for calculating pretreated data, and the result data after calculating is stored in
In the volatile memory；
The control module, for judging whether the result data in the volatile memory is critical data, if so,
Then the result data is moved in the nonvolatile memory, if it is not, the result data is retained in the volatibility
In memory.
Further, the on-line study module, for being carried out more to the configuration information in the nonvolatile memory
Change.
According to another embodiment of the invention, a kind of configuration method of the chip with parallel computation core is provided,
The chip include multiple calculating cores and with each calculating the one-to-one routing node of core, each calculate core with it is corresponding
A routing node form a calculate node, including：
Corresponding nonvolatile memory is set for multiple calculating caryogamy, wherein is stored in the nonvolatile memory
Each configuration information for calculating core；
When the chip starts, each calculates core and obtains configuration information progress from corresponding nonvolatile memory
Configuration.
According to the third aspect of the present invention, a kind of non-transient computer readable storage medium is provided, it is described non-transient
Computer-readable recording medium storage computer instruction, the computer instruction, which makes the computer execute, has parallel computation core
Chip configuration method.
Description of the drawings
Fig. 1 is the chip structure schematic diagram with parallel computation core of one embodiment of the invention quickly started；
Fig. 2 is the chip knot of configuring non-volatile memory NVRAM in parallel computation core of one embodiment of the invention
Structure schematic diagram；
Fig. 3 is the configuring non-volatile memory NVRAM between multiple parallel computation cores of another embodiment of the present invention
Chip structure schematic diagram；
Fig. 4 is nonvolatile memory NVRAM and other connection diagrams for being configured part；
Data communication knots of the Fig. 5 between nonvolatile memory NVRAM, volatile memory VRAM and other modules
Composition；
Fig. 6 is the data flow and processing schematic diagram calculated in core；
Fig. 7 is the structural schematic diagram of third generation nature's mystery chip one single chip；
Fig. 8 is the internal structure schematic diagram of third generation nature's mystery chip one single chip；
Fig. 9 is the server entity structural schematic diagram of one embodiment of the invention.
Specific implementation mode
With reference to the accompanying drawings and examples, the specific implementation mode of the present invention is described in further detail.Implement below
Example is not limited to the scope of the present invention for illustrating the present invention.
In one embodiment of the present of invention, a kind of chip with parallel computation core quickly started is provided, referring to figure
1, the chip include multiple calculating cores and with each calculating the one-to-one routing node of core, each calculate core with it is right
The routing node answered forms a calculate node.Multiple calculating caryogamy are equipped with corresponding nonvolatile memory, described non-
Each configuration information for calculating core is stored in volatile memory, when the chip starts, each calculates core from correspondence
Nonvolatile memory in obtain configuration information configured.
Chip provided in this embodiment have can concurrent collaborative work to support class brain calculate multiple calculating cores, with
And the routing node answered with each calculation and check, each calculates one in core and corresponding routing node compositing chip
A calculate node.Data communication between calculate node is carried out by pre-set routing policy, and data are calculated from some
Core sets out, several routing nodes of approach reach target and calculate core.
When class brain computing system breaks down or power down needs to restart, need to come from the outside a large amount of configuration information of reading
Carrying out configuration ability normal operation to each calculating core can cause class brain to calculate system from the extraneous configuration information for reading bulk redundancy
It is very slow that system starts speed.In order to solve this problem, the present embodiment is set corresponding non-easy for multiple calculating caryogamy in chip
Data in the property lost memory NVRAM, nonvolatile memory NVRAM will not lose after a power failure, non-volatile memories
Each configuration information for calculating core is stored in device NVRAM.When class brain computing system is due to failure or power-down rebooting, Ge Geji
Calculation core can directly obtain corresponding configuration information from nonvolatile memory NVRAM and be configured, and be restarted quickly fortune
Row, compared to current when restarting, the speed restarted from external acquisition configuration information is faster.
On the basis of the above embodiments, include extremely inside each described calculating core in one embodiment of the present of invention
A few nonvolatile memory；At least one nonvolatile memory, for store it is corresponding calculate core match confidence
Breath, when for restarting, calculating core therefrom obtains configuration information and is configured.
For there are many multiple modes for calculating core configuring non-volatile memory NVRAM in chip, two are mainly introduced below
Kind of mode, reference can be made to Fig. 2, first way be set for the calculating caryogamy inside each calculating core it is at least one non-volatile
Memory NVRAM, wherein the configuration information of the calculating core is stored at least one nonvolatile memory NVRAM.Each meter
Core is calculated during restarting, is concurrently carried out using the configuration information in the nonvolatile memory NVRAM calculated inside core
Configuration, so that during entirely restarting, start speed is not influenced by computing system scale, therefore even super large is advised
The class brain computing platform of mould remains able to rapidly be restarted.
First way is being used to set corresponding nonvolatile memory NVRAM for multiple calculating caryogamy, i.e., each is counted
It calculates and configures a nonvolatile memory NVRAM inside core, it further includes at least one volatile storage that each, which is calculated inside core,
Device, a cache module, a control module and a capacitance module, reference can be made to each in Fig. 3, Fig. 3 calculates packet inside core
Include multiple nonvolatile memory NVRAM, multiple volatile memory VRAM, a cache module, a control module and one
A capacitance module.It is connected by data/address bus between multiple nonvolatile memory NVRAM and multiple volatile memory VRAM.
Wherein, cache module, for caching the data being passed to by the outside that data/address bus receives；Control module is used for
Critical data is stored in nonvolatile memory NVRAM by the importance for judging data in cache module, by non-critical data
It is stored in VRAM volatile memory, critical data therein includes at least the configuration information for calculating core.Volatile memory,
For storing non-critical data, non-critical data includes calculating data, the intermediate data in calculating process and the result after calculating
Data；Capacitance module, in the case of power down, being nonvolatile memory NVRAM power supplies.
Storage needs the data stored for a long time, volatile memory VRAM storages to be not required in nonvolatile memory NVRAM
The data quickly read are stored or needed for a long time.In the case where happening suddenly power down, when losing power supply, the electricity in capacitance module
Appearance charge can supply nonvolatile memory NVRAM and carry out of short duration read-write capability, for storing important and crucial data,
It is unlikely in burst power down to be to lose the data read and write.Wherein, critical data can be defined as losing the data, system without
Method is voluntarily run with the help of external device, and non-critical data be primarily referred to as calculate object, calculating intermediate data with
And final result data after calculating.
It is multiple calculating cores in chip in an alternative embodiment of the invention on the basis of above-mentioned each embodiment
The second way for configuring corresponding nonvolatile memory NVRAM be configured between multiple calculating cores it is at least one it is non-easily
The property lost memory NVRAM, multiple calculating cores share a nonvolatile memory NVRAM, that is to say, that nonvolatile memory
NVRAM, which is arranged in, to be calculated except core.At least one nonvolatile memory of configuration, for storing corresponding multiple calculating
The configuration information of core, when starting for chip, each calculating core therefrom obtains corresponding configuration information and is configured.Referring to figure
4, it is every four calculate core share nonvolatile memory a NVRAM, NVRAM in be stored with this four calculating core match confidence
Breath reads corresponding configuration information from nonvolatile memory NVRAM, completes the configuration of itself when calculating core is restarted.Its
In, each configuration information for calculating core may be different, stores the configuration of four calculating core in the nonvolatile memory
When information, calculating core can be given to be numbered, different configuration informations is stored to the calculating core of different numbers.Core needs are calculated to match
When confidence ceases, the configuration information itself needed is obtained according to number, to which during restarting, four calculate core composition one
A startup group is carried out restarting configuration process parallel between multiple groups, for ultra-large class brain computing platform, be remained able to
Carry out rapid re-strike.
Under the mode that is configured so that, also configured between multiple calculating cores there are one cache module, a control module and
One capacitance module, and it is also configured at least one volatile memory inside each calculating core.
The cache module, for caching the data being passed to by the outside that data/address bus receives；The control module is used
In the importance for judging data in the cache module, critical data is stored in the nonvolatile memory, by non-pass
Key data is stored in volatile memory, and the critical data includes at least each configuration information for calculating core；It is described volatile
Property memory, for the non-critical data in storage computation process, the non-critical data includes calculating in data, calculating process
Intermediate data and calculating after result data；The capacitance module, in the case of power down, being described non-volatile
Memory is powered.
From the above various embodiments as can be seen that when nonvolatile memory NVRAM is configured at and calculates inside core, mould is cached
Block, control module and capacitance module, which are configured at, to be calculated inside core, is calculated outside core when nonvolatile memory NVRAM is configured at
When, then cache module, control module and capacitance module, which are also configured at, calculates inside core, regardless of be any configuration mode,
Volatile memory VRAM, which is disposed on, to be calculated inside core.
On the basis of the various embodiments described above, in one embodiment of the invention, reference can be made to Fig. 5, each described calculating core
Inside further includes computing module, data processing module and on-line study module；Each calculates core, is used for from corresponding non-volatile
Configuration information is obtained in property memory, respectively to the computing module, the data processing module and the on-line study mould
Block is configured accordingly.
On the basis of above-mentioned each embodiment, in one embodiment of the present of invention, referring to Fig. 6, the data processing mould
Block, for getting data to be treated from the nonvolatile memory and/or the volatile memory, if data
It is critical data, is then obtained from nonvolatile memory NVRAM, if data is non-critical data, from volatile memory
It obtains in VRAM, after data processing module gets these data, these data is pre-processed；The computing module is used
It is calculated in pretreated data, and the result data after calculating is stored in the volatile memory；It is described
Control module, for judging whether the result data in the volatile memory is critical data, if so, by the result
Data move in the nonvolatile memory, if it is not, the result data is retained in the volatile memory.Wherein
On-line study module, the configuration information in the nonvolatile memory can be modified by on-line study.
Wherein, it is third generation nature's mystery chip one single chip referring to Fig. 7, third generation nature's mystery chip therein has used non-easy
The class brain computing system that the property the lost memory NVRAM structure present invention is described, refers to Fig. 7, each core is equivalent to this hair
One in bright calculates core, and 13 × 12 core are shared on a chip chip.Data transmission between Core uses 2D-mesh
Two-dimensional grid first class by.Structure inside single Core, refers to Fig. 8 comprising routing module, aixs cylinder module, dendron mould
Block and cell space module.Relationship between module in Fig. 8 and foregoing description module refers to table 1.
Each module and each module mapping table in above-described embodiment in 1 nature's mystery 3 of table
The significant data of entire Core is stored in dendron mould NVRAM in the block, therefore third generation nature's mystery chip can be real
The long-term storage of distribution of existing configuration information, to quickly start after realizing power down.And it due to there is module for reading and writing, may be implemented
The continuous learning of on piece.
Based on above-mentioned each embodiment, the present invention also provides a kind of configuration sides of the chip with parallel computation core
Method, wherein the chip includes multiple calculating cores and calculates the one-to-one routing node of core with each, each calculating
Core forms a calculate node with a corresponding routing node, including：Corresponding non-volatile deposit is set for multiple calculating caryogamy
Reservoir, wherein each configuration information for calculating core is stored in the nonvolatile memory；When the chip starts, often
One calculating core obtains configuration information from corresponding nonvolatile memory and is configured.
When the calculating core restarting in chip, to the process that each calculating core is configured, may refer to above-mentioned
The technical characteristic of each embodiment, details are not described herein.
It is a kind of server of the present invention referring to Fig. 9, including：Processor (processor) 901, memory (memory)
902 and bus 903；Wherein, the processor 901 and memory 902 complete mutual communication by the bus 503.
The processor 901 is used to call the program instruction in the memory 902, to execute above-mentioned each method embodiment
The method provided, such as including：Corresponding nonvolatile memory is set for multiple calculating caryogamy, wherein described non-volatile
Each configuration information for calculating core is stored in memory；When the chip starts, each calculate core from it is corresponding it is non-easily
Configuration information is obtained in the property lost memory to be configured.
The embodiments such as the equipment of configuration method of chip with parallel computation core described above are only schematic
, wherein may or may not be physically separated as the unit that separating component illustrates, shown as unit
Component may or may not be physical unit, you can be located at a place, or may be distributed over multiple services
On end unit.Some or all of module therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.Those of ordinary skill in the art are not in the case where paying performing creative labour, you can to understand and implement.
Through the above description of the embodiments, those skilled in the art can be understood that each embodiment can
It is realized by the mode of software plus required general hardware platform, naturally it is also possible to pass through hardware.Based on this understanding, on
Stating technical solution, substantially the part that contributes to existing technology can be expressed in the form of software products in other words, should
Computer software product can store in a computer-readable storage medium, such as ROM/RAM, magnetic disc, CD, including several fingers
It enables and using so that a computer equipment (can be personal computer, server or server device etc.) executes each reality
Apply certain Part Methods of example or embodiment.
A kind of configuration method of chip and the chip with parallel computation core quickly started provided by the invention is core
Multiple calculating core configuring non-volatile memories of piece work as powering down chips wherein being stored with each configuration information for calculating core
When restarting, each calculating core in chip directly can obtain configuration information from nonvolatile memory and be configured, and
Without being externally introduced configuration information, quick startup when chip power-down is restarted can be realized.
Finally, the present processes are only preferable embodiment, are not intended to limit the scope of the present invention.It is all
Within the spirit and principles in the present invention, any modification, equivalent replacement, improvement and so on should be included in the protection of the present invention
Within the scope of.
Claims (10)
1. a kind of chip with parallel computation core quickly started, which is characterized in that the chip include multiple calculating cores with
And form a meter with each calculating one-to-one routing node of core, each calculating core and a corresponding routing node
Operator node, multiple calculating caryogamy are equipped with corresponding nonvolatile memory；
Each configuration information for calculating core is stored in the nonvolatile memory, it is described when the chip restarts
Each calculating core in chip obtains corresponding configuration information from corresponding nonvolatile memory and is configured.
2. chip as described in claim 1, which is characterized in that include at least one non-volatile inside each described calculating core
Property memory；
At least one nonvolatile memory, for storing the corresponding configuration information for calculating core, when for restarting,
Calculating core therefrom obtains configuration information and is configured.
3. chip as claimed in claim 2, which is characterized in that further include at least one volatibility in each described calculating core
Memory, a cache module, a control module and a capacitance module；
The cache module, for caching the data being passed to by the outside that data/address bus receives；
Critical data is stored in described non-easy by the control module, the importance for judging data in the cache module
In the property lost memory, non-critical data is stored in volatile memory, the critical data, which includes at least, calculates matching for core
Confidence ceases；
The volatile memory, for storing non-critical data, the non-critical data includes calculating in data, calculating process
Intermediate data and calculating after result data；
The capacitance module, in the case of power down, powering for the nonvolatile memory.
4. chip as described in claim 1, which is characterized in that configure at least one non-volatile deposit between multiple calculating cores
Reservoir, multiple calculating cores share at least one nonvolatile memory；
At least one nonvolatile memory, for storing corresponding multiple configuration informations for calculating core, for the core
When piece restarts, each calculating core therefrom obtains corresponding configuration information and is configured.
5. chip as claimed in claim 4, which is characterized in that also configured between multiple calculating cores there are one cache module,
One control module and a capacitance module, and it is also configured at least one volatile storage inside each calculating core
Device；
The cache module, for caching the data being passed to by the outside that data/address bus receives；
Critical data is stored in described non-easy by the control module, the importance for judging data in the cache module
In the property lost memory, non-critical data is stored in volatile memory, the critical data includes at least each calculating core
Configuration information；
The volatile memory, for the non-critical data in storage computation process, the non-critical data includes calculating number
According to the intermediate data in, calculating process and the result data after calculating；
The capacitance module, in the case of power down, powering for the nonvolatile memory.
6. chip as described in any one in claim 1-5, which is characterized in that further include calculating inside each described calculating core
Module, data processing module and on-line study module；
Each calculate core, for obtaining configuration information from corresponding nonvolatile memory, respectively to the computing module,
The data processing module and the on-line study module are configured accordingly.
7. chip as claimed in claim 6, which is characterized in that
The data processing module, for getting needs from the nonvolatile memory and/or the volatile memory
The data of processing pre-process the data；
The computing module for calculating pretreated data, and the result data after calculating is stored in described
In volatile memory；
The control module, for judging whether the result data in the volatile memory is critical data, if so, will
The result data moves in the nonvolatile memory, if it is not, the result data is retained in the volatile storage
In device.
8. chip as claimed in claim 6, which is characterized in that
The on-line study module, for being modified to the configuration information in the nonvolatile memory.
9. a kind of configuration method of the chip with parallel computation core, the chip includes multiple calculating cores and is counted with each
The one-to-one routing node of core is calculated, each calculates core and forms a calculate node with a corresponding routing node, special
Sign is, including：
Corresponding nonvolatile memory is set for multiple calculating caryogamy, wherein is stored in the nonvolatile memory each
Calculate the configuration information of core；
When the chip starts, each calculating core obtains configuration information from corresponding nonvolatile memory and is matched
It sets.
10. a kind of non-transient computer readable storage medium, which is characterized in that the non-transient computer readable storage medium is deposited
Computer instruction is stored up, the computer instruction makes the computer execute the method as described in claim 1-8 is any.
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| CN104049687A (en) * | 2014-05-27 | 2014-09-17 | 上海微小卫星工程中心 | Embedded cubic star task computer based on FPGA (Field Programmable Gate Array) and reconstruction method thereof |
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| CN114021708A (en) * | 2021-09-30 | 2022-02-08 | 浪潮电子信息产业股份有限公司 | Data processing method, device and system, electronic equipment and storage medium |
| CN114021708B (en) * | 2021-09-30 | 2023-08-01 | 浪潮电子信息产业股份有限公司 | Data processing method, device and system, electronic equipment and storage medium |
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