CN108418559B - Nonlinear compensation power amplifying circuit and polar coordinate transmitter - Google Patents
Nonlinear compensation power amplifying circuit and polar coordinate transmitter Download PDFInfo
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- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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Abstract
The embodiment of the invention provides a nonlinear compensation power amplification circuit and a polar coordinate transmitter, wherein the circuit comprises a polar coordinate signal generator, a first digital-to-analog converter, a first filter, a second digital-to-analog converter, a second filter, a mixer, a decoder and M groups of power amplifiers, the unit gain of each group of power amplifiers in the M groups of power amplifiers is different, and the gain of each group of power amplifiers can be adjusted step by taking the corresponding unit gain as a step. The decoder is used for comparing the decoded amplitude value with a preset threshold value, and enabling one or more groups of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is smaller than the preset threshold value; when the decoded amplitude value is larger than a predetermined threshold value, supplementing a group of power amplifiers in addition to the enabled group or groups of power amplifiers; and performing power amplification on the output of the mixer by using part or all of the enabled power amplifiers in each group of power amplifiers according to the decoded amplitude value.
Description
Technical Field
The invention relates to the technical field of nonlinear compensation, in particular to a nonlinear compensation power amplification circuit and a polar coordinate transmitter.
Background
The polar coordinate transmitter amplifies and combines the amplitude signal and the phase signal of the signal respectively, and then restores the combined signal to the original signal.
Ideally the basic elements of each power amplifier are identical and they should be linearly superposed. However, the combined current may deviate from a linear combination, which is called amplitude-to-amplitude non-linearity (AM-AM). This non-linearity can cause spectral growth out-of-band and degradation of modulation quality in-band.
Disclosure of Invention
The embodiment of the invention provides a nonlinear compensation power amplification circuit and a polar coordinate transmitter, aiming at recovering an amplified and combined signal to an original signal and solving the problems of out-of-band frequency spectrum generation and in-band modulation quality reduction.
In a first aspect, the present invention provides a non-linear compensation power amplifying circuit, which may include: the system comprises a polar coordinate signal generator, a first digital-to-analog converter, a first filter, a second digital-to-analog converter, a second filter, a frequency mixer and M groups of power amplifiers; the unit gain of each power amplifier in the M groups of power amplifiers is different, the gain of each group of power amplifiers can be adjusted step by taking the corresponding unit gain as a step length, each group of power amplifiers comprises at least one power amplifier, and M is a positive integer; the polar coordinate signal generator is used for converting an input signal of the nonlinear compensation power amplifying circuit into a phase signal and an amplitude signal and performing sine and cosine conversion on the phase signal into a first phase signal and a second phase signal; the first digital-to-analog converter and the second digital-to-analog converter are respectively used for converting the first phase signal and the second phase signal and respectively outputting the converted signals to the first filter and the second filter; the first filter and the second filter are respectively used for filtering the output of the first digital-to-analog converter and the output of the second digital-to-analog converter and outputting the filtered outputs to the mixer; the mixer is used for mixing the output of the first filter and the output of the second filter and outputting the mixed output to the M groups of power amplifiers; a decoder for decoding the amplitude signal, enabling one or more of the M sets of power amplifiers when the decoded amplitude value is less than a predetermined threshold, and power-amplifying the output of the mixer using some or all of the enabled one or more sets of power amplifiers according to the decoded amplitude value; when the decoded amplitude value is greater than the predetermined threshold, additionally enabling one of the M sets of power amplifiers in addition to the enabled one or sets of power amplifiers, and power amplifying the output of the mixer using a part or all of the enabled sets of power amplifiers based on the decoded amplitude value.
Preferably, the predetermined threshold comprises a plurality of thresholds; a decoder, further configured to: enabling the M groups of power amplifiers when the decoded amplitude value is larger than the maximum threshold value in the preset threshold values, and performing power amplification on the output of the mixer by using all the enabled M groups of power amplifiers according to the decoded amplitude value; enabling one of the M sets of power amplifiers when the decoded amplitude value is less than a minimum threshold of the predetermined thresholds, and power amplifying an output of the mixer using a part or all of the enabled set of power amplifiers according to the decoded amplitude value.
Preferably, the predetermined threshold comprises i thresholds; a decoder, specifically configured to: enabling the 1 st group of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is larger than the 1 st threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled 1 st group of power amplifiers according to the decoded amplitude value; enabling the 1 st to ith group of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is larger than the ith threshold value, and performing power amplification on the output of the mixer by using all the enabled 1 st to ith-1 group of power amplifiers and part or all of the enabled power amplifiers in the ith group of power amplifiers according to the decoded amplitude value; wherein i increases with the increase of the decoded amplitude value, and the value of i ranges from 2 to M.
Preferably, the polar coordinate signal generator includes a signal conversion unit, a gain distributor and a gain operation unit; the signal conversion unit is used for converting an input signal of the nonlinear compensation power amplification circuit into a phase signal and an amplitude signal, and performing sine and cosine conversion on the phase signal into a first phase signal and a second phase signal; a gain distributor for distributing a first gain factor k1 and a second gain factor k2 according to system gain requirements; and a gain operation unit for multiplying the first gain factor k1 by the amplitude signal and outputting as first amplitude information.
Preferably, the gain operation unit is further configured to: the first phase signal and the second phase signal are multiplied by a second gain factor k2, respectively, and output as a third phase signal and a fourth phase signal.
Preferably, the first digital-to-analog converter and the second digital-to-analog converter are further configured to: and converting the third phase signal and the fourth phase signal and outputting the converted signals to the first filter and the second filter.
Preferably, the first digital-to-analog converter and the second digital-to-analog converter are further configured to: multiplying the first phase signal and the second phase signal by a second gain factor k2 respectively to output a third phase signal and a fourth phase signal; and converting the third phase signal and the fourth phase signal and outputting the converted signals to the first filter and the second filter.
Preferably, the first filter and the second filter are further configured to: multiplying the output of the first digital-to-analog converter and the output of the second digital-to-analog converter by a second gain factor k2, respectively, to output a fifth phase signal and a sixth phase signal; and filtering the fifth phase signal and the sixth phase signal and outputting the filtered signals to the mixer.
Preferably, the decoder is further configured to: enabling the 1 st group of power amplifiers in the M groups of power amplifiers when the amplitude value is larger than the 1 st threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled 1 st group of power amplifiers according to the decoded amplitude value; enabling the 1 st to jth power amplifiers in the M groups of power amplifiers when the amplitude value is larger than the jth threshold value, and performing power amplification on the output of the mixer by using all the enabled 1 st to jth-1 groups of power amplifiers and part or all of the jth group of power amplifiers according to the decoded amplitude value; wherein j increases with increasing amplitude value, and the value of j ranges from 2 to M.
Preferably, the non-linear compensation power amplifying circuit further includes: n capacitors and N switches, wherein N is an integer; n capacitors are connected in parallel; one end of each capacitor in the N capacitors is connected with the output of the frequency mixer, and the other end of each capacitor is connected with the first end of each switch in the N switches; each switch in the N switches further comprises a second end and a third end, the second end of each switch is connected with the ground, and the third end of each switch is connected with the output of the decoder;
a decoder, further configured to: when the decoded amplitude value is larger than the ith threshold value, controlling the conduction of the ith to Nth switches in N switches connected with N capacitors, wherein the value of i is from 1 to N; or when the decoded amplitude value is larger than the jth threshold, controlling the conduction of the jth to nth switches of the N switches connected with the N capacitors, wherein the value of j is from 1 to N.
In a second aspect, the present invention provides a polar transmitter, which may include: the nonlinear compensation power amplifying circuit is described above.
Compared with the prior art, the invention provides a nonlinear compensation power amplification circuit and a polar coordinate transmitter. Enabling one or more groups of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is smaller than a predetermined threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled one or more groups of power amplifiers according to the decoded amplitude value; when the decoded amplitude value is larger than the predetermined threshold value, additionally enabling one group of power amplifiers in the M groups of power amplifiers besides the enabled group or groups of power amplifiers, and performing power amplification on the output of the mixer by using part or all of the enabled groups of power amplifiers according to the decoded amplitude value; the unit gain of each of the M groups of power amplifiers is different, and the gain of each group of power amplifiers can be adjusted step by taking the corresponding unit gain as a step. Thereby improving the non-linearity of the power amplifier and solving the problems of out-of-band spectral generation and in-band modulation quality degradation.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the embodiments of the present invention and the drawings required in the background art, and it is obvious that the drawings described below are only some embodiments, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
FIG. 1 is a circuit diagram of the prior art;
FIG. 2 is a schematic diagram of the bandwidth of the phase signal before and after sine and cosine transform;
FIG. 3 is a block diagram of a non-linear compensated power amplifier circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the amplitude-to-amplitude non-linear compensation of FIG. 3;
FIG. 5 is a block diagram of another non-linearity compensation circuit according to an embodiment of the present invention;
FIG. 6 is a block diagram of a non-linear compensated power amplifier circuit according to an embodiment of the present invention;
FIG. 7 is a block diagram of a non-linear compensated power amplifier circuit according to an embodiment of the present invention;
fig. 8 is a gain distribution diagram of fig. 7.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a circuit diagram of the prior art. As shown in fig. 1, the circuit includes: digital-to-analog (D/a) converter 1, filter 1, D/a converter 2, filter 2, mixer, at least one PA and decoder. Only 3 PAs are exemplified in fig. 1.
The cartesian (I and Q) components of the phase signal of the input signal are generated at baseband by the sine-cosine transform of the original phase signal. The bandwidth of the phase signal after conversion is smaller than the bandwidth of the phase signal generated directly at radio frequency by a voltage controlled oscillator as in the prior art, as shown in fig. 2.
The phase signals I and Q components are used as inputs to the mixer, which outputs a radio frequency carrier by phase modulation. The amplitude modulation of the radio frequency carrier is realized by a PA, and the opening of the PA is controlled by the amplitude signal through the changing envelope of the decoder output.
Specifically, the input signal is converted into a phase signal phi and an amplitude signal amp, the phase signal phi is subjected to sine and cosine transformation and is output as a first phase signal sin (phi) and a second phase signal cos (phi), the first phase signal sin (phi) and the second phase signal cos (phi) are respectively input into the D/a converter 1 and the D/a converter 2, the first phase signal sin (phi) is subjected to D/a conversion by the D/a converter 1 and is output to the filter 1, a low-pass filter can be adopted in practical use, and the filter 1 is used for filtering out high frequency in the output signal of the D/a converter 1; the two-phase signal cos (phi) is output to the filter 2 after D/a conversion at the D/a converter 2, and in practical use, a low-pass filter may be adopted, and the filter 2 is used for filtering out high frequency in the output signal of the D/a converter 2; the mixer mixes the signals output by the filter 1 and the filter 2 and outputs the mixed signals.
The decoder comprises an input connected to the amplitude signal amp and an output connected to each amplifier in the at least one PA. The decoder is added to the circuit from at least one PA in accordance with the decoded amplitude signal.
Each PA of the at least one PA comprises two input terminals, an output terminal, a first input terminal of each PA being connected to the output terminal of the mixer, a second input terminal of each PA being connected to the output terminal of the decoder, the output terminals of each PA being interconnected.
However, in an actual circuit, due to the non-linearity of the PA, the signals output by the PA cannot be restored to the original input signals after being combined.
How the invention improves the non-linearity of the power amplifier is described in detail below with reference to fig. 3, 5, 6 and 7.
Fig. 3 is a block diagram of a non-linear compensation power amplifier circuit according to an embodiment of the present invention. Compared with fig. 3, the difference between fig. 1 and fig. 3 is that the nonlinear compensation power amplifying circuit further includes: a plurality of groups of power amplifiers, for example, M groups of power amplifiers, where the M groups of power amplifiers include at least one group of power amplifiers, and a unit gain of each group of power amplifiers in the M groups of power amplifiers is different, and may be different between groups or different for each power amplifier in a group; the gain of each group of power amplifiers can be adjusted step by step with the corresponding unit gain. M is a positive integer. In fig. 6, a first group PA 1, a second group PA 2, and an M-th group PA M are taken as an example.
Each power amplifier in each group of power amplifiers comprises a first input end, a second input end and an output end, the first input end of each power amplifier is connected with the output end of the mixer, and the second input end of each power amplifier is connected with the output end of the decoder.
Specifically, a first input terminal of each PA 1 in the first group PA 1 is connected to an output of the mixer, and a second input terminal of each PA 1 is connected to an output terminal of the decoder; a first input end of each PA 2 in the second group of PA 2 is connected with the output end of the mixer, and a second input end of each PA 2 is connected with the output end of the decoder; a first input of each PA M of the mth group of PAs M is connected to the output of the mixer and a second input of each PA M is connected to the output of the decoder. Each amplifier in each group of power amplifiers can realize multi-stage amplification in a cascade mode, and a proper connection mode is selected according to the use condition of the nonlinear compensation power amplification circuit, which is not described herein.
In the prior art, the basic amplifier cells of a power amplifier are identical, but after combining, the current deviates from a linear combination, which is called amplitude-to-amplitude non-linearity (AM-AM). In the embodiment of the present invention, the nonlinearity of AM-AM is compensated by using a piecewise linear approximation to implement the inverse function of amplitude compression, that is, M sets of PAs with different unity gains are set, where the unity gain for the first set of PAs is s1, the gain for the second set of PAs is s2, the gain for the third set of PAs is s3, the gain for the fourth set of PAs is s4, …, and the unity gain for the M set of PAs is s (n) (as shown in fig. 4). Comparing the amplitude value output by the decoder with a preset threshold value, and enabling one or more groups of power amplifiers in the M groups of power amplifiers if the amplitude value after decoding is smaller than the preset threshold value; if the amplitude value after decoding is larger than the predetermined threshold value, on the basis of enabling one or more groups of power amplifiers in the M groups of power amplifiers originally, supplement a group of power amplifiers; in both cases, the output signal of the mixer needs to be power-amplified by using some or all of the enabled power amplifiers in each group of power amplifiers according to the decoded decoder. Wherein the predetermined threshold comprises a plurality of thresholds; if the amplitude value decoded and output by the decoder is larger than the maximum threshold value in the preset threshold values, enabling all the M groups of power amplifiers, and performing power amplification on the output of the mixer by using all the enabled M groups of power amplifiers according to the decoded amplitude value; and if the decoded amplitude value is smaller than the minimum threshold value in the preset threshold values, enabling one group of power amplifiers in the M groups of power amplifiers, and performing power amplification on the output of the mixer by using part or all of the enabled group of power amplifiers according to the decoded amplitude value.
It is assumed that the predetermined threshold includes i thresholds; if the decoded amplitude value is larger than the 1 st threshold value, enabling the 1 st group of PAs, and performing power amplification on the output of the mixer by using part or all of the enabled 1 st group of power amplifiers according to the decoded amplitude value; if the decoded amplitude value is larger than the 2 nd threshold value, the 1 st to 2 nd groups of PAs need to be enabled, and then all the PAs in the enabled 1 st group of PAs and all or part of the PAs in the 2 nd group of PAs are used for amplifying the power of the output of the mixer according to the decoded amplitude value; in this way, if the decoded amplitude value is greater than the ith threshold, the 1 st to ith groups of PAs need to be enabled, and then, according to the decoded amplitude value, all PAs in the enabled 1 st to (i-1) th groups of PAs and all or part of PAs in the ith group of PAs are used to perform power amplification on the output of the mixer. The above-mentioned s1, s2, …, s (i) are unit gains corresponding to the 1 st to i th groups PA, and are also used to indicate a straight line segment in which the combined amplitude varies with the amplitude in the group. When the straight line segments represented by s1, s2, …, s (i) are connected, a compensation inverse function curve of amplitude compression nonlinearity is approximately obtained, so that the signal amplified by the PA can be recovered to the original linear signal, and the problems of out-of-band spectrum growth and in-band modulation quality reduction can be solved; wherein i increases with the increase of the decoded amplitude value, and the value of i ranges from 2 to M. The 1 st threshold to the ith threshold are larger and larger, each threshold corresponds to the number of PAs needing to be conducted, and the number of the conducted PAs is in direct proportion to the decoded amplitude value.
It should be noted that the unit gains of the PAs from the 1 st group to the M th group are sequentially increased, and as described above, when the decoded amplitude value is larger than the ith threshold, the decoded amplitude value is also larger than the 1 st threshold, the 2 nd threshold, …, and the (i-1) th threshold at this time, but only all the PAs from the 1 st group to the ith group corresponding to the ith threshold are enabled.
Fig. 5 is a block diagram of another non-linear compensation power amplifier circuit according to an embodiment of the present invention. Comparing fig. 5 is different from fig. 1 in that the non-linear compensation power amplifying circuit further includes N capacitors and N switches connected in parallel. As shown in fig. 5, one end of each of the N capacitors is connected to the first input terminal of each of the at least one PA, the other end of each of the N capacitors is connected to the first end of each of the N switches, the second end of each of the N switches is connected to a ground signal, and the third end of each of the N switches is connected to the output terminal of the decoder. In fig. 5, C1 and K1, C2 and K2, and C (n) and K (n) are given as an example, and the mode of the switch is the normally open mode. N is an integer.
Specifically, one end of the C1 is connected with a first input end of each PA in the at least one PA, the other end of the C1 is connected with a first end of the K1, a second end of the K1 is connected with a ground signal, and a third end of the K1 is connected with an output end of the decoder; one end of the C2 is connected with a first input end of each PA in the at least one PA, the other end of the C2 is connected with a first end of K2, a second end of the K2 is connected with a ground signal, and a third end of the K2 is connected with an output end of the decoder; one end of C (N) is connected with the first input end of each PA in at least one PA, the other end of C (N) is connected with the first end of K (N), the second end of K (N) is connected with a ground signal, and the third end of K (N) is connected with the output end of the decoder.
The magnitude of the capacitance value at the input of the power amplifier varies with the number of enabled PAs. This capacitance value varies with the amplitude signal output by the decoder, and the linear variation also varies nonlinearly. As long as there is a change in capacitance (phase PM) with respect to amplitude AM, there will be amplitude-to-phase non-linearity (AM-PM).
In the embodiment of the invention, N capacitors are connected in parallel at the input end of the power amplifier, so that when the capacitance value of the input end of the power amplifier changes along with the amplitude signal output by the decoder, the amplitude value output by the decoder is compared with a threshold value, and if the decoded amplitude value is larger than a preset threshold value, the closing or opening of N switches connected with the N capacitors is controlled, so that the effective capacitance value of the capacitor coupled between the output end of the mixer and the ground end is a first capacitance value; and if the decoded amplitude value is smaller than the preset threshold value, controlling N switches connected with N capacitors to enable the effective capacitance value of the capacitor coupled between the output end and the grounding end of the mixer to be a second capacitance value, wherein the second capacitance value is larger than the first capacitance value. Wherein the predetermined threshold comprises a plurality of thresholds; if the decoded amplitude value is larger than the maximum threshold value in the preset threshold values, controlling all N switches connected with the N capacitors to be turned off, so that the effective capacitance value of the capacitor coupled between the output end and the ground end of the mixer is 0; and when the decoded amplitude value is smaller than the minimum threshold value in the preset threshold values, controlling all N switches connected with the N capacitors to be conducted.
It is assumed that the predetermined threshold includes i thresholds; enabling part or all of the at least one power amplifier and controlling the conduction of the ith to Nth switches of the N switches connected with the N capacitors if the decoded amplitude value is larger than the ith threshold; enabling part or all of the at least one power amplifier and controlling N switches connected with N capacitors to be completely conducted if the decoded amplitude value is smaller than the 1 st threshold; wherein the number of power amplifiers of the at least one power amplifier is enabled to increase with increasing decoded amplitude signal, and the number of the at least one capacitor is enabled to decrease with increasing decoded amplitude signal; and further, the phase offset of the PA input end is compensated, so that the signals which are amplified and combined by the PA can be recovered to the original signals, and the problems of out-band spectrum growth and in-band modulation quality reduction can be solved. i takes values from 1 to N. The 1 st threshold value to the ith threshold value are larger and larger, each threshold value corresponds to the number of capacitors needing to be conducted, and the number of the conducting capacitors is inversely proportional to the decoded amplitude value. The first capacitance and the second capacitance correspond to a phase offset at the input of the PA in the access circuit, that is, the first capacitance and the second capacitance are used to compensate the phase offset at the input of the PA (which is involved in power amplification of the output of the mixer).
It should be noted that the capacitance value of the output end of the PA also changes with the change of the amplitude signal output by the decoder, so that N capacitors and N switches can be connected to the output end of the PA, and this connection method can also enable the number of capacitors in the N capacitors connected into the circuit according to the magnitude of the amplitude signal, so as to compensate the phase shift existing at the output end of the PA, so that the combined signal amplified by the PA can be restored to the original signal, and the problems of out-of-band spectrum growth and in-band modulation quality degradation can be solved; the connection manner of the N capacitors and the N switches may be the same as that in fig. 5.
Fig. 6 is a block diagram of a non-linear compensation power amplifier circuit according to another embodiment of the present invention. Comparing fig. 6, it differs from fig. 1 in that the non-linear compensation power amplifying circuit further includes N inductors and N switches connected in series. As shown in fig. 6, one end of each of the N inductors is connected to the first input terminal of each PA of the at least one PA and the first end of each of the N switches, the other end of each of the N inductors is connected to the ground signal and the second end of each of the N switches, and the third end of each of the N switches is connected to the output terminal of the decoder. In fig. 6, L1 and K1, L2 and K2, and L (n) and K (n) are given as an example. N is an integer.
Specifically, one end of L1 is connected to a first input end of each PA of the at least one PA, a first end of K1 is connected, the other end of L1 is connected to a second end of K1, one end of L2, a first end of K2, and a third end of K1 is connected to an output end of the decoder; the other end of the L2 is connected with the second end of the K2, and the third end of the K2 is connected with the output end of the decoder; one end of L (N) is connected with the first end of K (N), the other end of L (N) is connected with the second end of K (N) and the ground, and the third end of K (N) is connected with the output end of the decoder.
In the embodiment of the invention, N inductors are connected to the input end of the power amplifier in series, so that different quantities of inductors can be connected into the circuit according to the magnitude of the amplitude signal output by the decoder, and the phase offset of the PA at the input end is compensated, so that the signals combined after being amplified by the PA can be recovered to the original signals, and the problems of out-of-band spectrum growth and in-band modulation quality reduction can be solved.
It should be noted that the capacitance value of the output end of the PA also changes with the amplitude signal output by the decoder, so that N inductors and N switches can be connected to the output end of the PA, and this connection mode can also enable the number of inductors in the N inductors to be connected into the circuit according to the magnitude of the amplitude signal, so as to compensate the phase shift existing at the output end of the PA, so that the combined signal after being amplified by the PA can be recovered to the original signal, and the problems of out-of-band spectrum growth and in-band modulation quality degradation can be solved; the connection manner of the N inductors and the N switches may be the same as that in fig. 6.
It should be noted that the power amplifiers in fig. 5 and fig. 6 may also be multiple sets of power amplifiers, and the unit gains of the power amplifiers in each set are different. The nonlinear compensation circuit can eliminate AM-AM nonlinearity and AM-PM nonlinearity at the same time.
Fig. 7 is a block diagram of another non-linear compensation power amplifier circuit according to an embodiment of the present invention. Comparing fig. 7 is different from fig. 1 in that the polar coordinate signal generator includes a signal conversion unit, a gain distributor, and a gain operation unit.
The signal conversion unit is used for converting an input signal of the nonlinear compensation power amplification circuit into a phase signal and an amplitude signal and performing sine and cosine conversion on the phase signal into a first phase signal and a second phase signal; a gain distributor for distributing a first gain factor k1 and a second gain factor k2 according to system gain requirements; and the gain operation unit is used for multiplying the first gain factor k1 by the amplitude signal amp and outputting the result as a first amplitude signal amp'.
Assuming that the system gain requirement is 1.1, the following combinations [1.1, 1], [1, 1.1], [0.9, 1.2] can be used for the assigned gain combinations [ k2, k1], and the normalized gains of the three groups are calculated as [0.8 × 1] ═ 0.8, [1 × 0.9] ═ 0.9, [1.2 × 0.8] ═ 0.96, respectively. The third combination is most effective, and the most effective gain allocation can be stored, and when the system requires a certain total gain, the polar signal generator can read out the gain allocation factor from the internal memory. As shown in fig. 8.
The operation of the second gain factor k2 with the first phase signal and the second phase signal, respectively, may be performed in the polar signal generator, in the D/a converter, or in the filter. The details will be described below.
The first mode is as follows: the gain unit is further used for multiplying the first phase signal and the second phase signal by a second gain factor k2 respectively and outputting a third phase signal and a fourth phase signal; a D/a converter 1 and a D/a converter 2 for converting the third phase signal and the fourth phase signal, respectively, and outputting the converted signals to the filter 1 and the filter 2, respectively; a filter 1 and a filter 2 for filtering and outputting the output of the D/a converter 1 and the output of the D/a converter 2 to the mixer, respectively; a mixer for mixing the output of the filter 1 and the output of the filter 2 and outputting to at least one power amplifier; and the decoder is used for decoding the first amplitude signal, enabling all the power amplifiers in the at least one power amplifier when the decoded amplitude value is larger than the jth threshold value, and using part or all of the enabled power amplifiers in the at least one power amplifier according to the amplitude value. The jth threshold value then corresponds to the number of amplifiers in the at least one power amplifier. The larger the threshold j, the larger the amplitude value is, the larger the number of PAs turned on.
The second mode is as follows: d/a converter 1 and D/a converter 2, further for: multiplying the first phase signal and the second phase signal by a second gain factor k2 respectively to output a third phase signal and a fourth phase signal; converting the third phase signal and the fourth phase signal and outputting the converted signals to a filter 1 and a filter 2; a filter 1 and a filter 2 for filtering and outputting the output of the D/a converter 1 and the output of the D/a converter 2 to the mixer, respectively; a mixer for mixing the output of the filter 1 and the output of the filter 2 and outputting to at least one power amplifier; and the decoder is used for decoding the first amplitude signal, enabling all the power amplifiers in the at least one power amplifier when the decoded amplitude value is larger than the jth threshold value, and using part or all of the enabled power amplifiers in the at least one power amplifier according to the amplitude value. The jth threshold value then corresponds to the number of amplifiers in the at least one power amplifier. The larger the threshold j, the larger the amplitude value is, the larger the number of PAs turned on.
The third mode is as follows: filter 1 and filter 2, further for: multiplying the output of the D/a converter 1 and the output of the D/a converter 2 by a second gain factor k2, respectively, to output a fifth phase signal and a sixth phase signal; filtering the fifth phase signal and the sixth phase signal and outputting the filtered signals to the mixer; the mixer is used for mixing the fifth phase signal and the sixth phase signal and outputting the mixed signals to at least one power amplifier; and the decoder is used for decoding the first amplitude signal, enabling all the power amplifiers in the at least one power amplifier when the decoded amplitude value is larger than the jth threshold value, and using part or all of the enabled power amplifiers in the at least one power amplifier according to the amplitude value. The jth threshold value then corresponds to the number of amplifiers in the at least one power amplifier. The larger the threshold j, the larger the amplitude value is, the larger the number of PAs turned on.
It should be noted that, the D/a converter 1 and the D/a converter 2 are linear devices, and in the second mode, the D/a converter 1 and the D/a converter 2 may convert the first phase signal and the second phase signal, multiply the converted signals by the second gain factor k2, and output the multiplied results to the filter 1 and the filter 2, respectively.
The polar signal generator of figure 7 may be replaced with the polar signal generator of figure 5. The nonlinear compensation power amplifying circuit can eliminate AM-PM nonlinearity and gain distribution compensation nonlinearity through a phase path and an amplitude path.
A decoder, further configured to: decoding the first amplitude signal, enabling all power amplifiers in the at least one power amplifier when the decoded amplitude value is larger than a jth threshold, performing power amplification on the output of the mixer by using part or all of the enabled power amplifiers in the at least one power amplifier, and enabling the jth to nth switches of the N switches connected with the N capacitors to be conducted; and if the decoded amplitude value is smaller than the 1 st threshold value, enabling all N switches connected with the N capacitors to be conducted, and enabling the value of j to be from 1 to N.
The polar signal generator of figure 7 may be replaced with the polar signal generator of figure 3. The nonlinear compensation power amplifying circuit can eliminate AM-AM nonlinearity and gain distribution compensation nonlinearity through a phase path and an amplitude path.
A decoder, further configured to: enabling the 1 st group of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is larger than the 1 st threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled 1 st group of power amplifiers according to the decoded amplitude value; enabling the 1 st to jth power amplifiers in the M groups of power amplifiers when the decoded amplitude value is larger than the jth threshold, and performing power amplification on the output of the mixer by using all the enabled 1 st to jth-1 groups of power amplifiers and part or all of the jth group of power amplifiers according to the decoded amplitude value; wherein j increases with increasing decoded amplitude value, and the value of j ranges from 2 to M.
It should be noted that the system gain requirement is given by the external system to enable the ratio of the average output of some or all of the at least one power amplifier to the average input of the non-linearity compensated power amplification circuit.
The three nonlinear compensation power amplification circuits described in fig. 3, fig. 5 (fig. 6) and fig. 7 can be combined together to perform nonlinear compensation, so that the AM-AM nonlinearity, the AM-PM nonlinearity and the gain distribution compensation nonlinearity through the phase and amplitude paths can be eliminated. Thereby improving the non-linearity of the power amplifier and solving the problems of out-of-band spectral generation and in-band modulation quality degradation.
The embodiment of the invention provides a polar coordinate transmitter which comprises the nonlinear compensation power amplification circuit.
The invention provides a nonlinear compensation power amplification circuit and a polar coordinate transmitter. Enabling one or more groups of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is smaller than a predetermined threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled one or more groups of power amplifiers according to the decoded amplitude value; when the decoded amplitude value is larger than the predetermined threshold value, additionally enabling one group of power amplifiers in the M groups of power amplifiers besides the enabled group or groups of power amplifiers, and performing power amplification on the output of the mixer by using part or all of the enabled groups of power amplifiers according to the decoded amplitude value; the unit gain of each of the M groups of power amplifiers is different, and the gain of each group of power amplifiers can be adjusted step by taking the corresponding unit gain as a step. Thereby improving the non-linearity of the power amplifier and solving the problems of out-of-band spectral generation and in-band modulation quality degradation.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A non-linear compensated power amplification circuit, comprising: the system comprises a polar coordinate signal generator, a first digital-to-analog converter (1), a first filter (1), a second digital-to-analog converter (2), a second filter (2), a mixer, a decoder and M groups of power amplifiers; wherein the unit gain of each of the M groups of power amplifiers is different, the gain of each group of power amplifiers can be adjusted step by step with the corresponding unit gain as a step, each group of power amplifiers comprises at least one power amplifier, and M is a positive integer;
the polar coordinate signal generator is used for converting an input signal of the nonlinear compensation power amplifying circuit into a phase signal and an amplitude signal and performing sine and cosine conversion on the phase signal into a first phase signal and a second phase signal; the polar coordinate signal generator comprises a signal conversion unit, a gain distributor and a gain operation unit; the signal conversion unit is used for converting an input signal of the nonlinear compensation power amplification circuit into a phase signal and an amplitude signal and performing sine and cosine conversion on the phase signal into a first phase signal and a second phase signal; the gain distributor is used for distributing a first gain factor k1 and a second gain factor k2 according to the system gain requirement; the gain operation unit is used for multiplying the first gain factor k1 by the amplitude signal and outputting the first amplitude value;
the first digital-to-analog converter (1) and the second digital-to-analog converter (2) are respectively used for converting the first phase signal and the second phase signal and outputting the converted signals to the first filter (1) and the second filter (2);
the first filter (1) and the second filter (2) are respectively used for filtering the output of the first digital-to-analog converter (1) and the output of the second digital-to-analog converter (2) and outputting the filtered outputs to the mixer;
the mixer is used for mixing the output of the first filter and the output of the second filter and outputting the mixed output to the M groups of power amplifiers;
the decoder is used for decoding the amplitude signal, enabling one or more groups of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is smaller than a preset threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled one or more groups of power amplifiers according to the decoded amplitude value; additionally enabling one of the M groups of power amplifiers in addition to the one or each group of power amplifiers already enabled when the decoded amplitude value is greater than the predetermined threshold, and power amplifying the output of the mixer using some or all of the power amplifiers already enabled according to the decoded amplitude value.
2. The circuit of claim 1, wherein the predetermined threshold comprises a plurality of thresholds;
the decoder is further configured to:
enabling the M groups of power amplifiers when the decoded amplitude value is larger than the maximum threshold value in the preset threshold values, and performing power amplification on the output of the mixer by using all the enabled M groups of power amplifiers according to the decoded amplitude value; enabling one of the M sets of power amplifiers when the decoded amplitude value is less than a minimum threshold of predetermined thresholds, and power amplifying the output of the mixer using some or all of the enabled set of power amplifiers according to the decoded amplitude value.
3. The circuit of claim 2, wherein the predetermined threshold comprises i thresholds;
the decoder is specifically configured to:
enabling the 1 st group of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is larger than the 1 st threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled 1 st group of power amplifiers according to the decoded amplitude value;
enabling the 1 st to ith group of power amplifiers in the M groups of power amplifiers when the decoded amplitude value is larger than the ith threshold value, and performing power amplification on the output of the mixer by using all the enabled 1 st to ith-1 group of power amplifiers and part or all of the enabled power amplifiers in the ith group of power amplifiers according to the decoded amplitude value; wherein i increases with the increase of the decoded amplitude value, and the value of i ranges from 2 to M.
4. The circuit of claim 1, wherein the gain operation unit is further configured to:
and multiplying the first phase signal and the second phase signal by the second gain factor k2 respectively to output a third phase signal and a fourth phase signal.
5. The circuit according to claim 4, wherein the first digital-to-analog converter (1) and the second digital-to-analog converter (2) are further configured to:
and converting and outputting the third phase signal and the fourth phase signal to the first filter (1) and the second filter (2).
6. The circuit according to claim 1, wherein the first digital-to-analog converter (1) and the second digital-to-analog converter (2) are further configured to:
multiplying the first phase signal and the second phase signal by the second gain factor k2 respectively to output a third phase signal and a fourth phase signal;
and converting and outputting the third phase signal and the fourth phase signal to the first filter (1) and the second filter (2).
7. The circuit according to claim 1, characterized in that said first filter (1) and said second filter (2) are further configured to respectively:
multiplying the output of the first digital-to-analog converter (1) and the output of the second digital-to-analog converter (2) by the second gain factor k2 respectively to output a fifth phase signal and a sixth phase signal;
and filtering the fifth phase signal and the sixth phase signal and outputting the filtered signals to the mixer.
8. The circuit of any of claims 3-7, wherein the decoder is further configured to:
enabling a group 1 power amplifier of the M groups of power amplifiers when the first amplitude value is larger than a 1 st threshold value, and performing power amplification on the output of the mixer by using part or all of the enabled group 1 power amplifiers according to the decoded amplitude value;
enabling the 1 st to jth groups of power amplifiers in the M groups of power amplifiers when the first amplitude value is larger than a jth threshold value, and performing power amplification on the output of the mixer by using all the enabled 1 st to jth-1 groups of power amplifiers and part or all of the jth group of power amplifiers according to the decoded amplitude value; wherein j increases with increasing first amplitude value, and j takes a value from 2 to M.
9. The circuit of claim 3, further comprising: n capacitors and N switches, wherein N is an integer; the N capacitors are connected in parallel; one end of each capacitor in the N capacitors is connected with the output of the mixer, and the other end of each capacitor is connected with the first end of each switch in the N switches; each switch of the N switches further comprises a second terminal and a third terminal, the second terminal of each switch is connected with the ground, and the third terminal of each switch is connected with the output of the decoder;
the decoder is further configured to:
when the decoded amplitude value is larger than the ith threshold value, controlling the conduction of the ith to Nth switches in the N switches connected with the N capacitors, wherein the value of i is from 1 to N; alternatively, the first and second electrodes may be,
and when the decoded amplitude value is larger than the jth threshold, controlling the conduction of the jth to nth switches of the N switches connected with the N capacitors, wherein the value of j is from 1 to N.
10. A polar transmitter comprising a non-linear compensated power amplification circuit as claimed in any one of claims 1 to 9.
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