CN108400570A - A kind of load faulty detection protection circuit and its control method - Google Patents
A kind of load faulty detection protection circuit and its control method Download PDFInfo
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- CN108400570A CN108400570A CN201810467477.9A CN201810467477A CN108400570A CN 108400570 A CN108400570 A CN 108400570A CN 201810467477 A CN201810467477 A CN 201810467477A CN 108400570 A CN108400570 A CN 108400570A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
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- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The load faulty detection protection circuit that the invention discloses a kind of for power supply system, power supply system include power supply, and first, second, third relay and load.Load faulty detection protection circuit includes reference signal generation circuit, test signal generation circuit, amplitude detection circuit, logic judging circuit and warning circuit.Reference signal generation circuit generates reference signal, test signal generation circuit generates test signal according to reference signal, the amplitude that amplitude detection circuit detects test signal generates amplitude signal, amplitude signal is generated compared with first threshold voltage and second threshold voltage control signal and controls the first, the second and third relay and warning circuit respectively by logic judging circuit.When short circuit, open circuit or electric leakage occur for load, load faulty detection protection circuit sends out sound-light alarm and will not provide power supply for load, to avoid leading to power supply or load further damage due to load faulty.
Description
Technical field
The present invention relates to the fault detect of power electronics field more particularly to capacitive load and protection circuit and
Detect guard method.
Technical background
The start-up capacitance of current power storage system and part motor is substantially made of capacitive load, inside can wait
Effect is considered as a capacitance.Capacitive load when in use, be easy to happen open circuit, short circuit, electric leakage situations such as, in this case, if
Corresponding safeguard measure cannot be detected and taken in time, and the secondary damage of capacitive load equipment can be caused even to damage power supply electricity
Source.
Therefore it needs one kind that can detect load cut-off, open circuit and drain conditions and protects load equipment and power supply
Circuit, to solve the above problems.
Invention content
One embodiment of the invention proposes a kind of load faulty detection protection circuit for power supply system, power supply system packet
Include power supply, the first relay, the second relay, third relay and capacitive load, wherein power supply and capacitive load
First end and second end is all had, wherein load faulty detection protection circuit includes reference signal generation circuit, test signal production
Raw circuit, amplitude detection circuit, logic judging circuit and warning circuit.Wherein reference signal generation circuit generates reference signal
To the first end of capacitive load.Test signal generation circuit is coupled to the second end of capacitive load, is generated and is surveyed according to reference signal
Trial signal.Amplitude detection circuit is coupled to test signal generation circuit to receive test signal, and exports characterization test signal width
The amplitude signal of value.Logic judging circuit receives amplitude signal and by it compared with first threshold voltage and second threshold voltage
First control signal is generated to control the first relay, the second relay and third relay and second control signal to control
Warning circuit.
One embodiment of the invention proposes a kind of method for detecting capacitive load, and the method includes generating with reference to letter
Number and be input to the first end of capacitive load, the reference signal generates a test signal in the second end of capacitive load；Inspection
It surveys the amplitude of test signal and generates amplitude signal with the amplitude of characterization test signal；By amplitude signal and first threshold voltage,
Second threshold voltage, which is compared, generates first control signal and second control signal；Wherein first control signal is for controlling the
One relay, the second relay and third relay, second control signal is for controlling warning circuit.
Load faulty proposed by the present invention detection protection circuit before load connects power supply to capacitive load equipment into
Row detection, if there is situations such as short circuit, electric leakage or open circuit occurs, operation of being protected and alarmed is very meaningful.
Description of the drawings
In order to better understand the present invention, the embodiment of the present invention will be described according to the following drawings.These attached drawings
It is given for example only.Attached drawing usually only shows system or the Partial Feature of circuit in embodiment, and attached drawing is not necessarily to scale
It draws.
Fig. 1 gives the module diagram of load faulty detection protection circuit 100 according to an embodiment of the invention.
Fig. 2 gives the circuit diagram of reference signal generation circuit 11 according to an embodiment of the invention.
Fig. 3 gives the circuit diagram of amplitude detection circuit 13 according to an embodiment of the invention.
Fig. 4 gives the circuit diagram of logic judging circuit 14 according to an embodiment of the invention.
Fig. 5 gives the circuit diagram of warning circuit 15 according to an embodiment of the invention.
Fig. 6 gives the circuit diagram of control relay circuit 16 according to an embodiment of the invention.
Fig. 7 gives the flow chart of the method 700 of detection power supply system load faulty according to an embodiment of the invention.
Identical reference numeral in different schematic diagrames indicates same or similar part or feature.
Specific implementation mode
Specific embodiments of the present invention are described more fully below, it should be noted that the embodiments described herein is served only for illustrating
Illustrate, is not intended to restrict the invention.In the following description, in order to provide a thorough understanding of the present invention, a large amount of spies are elaborated
Determine details.It will be apparent, however, to one skilled in the art that, it is not necessary to carry out this hair using these specific details
It is bright.In other embodiments, in order to avoid obscuring the present invention, well known circuit, material or method are not specifically described.
Throughout the specification, meaning is referred to " one embodiment ", " embodiment ", " example " or " example "
It：A particular feature, structure, or characteristic described in conjunction with this embodiment or example is comprised at least one embodiment of the present invention.
Therefore, the phrase " one embodiment " in each place appearance of the whole instruction, " embodiment ", " example ", " example "
It is not necessarily all referring to the same embodiment or example.Furthermore, it is possible to will be specific special with any combination appropriate and/or sub-portfolio
Sign, structure or feature combination are in one or more embodiments or example.In addition, it should be understood by one skilled in the art that
When claiming element " being connected to " or " being couple to " another element, it can be directly connected or coupled to another element or can be with
There are intermediary elements.On the contrary, when claiming element " being directly connected to " or " being directly coupled to " another element, cental element is not present
Part.Identical reference numeral indicates identical element.Term "and/or" used herein includes that one or more correlations are listed
Any and all combinations of project.
Fig. 1 gives the module diagram of load faulty detection protection circuit 100 according to an embodiment of the invention.Load
Fault detect protect circuit 100 include reference signal generation circuit 11, test signal generation circuit 12, amplitude detection circuit 13,
Logic judging circuit 14, warning circuit 15, the first relay K1, the second relay K2, third relay K3, power supply AC/
DC and load LD.In the illustrated embodiment, power supply AC/DC and load LD all have first end and second end.First relay
Device K1 has the power end for being coupled to DC power supply VCC, and control terminal, beginning and closed end, wherein closed end are coupled to power supply AC/
The first end of DC.In one embodiment, between the power end and control terminal of the first relay K1 an in parallel diode to protect the
One relay K1.Third relay K3 has the power end for being coupled to DC power supply VCC, control terminal, closed end and beginning, wherein closing
End is coupled to the second end of power supply AC/DC.In one embodiment, between the power end and control terminal of third relay K3 simultaneously
Join a diode to protect third relay K3.Second relay K2 is two channel relay, has and is coupled to DC power supply
The power end of VCC, control terminal, first switch S1 and second switch S2, wherein first switch S1 and second switch S2 all have often
Beginning, normal-closed end and common end.The normal-closed end of first switch S1 is coupled to reference signal generation circuit 11 to receive reference signal
The common end of SIN, first switch S1 are coupled to the first end of load LD, and the normally open end of first switch S1 is coupled to the first relay
The beginning of K1.The common end of second switch S2 is coupled to the second end of load LD, and the normal-closed end of second switch S2 is coupled to test
Signal generating circuit 12, the normally open end of second switch S2 are coupled to the beginning of third relay K3.In one embodiment, second after
One diode of parallel connection is to protect the second relay K2 between the power end and control terminal of electric appliance K2.12 coupling of test signal generation circuit
It is connected to the normal-closed end of the second relay second switch S2 and test signal SIN1 is generated to be input to amplitude according to reference signal SIN
Detection circuit 13.Amplitude detection circuit 13 detects the amplitude of test signal SIN1, and exports characterization test signal SIN1 amplitudes
Amplitude signal VP.Logic judging circuit 14 compares amplitude signal VP and first threshold voltage V1 and second threshold voltage V2
Compared with, and first control signal A is generated based on comparative result to control the first relay K1, the second relay K2 and third relay
K3 and second control signal B is to control warning circuit 15.In one embodiment, load faulty detection protection circuit 100 also wraps
Include control relay circuit 16, control relay circuit 16 receives first control signal A and generates the based on first control signal A
One relay signal CR1 to the control terminal of the first relay K1 and third relay K3 with control the first relay K1 and third after
Electric appliance K3 generates the second relay signal CR2 to the control terminal of the second relay K2 to control the second relay K2.
Continue the explanation of Fig. 1, test signal generation circuit 12 generates test signal SIN1 to input according to reference signal SIN
To amplitude detection circuit 13.In the illustrated embodiment, test signal generation circuit 12 includes the 9th resistance R9, the 9th resistance R9 tools
There are first end and second end, wherein first end to be coupled to the normal-closed end of the second relay second switch S2, second end is coupled to ginseng
Examine ground GND.Reference signal SIN is divided on load LD and the 9th resistance R9 and is formed test signal on the 9th resistance R9
SIN1.When load LD is in normal condition, the amplitude of the test signal SIN1 generated on the 9th resistance R9 is slightly less than with reference to letter
The amplitude of number SIN.When loading LD in short circuit or leakage condition, the width of the test signal SIN1 generated on the 9th resistance R9
Amplitude of the value equal to reference signal SIN.When loading LD and being in open-circuit condition, the test signal SIN1 that generates on the 9th resistance R9
Amplitude be zero.
Fig. 2 gives the circuit diagram of reference signal generation circuit 11 according to an embodiment of the invention.In diagram embodiment
In, reference signal generation circuit 11 includes square wave generation circuit 21, filter circuit 22, integrating amplification circuit 23 and common emitter amplification
Circuit 24.Square wave generation circuit 21 generates frequency and the adjustable square-wave signal CLK of amplitude, and filter circuit 22 receives square-wave signal
CLK is simultaneously filtered it generation triangular signal SLP, and integrating amplification circuit 23 is integrated and put to triangular signal SLP
Big to generate integrated signal AP, common emitter amplifying circuit 24 receives integrated signal AP and is further amplified it to generate reference signal
SIN。
In the illustrated embodiment, square wave generation circuit 21 includes the 5th resistance R5, the 8th resistance R8, the 7th capacitance C7, the
Six capacitance C6, thirteenth resistor R13 and square wave chip X.5th resistance R5 and the 7th capacitance C7 all have first end and second end,
There is 8th resistance R8 the first fixing end, the second fixing end and adjustable end, square wave chip X to have eight pins.5th resistance R5,
8th resistance R8 and the 7th capacitance C7 coupled in series are between DC power supply VCC and reference ground GND, wherein the of the 5th resistance R5
One end is coupled to DC power supply VCC, and the second end of the 7th capacitance C7 is coupled to reference ground GND.The first of 8th resistance R8 is fixed
End is coupled to the second end of the 5th resistance R5 and the 7th pin of square wave chip X, the second fixing end of the 8th resistance R8 and can
End is adjusted to be coupled to the 6th pin and second pin of square wave chip X.6th capacitance C6 has a first end and a second end, wherein first
End is coupled to reference ground GND, and second end is coupled to the 5th pin of square wave chip X.Thirteenth resistor R13 has first to fix
End, the second fixing end and adjustable end, wherein the first fixing end is coupled to the third pin of square wave chip X, the coupling of the second fixing end
In reference ground GND, the amplitude of square-wave signal CLK is adjusted in the adjustable end for adjusting thirteenth resistor R13.The first of square wave chip X
Pin is coupled to reference ground GND, and the 4th pin and the 8th pin are coupled to DC power supply VCC.In one embodiment, square wave chip
The model NE555 of X.
Continue the explanation of Fig. 2, filter circuit 22 includes the first rank filter circuit RF1 and second-order filter circuit RF2.First
Rank filter circuit RF1 includes the 5th capacitance C5, the 9th capacitance C9 and twelfth resistor R12.5th capacitance C5 have first end and
Second end, wherein first end receive square-wave signal CLK.9th capacitance C9 has a first end and a second end, and wherein first end couples
In the second end of the 5th capacitance C5, second end is coupled to reference ground GND.Twelfth resistor R12 has a first end and a second end,
Middle first end is coupled to the first end of the 9th capacitance C9, and second end exports first-order filtering signal SLP1.Second-order filter circuit RF2
Including eleventh resistor R11 and the 8th capacitance C8.Eleventh resistor R11 and the 8th capacitance C8 all have first end and second end,
The first end of eleventh resistor R11 and the first end of the 8th capacitance C8 are coupled together and receive first-order filtering signal SLP1, the
The second end of eight capacitance C8 is coupled to reference ground GND, the second end output triangular signal SLP of eleventh resistor R11.
In the embodiment depicted in figure 2, integrating amplification circuit 23 includes the second triode Q2, the tenth resistance R10, the 4th capacitance
C4 and the 6th resistance R6.Second triode Q2 has base stage, collector and emitter, wherein base stage receives triangular signal
SLP, emitter are coupled to reference ground GND, and collector exports integrated signal AP.4th capacitance C4 and the tenth resistance R10 are connected in parallel on
Between the base stage and collector of second triode Q2.6th resistance R6 is coupled to the base of DC power supply VCC and the second triode Q2
Between pole.
In the illustrated embodiment, common emitter amplifying circuit 24 include 3rd resistor R3, the 7th resistance R7, third capacitance C3 and
First triode Q1.There is first triode Q1 base stage, collector and emitter, wherein collector to be coupled to DC power supply VCC,
Base stage receives the integrated signal AP of integrating amplification circuit 23, and emitter is coupled to reference ground GND by the 7th resistance R7.Third electricity
Resistance R3 is coupled between the base stage and DC power supply VCC of the first triode Q1.Third capacitance C3 has a first end and a second end,
Middle first end is coupled to the emitter of the first triode Q1, and second end exports reference signal SIN.In one embodiment, the one three
Pole pipe Q1 and the second triode Q2 is NPN type triode, applies example another, the type of the first triode Q1 and the second triode Q2
Number be S9014.
Fig. 3 gives the circuit diagram of amplitude detection circuit 13 according to an embodiment of the invention.Amplitude detection circuit 13 is examined
It surveys the amplitude of test signal SIN1 and exports the amplitude signal VP of characterization test signal SIN1 amplitudes.Amplitude detection circuit 13 includes
First amplifier U3A and the second amplifier U3B, the 7th diode D7, the tenth capacitance C10 and the 23rd resistance R23.First puts
Big device U3A has first input end, the second input terminal and an output end, and wherein first input end receives test signal SIN1, and second
Input terminal is coupled to the anode of its output end and the 7th diode D7.Second amplifier U3B has first input end, and second is defeated
Enter end and output end, wherein first input end is coupled to the cathode of the 7th diode D7, and the second input terminal is coupled to its output end
And in output end output amplitude signal VP with the amplitude of characterization test signal SIN1.Tenth capacitance C10, the 23rd resistance R23
Coupled in parallel is between the second amplifier U3B first input ends and reference ground GND.In one embodiment, the first amplifier U3A and
Second amplifier U3B can be double operational integrated chip.In another embodiment, the first amplifier U3A and the second amplifier U3B
Including chip NE5532.In another embodiment, the model IN4007 of the 7th diode D7.
Fig. 4 gives the circuit diagram of logic judging circuit 14 according to an embodiment of the invention.Logic judging circuit 14 wraps
Include indicating circuit 41 and decision circuitry 42.In the illustrated embodiment, indicating circuit 41 includes window comparator circuit, and window is more electric
The upper limit voltage on road is first threshold voltage V1, and the lower voltage limit of window comparator circuit is second threshold voltage V2, when amplitude is believed
Number VP is less than first threshold voltage V1, and when being more than second threshold voltage V2, indication signal IND is in logic low.Work as amplitude signal
VP be more than first threshold voltage V1, or less than second threshold voltage V2 when, indication signal IND be it is logically high.Implement in diagram
In example, first threshold voltage V1, second threshold voltage V2 are by first resistor R1, second resistance R2 and the 4th resistance R4 partial pressure lifes
At the first resistor R1, second resistance R2 and the 4th resistance R4 are connected between DC power supply VCC and reference ground GND.Scheming
Show in embodiment, window comparator circuit includes first comparator U1A and the second comparator U1B, and first comparator U1A has first
Input terminal, the second input terminal and output end, wherein first input end receive amplitude signal VP, and the second input terminal receives first threshold
Voltage V1, output end are coupled to the anode of the first diode D1 and in the cathode of the first diode D1 output indication signal IND.The
There is two comparator U1B first input end, the second input terminal and output end, wherein first input end to receive second threshold voltage
V2, the second input terminal receive amplitude signal VP, and output end is coupled to the anode of the second diode D2 and the second diode D2's
Cathode exports indication signal IND.In one embodiment, first comparator U1A and the second comparator U1B is that a double operational is integrated
Chip.In another embodiment, first comparator U1A and the second comparator U1B includes chip NE5532.
Continue the explanation of Fig. 4, decision circuitry 42 includes third comparator U2A and the 4th comparator U2B.Third comparator
U2A has a first input end, the second input terminal and and output end, wherein first input end receive third threshold voltage V3, second
Input terminal receives indication signal IND, and output end exports first control signal A, wherein third threshold voltage V3 is by being connected on direct current
The 17th resistance R17 and the 22nd resistance R22 partial pressures between power supply VCC and reference ground GND are generated.In one embodiment,
Third threshold voltage V3 is equal to VCC/2.4th comparator U2B has first input end, the second input terminal and output end, wherein the
One input terminal receives indication signal IND, and the second input terminal receives third threshold voltage V3, and output end generates the based on comparative result
Two control signal B.In one embodiment, third comparator U2A and the 4th comparator U2B can be a double operational integrated chip,
In another embodiment, third comparator U2A and the 4th comparator U2B includes chip NE5532.
Fig. 5 gives the circuit diagram of warning circuit 15 according to an embodiment of the invention.Warning circuit 15 includes the 18th
Resistance R18, the 19th resistance R19, third transistor Q3, the 14th resistance R14, the 4th thyristor Q4, the 15th resistance R15,
First buzzer LS1 and the 4th diode D4.In the illustrated embodiment, the 18th resistance R18 and the 19th resistance R19 series connection connect
It connects, one end of the 18th resistance R18 receives second control signal B, and one end of the 19th resistance R19 is coupled to reference ground GND.The
There is three triode Q3 base stage, collector and emitter, the 14th resistance R14 to have a first end and a second end.Third transistor
Q3, the 14th resistance R14, the 4th thyristor Q4 and the 15th resistance R15 coupled in series are in DC power supply VCC and reference ground GND
Between, wherein the collector of third transistor Q3 is coupled to DC power supply VCC, and the base stage of third transistor Q3 is coupled to the tenth
The common end of eight resistance R18 and the 19th resistance R19, the emitter of third transistor Q3 are coupled to the one of the 14th resistance R14
End.15th resistance R15 has a first end and a second end, and wherein first end is coupled to reference ground GND.4th thyristor Q4 has
Anode, cathode and control pole, wherein the control pole of the 4th thyristor Q4 is coupled to the other end of the 14th resistance R14, cathode
It is coupled to the second end of the 15th resistance R15.First buzzer LS1 and the 4th diode D4 coupled in parallel are in DC power supply VCC
And the 4th between thyristor Q4 anodes, the anode of wherein diode D4 is coupled to DC power supply VCC.In one embodiment, third
The model S9014 of triode Q3.
Fig. 6 gives the circuit diagram of control relay circuit 16 according to an embodiment of the invention.Control relay circuit
16 include first control circuit 16A and second control circuit 16B.In the illustrated embodiment, first control circuit 16A receives first
Control signal A simultaneously generates the first relay signal CR1 to the control terminal of the first relay K1 and third relay K3 to control the
One relay K1 and third relay K3.Second control circuit 16B receives first control signal A and generates the second relay signal
CR2 is to the control terminal of the second relay K2 to control the second relay K2.First control circuit 16A includes the 25th resistance
R25, the 26th resistance R26, the 8th triode Q8, the 24th resistance R24, the 7th thyristor Q7.Wherein the 25th electricity
Hindering R25 and the 26th resistance R26 coupled in series, one end of the 26th resistance R26 receives first control signal A, and the 20th
One end of five resistance R25 is coupled to the Q7 series connection of the reference ground thyristor of GND, the 8th triode Q8, the 24th resistance R24, the 7th
It is coupled between DC power supply VCC and reference ground GND.8th triode Q8 has base stage, collector and emitter, wherein base stage
It is coupled to the common end of the 25th resistance R25 and the 26th resistance R26, collector is coupled to DC power supply VCC, emitter
It is coupled to one end of the 24th resistance R24.There is 7th thyristor Q7 anode, cathode and control pole, wherein control pole to couple
In the other end of the 24th resistance R24, cathode is coupled to reference ground GND, and anode pole exports the first relay signal CR1.
In one embodiment, the model S9014 of the 8th triode Q8.
Second control circuit 16B includes the 20th resistance R20, the 21st resistance R21, the 5th triode Q5, the 16th
Resistance R16, the 6th thyristor Q6.Wherein the 20th resistance R20 and the 21st resistance R21 coupled in series, the 20th resistance R20
One end receive first control signal A, one end of the 21st resistance R21 is coupled to reference ground GND.5th triode Q5, the
16 resistance R16, the 6th thyristor Q6 coupled in series is between DC power supply VCC and reference ground GND.5th triode Q5 has
Base stage, collector and emitter, wherein base stage are coupled to the common end of the 20th resistance R20 and the 21st resistance R21, current collection
Pole is coupled to DC power supply VCC, and emitter is coupled to one end of the 16th resistance R16.6th thyristor Q6 has anode and the moon
Pole and control pole, wherein control pole are coupled to the other end of the 16th resistance R16, and cathode is coupled to reference ground GND, anode output
Second relay signal CR2.In one embodiment, the model S9014 of the 5th triode Q5.
When load LD is normal, test signal generation circuit 12 is according to the reference signal SIN test signal SIN1's generated
Amplitude is slightly less than the amplitude of reference signal SIN, and the amplitude signal VP that amplitude detection circuit 13 exports is less than first threshold voltage V1
And it is more than second threshold voltage V2, the indication signal IND of characterization load LD states is logic low, corresponding first control signal A
To be logically high, second control signal B is logic low.Because first control signal A is logically high, the in first control circuit 16A
Eight triode Q8 and the 7th thyristor Q7 conductings, the first relay signal CR1 controls first of first control circuit 16A outputs after
Electric appliance K1, the K3 actions of third relay.Similarly, the 5th triode Q5 and the 6th thyristor Q6 conductings in second control circuit 16B,
Second relay signal CR2 control the second relay K2 actions of second control circuit 16B output, power supply AC/DC and negative
Carry LD connections conducting.Simultaneously as second control signal B is logic low, the first buzzer LS1 and the 4th in warning circuit 15
Diode D4 is not turned on, and warning circuit 15 is not alarmed.
When loading LD and being in short circuit, drain conditions, survey that test signal generation circuit 12 is generated according to reference signal SIN
The amplitude of trial signal SIN1 is identical with the amplitude of reference signal SIN, and the amplitude signal VP that amplitude detection circuit 13 exports is higher than the
The indication signal IND of one threshold voltage V1, characterization load LD states are logically high, and first control signal A is logic low, the second control
Signal B processed is logically high.First control signal A in logic low controls the first relay K1, the second relay K2 and third
Relay K3 is failure to actuate, and load LD and power supply AC/DC is off.In logically high second control signal B
Control the third transistor Q3 and the 4th thyristor Q4 conductings, the first buzzer LS1 and the 4th diode D4 in warning circuit 15
Conducting, warning circuit 15 send out alarm, and load LD is faulty at this time for prompt.
When load LD is in open circuit conditions, test signal generation circuit 12 is believed according to the test that reference signal SIN is generated
The amplitude of number SIN1 is zero, and the amplitude signal VP that amplitude detection circuit 13 exports is less than second threshold voltage V2, characterization load shape
The indication signal IND of state is logically high, and first control signal A is logic low, and second control signal B is logically high.Similarly, it alarms
Circuit 15 sends out alarm, and load LD is faulty at this time for prompt.
Fig. 7 gives the flow chart of the method 700 of detection power supply system load faulty according to an embodiment of the invention.For
Electric system includes power supply, the first relay, the second relay, third relay and capacitive load, wherein power supply and
Capacitive load all has first end and second end.Method 700 includes first step 701：Reference signal is input to capacitive load
First end, the reference signal capacitive load second end generate a test signal.Method 700 further includes second step
702：It detects the amplitude of test signal and generates amplitude signal with the amplitude of characterization test signal.Method 700 further includes third step
Rapid 703：By amplitude signal and first threshold voltage, second threshold voltage, which is compared, generates first control signal and the second control
Signal.Wherein first control signal is used for controlling the first relay, the second relay and third relay, second control signal
In control warning circuit.
In some above embodiments, " effective status " corresponds to the logic " high " state of high voltage, " invalid shape
State " corresponds to the logic " low " state of low-voltage, and still, in some other embodiment, " effective status " can be low electricity
Pressure, " invalid state " is high voltage.
Only the present invention will be described in an exemplary fashion for some above-mentioned specific embodiments.These embodiments are not
Completely in detail, it is not intended to limit the scope of the present invention.It is possible disclosed embodiment to be changed and is changed all,
Other feasible selective embodiments and can be by the ordinary skill people of the art to the equivalent variations of element in embodiment
Member is understood.Other change and modification of disclosed embodiment of this invention are limited without departing from spirit and claims of the present invention
Fixed protection domain.
Claims (10)
1. a kind of load faulty detection protection circuit for power supply system, power supply system includes power supply, the first relay,
Second relay, third relay and capacitive load, wherein power supply and capacitive load all have first end and second end, bear
Carrying fault detect protection circuit includes：
Reference signal generation circuit, the first end of generation reference signal to capacitive load；
Test signal generation circuit is coupled to the second end of capacitive load, and test signal is generated according to reference signal；
Amplitude detection circuit is coupled to test signal generation circuit to receive test signal, and exports characterization test signal amplitude
Amplitude signal；And
Logic judging circuit receives amplitude signal and it is generated to the first control compared with first threshold voltage and second threshold voltage
Signal processed is to control the first relay, the second relay and third relay and second control signal to control warning circuit.
2. as described in claim 1 for the load faulty of power supply system detection protection circuit, wherein
There is first relay beginning, closed end, power end and control terminal, wherein power end to be coupled to DC power supply, closed end coupling
In the first end of power supply；
There is second relay power end, control terminal, first switch and the second switch, wherein power end to be coupled to DC power supply,
First switch and the second switch all has normally open end, normal-closed end and common end, wherein the normally open end of first switch is coupled to first
The beginning of relay, the normal-closed end of first switch receive reference signal, and the common end of first switch is coupled to the of capacitive load
The normal-closed end of one end, second switch is coupled to test signal generation circuit, and the common end of second switch is coupled to capacitive load
Second end；And
There is third relay beginning, closed end, power end and control terminal, wherein power end to be coupled to DC power supply, beginning coupling
In the normally open end of the second relay second switch, closed end is coupled to the second end of power supply.
3. as described in claim 1 for the load faulty of power supply system detection protection circuit, wherein reference signal generates electricity
Road includes square wave generation circuit, filter circuit, integrating amplification circuit and common emitter amplifying circuit, wherein square wave generation circuit packet
It includes：
5th resistance, has a first end and a second end, and wherein first end is coupled to DC power supply；
8th resistance has the first fixing end, the second fixing end and adjustable end, wherein the first fixing end is coupled to the 5th resistance
Second end；
7th capacitance, has a first end and a second end, and wherein first end is coupled to reference ground, and second end is coupled to the 8th resistance
Second fixing end and adjustable end；
Square wave chip has eight pins, wherein the first pin is coupled to reference ground, second pin and the 6th pin are coupled to the
The adjustable end of eight resistance, the 4th pin and the 8th pin are coupled to DC power supply, and the 7th pin is coupled to the first of the 8th resistance
Fixing end；
6th capacitance, has a first end and a second end, and wherein first end is coupled to the 5th pin of square wave chip, second end coupling
In reference ground；And
Thirteenth resistor has the first fixing end, the second fixing end and adjustable end, wherein the first fixing end is coupled to square wave chip
Third pin, the second fixing end is coupled to reference ground, and adjustable end exports square-wave signal；
Wherein filter circuit includes the first rank filter circuit and second-order filter circuit, and the first rank filter circuit includes：
5th capacitance, has a first end and a second end, and wherein first end receives square-wave signal；
9th capacitance, has a first end and a second end, and wherein first end is coupled to the second end of the 5th capacitance, and second end is coupled to
Reference ground；And
Twelfth resistor has a first end and a second end, and wherein first end is coupled to the second end and the 9th capacitance of the 5th capacitance
First end, second end export first-order filtering signal；And
Second-order filter circuit includes：
Eleventh resistor has a first end and a second end, and wherein first end receives first-order filtering signal, and second end exports triangular wave
Signal；And
8th capacitance, has a first end and a second end, and wherein first end is coupled to the first end of eleventh resistor, second end coupling
In reference ground；
Wherein integrating amplification circuit includes：
There is second triode base stage, collector and emitter, wherein base stage to receive triangular signal, and emitter is coupled to ginseng
Ground is examined, collector exports integrated signal；
6th resistance is coupled between DC power supply and the base stage of the second triode；And
4th capacitance and the tenth resistance, coupled in parallel is between the base stage and collector of the second triode；And
Wherein common emitter amplifying circuit includes：
There is first triode base stage, collector and emitter, wherein base stage to receive integrated signal, and collector is coupled to direct current
Power supply；
3rd resistor is coupled between the base stage and DC power supply of the first triode；
7th resistance, has a first end and a second end, and wherein first end is coupled to the emitter of the first triode, second end coupling
In reference ground；And
Third capacitance, has a first end and a second end, and wherein first end is coupled to the emitter of the first triode, second end output
Reference signal.
4. as described in claim 1 for the load faulty of power supply system detection protection circuit, wherein test signal generates electricity
Road includes the 9th resistance, and the 9th resistance has first end and second end, and wherein first end is coupled to the second relay second switch
Normal-closed end, second end are coupled to reference ground.
5. as described in claim 1 for the load faulty of power supply system detection protection circuit, wherein amplitude detection circuit packet
It includes：
7th diode has anode and cathode；
First amplifier has first input end, the second input terminal and output end, wherein the first input receives test signal, the
Two input terminals are coupled to the anode of its output end and the 7th diode；
There is second amplifier first input end, the second input terminal and output end, wherein first input end to be coupled to the seven or two pole
The cathode of pipe, the second input terminal are coupled to its output end and in output end output amplitude signals；And
Tenth capacitance and the 23rd resistance, coupled in parallel is between the first input end and reference ground of the second amplifier.
6. as described in claim 1 for the load faulty of power supply system detection protection circuit, wherein logic judging circuit packet
It includes：
There is first comparator first input end, the second input terminal and output end, wherein first input end to receive amplitude signal,
Second input terminal receives first threshold voltage；
There is first diode anode and cathode, Anodic to be coupled to the output end of first comparator, cathode output instruction letter
Number；
There is second comparator first input end, the second input terminal and output end, wherein first input end to receive second threshold electricity
Pressure, the second input terminal receive amplitude signal；
There is second diode anode and cathode, Anodic to be coupled to the output end of the second comparator, cathode output instruction letter
Number；
There is third comparator first input end, the second input terminal and output end, wherein first input end to receive third with reference to electricity
Pressure, the second input terminal receive indication signal, and output end exports first control signal；And
There is 4th comparator first input end, the second input terminal and output end, wherein first input end to receive indication signal,
Second input terminal receives third reference voltage, and output end exports second control signal.
7. as described in claim 1 for the load faulty of power supply system detection protection circuit, wherein warning circuit includes：
18th resistance, has a first end and a second end, and wherein first end receives second control signal；
19th resistance, has a first end and a second end, and wherein first end is coupled to the second end of the 18th resistance, second end coupling
It is connected to reference ground；
Third transistor has base stage, and collector and emitter, wherein base stage are coupled to the second end and the tenth of the 18th resistance
The first end of nine resistance, collector are coupled to DC power supply；
14th resistance, has a first end and a second end, and wherein first end is coupled to the emitter of third transistor；
15th resistance, has a first end and a second end, and wherein first end is coupled to reference ground；
There is 4th thyristor anode, cathode and control pole, wherein control pole to be coupled to the second end of the 14th resistance, cathode
It is coupled to the second end of the 15th resistance；And
First buzzer and the 4th diode, coupled in parallel is between DC power supply and the anode of the 4th thyristor.
Further include relay control electricity 8. as described in claim 1 for the load faulty of power supply system detection protection circuit
Road, control relay circuit include first control circuit and second control circuit, and wherein first control circuit receives the first control
Signal generates the first relay signal to control the first relay and third relay, and second control circuit receives the first control letter
Number generate the second relay signal to control the second relay.
9. as claimed in claim 8 for the load faulty of power supply system detection protection circuit, wherein first control circuit packet
It includes：
26th resistance, has a first end and a second end, and wherein first end receives first control signal；
25th resistance, has a first end and a second end, and wherein first end is coupled to the second end of the 26th resistance, and second
End is coupled to reference ground；
8th triode has base stage, and collector and emitter, wherein base stage are coupled to the 25th resistance first end and second
The second end of 16 resistance, collector are coupled to DC power supply；
24th resistance, has a first end and a second end, and wherein first end is coupled to the emitter of the 8th triode；And
There is 7th thyristor anode, cathode and control pole, wherein control pole to be coupled to the second end of the 24th resistance, cloudy
Pole is coupled to reference ground, and anode exports the first relay signal；And
Second control circuit includes：
20th resistance, has a first end and a second end, and wherein first end receives first control signal；
21st resistance, has a first end and a second end, and wherein first end is coupled to the second end of the 20th resistance, second end
It is coupled to reference ground；
5th triode has base stage, and collector and emitter, wherein base stage are coupled to the second end and second of the 20th resistance
The first end of 11 resistance, collector are coupled to DC power supply；
16th resistance, has a first end and a second end, and wherein first end is coupled to the emitter of the 5th triode；And
There is 6th thyristor anode, cathode and control pole, wherein control pole to be coupled to the second end of the 16th resistance, cathode
It is coupled to reference ground, anode exports the second relay signal.
10. a kind of method for detecting the load faulty of power supply system, power supply system includes power supply, the first relay,
Second relay, third relay and capacitive load, wherein power supply and capacitive load all have first end and second end, institute
The method of stating includes：
It generates reference signal and is input to the first end of capacitive load, the reference signal is generated in the second end of capacitive load and surveyed
Trial signal；
It detects the amplitude of test signal and generates amplitude signal with the amplitude of characterization test signal；
By amplitude signal and first threshold voltage, second threshold voltage, which is compared, generates first control signal and the second control letter
Number；
Wherein first control signal is used for controlling the first relay, the second relay and third relay, second control signal
In control warning circuit.
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| CN108400570B (en) | 2023-08-25 |
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