CN108399937B

CN108399937B - Automatic repair circuit of memory

Info

Publication number: CN108399937B
Application number: CN201710066123.9A
Authority: CN
Inventors: 姚泽华; 陈懿范
Original assignee: Elite Semiconductor Memory Technology Inc
Current assignee: Elite Semiconductor Memory Technology Inc
Priority date: 2017-02-06
Filing date: 2017-02-06
Publication date: 2021-06-04
Anticipated expiration: 2037-02-06
Also published as: CN108399937A

Abstract

The automatic repair circuit of the memory comprises a decoding circuit, a latch enabling circuit and a first latch circuit. The decoding circuit is used for comparing a first input address with a plurality of bad addresses so as to generate a control signal. The latch enable circuit is used for selectively generating a first enable signal at least according to the control signal. The first latch circuit is used for receiving the first input address and storing the first input address after receiving the first enabling signal. When the control signal indicates that the first input address is the same as one of the bad addresses, the latch enabling circuit prevents the enabling signal from being transmitted to the first latch circuit.

Description

Automatic repair circuit of memory

Technical Field

The invention relates to an automatic repair circuit of a memory.

Background

The testing of memory elements typically has two stages: bare Chip Test (Chip bonding, CP) and Final Test (Final Test, FT). The former is to detect the crystal grain on the chip by the way of needle test, and the latter is to perform the electrical test again for the finished product after packaging. In a test process, when a word line corresponding to an input address is found to be defective, a redundant word line is usually selected to replace the defective word line. When a word line corresponding to a particular address is found to be defective, there is a possibility that two redundant word lines correspond to the particular address in two different test stages, and the problem of duplicate selection occurs. At the final test stage, the problem of repeated selection may also occur. Therefore, it is necessary to provide a circuit such that a specific address can only access a normal word line or a redundant word line.

Disclosure of Invention

An embodiment of an automatic repair circuit for a memory according to the present invention includes a decoding circuit, a latch enable circuit and a first latch circuit. The decoding circuit is used for comparing a first input address with a plurality of bad addresses so as to generate a control signal. The latch enable circuit is used for selectively generating a first enable signal at least according to the control signal. The first latch circuit is used for receiving the first input address and storing the first input address after receiving the first enabling signal. When the control signal indicates that the first input address is the same as one of the bad addresses, the latch enabling circuit prevents the enabling signal from being transmitted to the first latch circuit.

Drawings

FIG. 1 is a block diagram of an automatic repair circuit of a memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an automatic repair circuit of a memory according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an automatic repair circuit of a memory according to a third embodiment of the present invention.

FIG. 4 is a block diagram of an automatic repair circuit of a memory according to a fourth embodiment of the present invention.

[ notation ] to show

100 memory automatic repair circuit

101 decoding circuit

102 inspection circuit

103 latch enable circuit

104 latch circuit

105E type fuse circuit

200 memory automatic repair circuit

201 decoding circuit

202 inspection circuit

203 latch enable circuit

204_1, 204_2 latch circuit

205_1, 205_ 2E type fuse circuit

206 comparison circuit

300 memory automatic repair circuit

301 decoding circuit

302 checking circuit

303 latch enable circuit

304_1, 304_2 latch circuit

305_1, 305_ 2E type fuse circuit

306 comparison circuit

400 memory automatic repair circuit

401 decoding circuit

402 checking circuit

403 latch enabling circuit

404_1, 404_2 latch circuit

405_1, 405_ 2E type fuse circuit

406 comparison circuit

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This description and the appended claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is used herein to encompass any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

FIG. 1 is a block diagram of an automatic repair circuit of a memory according to a first embodiment of the present invention. Referring to fig. 1, the automatic repair circuit 100 includes a decoding circuit 101, a checking circuit 102, a latch enable circuit 103, a latch circuit 104 and an E-type fuse circuit 105.

The decoding circuit 101 is configured to receive an input address (e.g., the input address a1 of fig. 1) and perform decoding according to whether the input address a1 is the same as one of the bad addresses FAm-FAn. When the input address a1 is the same as one of the bad addresses FAm-FAn, the decoding circuit 101 selects a redundant word line previously assigned to the bad address instead of a normal word line. These defective addresses FAm through FAn are usually stored in a plurality of E-type fuse circuits. For simplicity, only one E-type fuse circuit 105 is shown in this embodiment.

Referring to fig. 1, when the input address a1 is identical to one of the bad addresses FAm-FAn, the decoding circuit 101 generates a control signal CS. The check circuit 102 receives and checks the input address a1 to determine whether the input address a1 corresponds to a word line having a defect. The check circuit 102 generates a check result IR to the latch enable circuit 103. In the present embodiment, the check circuit 102 is located in the automatic memory repair circuit 100. In other embodiments, however, the check circuit 102 is external to the memory auto-repair circuit 100. The checking circuit 102 may be in various forms of hardware, software, or firmware.

The latch enable circuit 103 is configured to selectively generate an enable signal EN1 according to the control signal CS and the check result IR. When the control signal CS is asserted, indicating that the input address a1 is identical to one of the bad addresses FAm-FAn, the latch enable circuit 103 prevents the enable signal EN1 from being transmitted to the latch circuit 104. When the check result IR is generated, indicating that the input address a1 does not correspond to a word line with defects, the latch enable circuit 103 prevents the enable signal EN1 from being transmitted to the latch circuit 104. In other cases, the enable signal EN1 is sent from the latch enable circuit 103 to the latch circuit 104. The latch circuit 104 is configured to receive the input address a1 and store the input address a1 to the E-fuse circuit 105 as a bad address FA1 after receiving the enable signal EN 1. When the bad address FA1 is stored by the E-fuse circuit 105, the decoding circuit 101 compares the input address A1 with the defective address FA1 after receiving the input address A1. Since both are the same, the decoding circuit 101 selects a redundancy word line RWL1 corresponding to the defect address FA1 to be turned on.

Further, the automatic repair circuit 100 has three conditions during operation. In the first situation, when the input address A1 is different from one of the bad addresses FAm-FAn, and the check result IR indicates that the input address A1 does not correspond to a word line having a defect, the latch enable circuit 103 prevents the enable signal EN1 from being transmitted to the latch circuit 104. Therefore, the latch circuit 104 does not store the input address a1 as a bad address. The decoding circuit 101 decodes the input address a1 and accesses a normal word line WL1 corresponding to the input address a 1. In the second situation, when the input address a1 is identical to one of the bad addresses FAm-FAn, the control signal CS is generated to the latch enable circuit 103, such that the enable signal EN1 is not transmitted to the latch circuit 104. Therefore, the latch circuit 104 does not store the input address a 1. The decoding circuit 101, upon receiving the input address a1 for decoding, selects a redundant word line previously assigned to the bad address. In a third situation, when the input address A1 is different from one of the bad addresses FAm FAn, and the checking result IR indicates that the input address A1 corresponds to a word line having a defect, the latch enable circuit 103 generates the enable signal EN1 to the latch circuit 104. Therefore, the latch circuit 104 stores the input address a1 to the E-type fuse circuit 105 as a bad address FA 1. The decoding circuit 101 receives the input address a1 and then selects the redundancy word line RWL1 corresponding to the bad address FA1 to be turned on.

FIG. 2 is a block diagram of an automatic repair circuit 200 for a memory according to a second embodiment of the present invention. Referring to fig. 2, the automatic repair circuit 200 includes a decoding circuit 201, a checking circuit 202, a latch enable circuit 203, two latch circuits 204_1 and 204_2, two E-type fuse circuits 205_1 and 205_2, and a comparison circuit 206.

In the present embodiment, the input address A1 has been stored in the latch circuit 204_1 according to the enable signal EN1, so the defective address FA1 is stored by the E-type fuse circuit 205_ 1. The decoding circuit 201 is configured to receive an input address (e.g., the input address a2 of fig. 2) and perform decoding according to whether the input address a2 is the same as one of the bad addresses FAm-FAn. When the input address A2 is the same as one of the bad addresses FAm-FAn, the decoding circuit 201 selects a redundant word line previously assigned to the bad address.

In addition, when the input address a2 is identical to one of the bad addresses FAm-FAn, the decoding circuit 201 generates the control signal CS. The check circuit 202 receives and checks the input address a2 to determine whether the input address a2 corresponds to a word line having a defect. The check circuit 202 generates the check result IR to the latch enable circuit 203.

The comparing circuit 206 is used for comparing the input address a1 with the input address a2 to generate a comparison signal COM. The latch enable circuit 203 is configured to selectively generate an enable signal EN2 according to the control signal CS, the check result IR and the comparison signal COM. When the control signal CS is asserted, indicating that the input address a2 is identical to one of the bad addresses FAm-FAn, the latch enable circuit 203 prevents the enable signal EN2 from being asserted. When the check result IR is generated, indicating that the input address a2 does not correspond to a word line having a defect, the latch enable circuit 203 prevents the enable signal EN2 from being transmitted. When the comparison circuit 260 compares the input address A2 and finds the same address A1 previously stored in the latch circuit 204_1, the latch enable circuit 203 prevents the enabling signal EN2 from being transmitted. In other cases, the enable signal EN2 is sent from the latch enable circuit 203 to the latch circuit 204_ 2. After receiving the input address a2, the latch circuit 204_2 stores the input address a2 to the E-fuse circuit 205_2 as a bad address FA2 according to the enable signal EN 2. After the bad address FA2 is stored in the E-fuse circuit 205_2, after the decoding circuit 201 receives the input address a2, if the input address a2 is the same as the bad address FA2, the decoding circuit 201 selects a redundant word line RWL2 corresponding to the bad address FA2 to be turned on.

Further, the automatic repair circuit 200 has four conditions during operation. In the first situation, when the comparison signal COM indicates that the input address a2 is different from the input address a1, the input address a2 is different from one of the bad addresses FAm-FAn, and the check result IR indicates that the input address a2 does not correspond to a word line having a defect, the latch enable circuit 203 prevents the enable signal EN2 from being transmitted to the latch circuit 204_ 2. Therefore, the latch circuit 204_2 does not store the input address a2 as a bad address. The decoding circuit 201 decodes the input address a2 and accesses a normal word line WL2 corresponding to the input address a 2. In the second situation, when the comparison signal COM indicates that the input address a2 is different from the input address a1 and the input address a2 is the same as one of the bad addresses FAm-FAn, the control signal CS is generated to the latch enable circuit 203 such that the enable signal EN2 is not transmitted to the latch circuit 204_ 2. Therefore, the latch circuit 204_2 does not store the input address a2 as a bad address. The decoding circuit 201 receives the input address a2 for decoding, and selects a redundant word line previously assigned to the bad address. In a third situation, when the comparison signal COM indicates that the input address a2 is different from the input address a1, the input address a2 is different from one of the bad addresses FAm-FAn, and the check result IR indicates that the input address a2 corresponds to a word line with a defect, the latch enable circuit 203 generates the enable signal EN2 to the latch circuit 204_ 2. Therefore, the latch circuit 204_2 stores the input address A2 to the E-type fuse circuit 205_2 as a defective address FA 2. The decoding circuit 201 receives the input address a2 and then selects the redundant word line RWL2 corresponding to the defective address FA2 to be turned on. In the last case, when the comparison signal COM indicates that the input address A2 is the same as the input address A1, the latch enable circuit 203 does not generate the enable signal EN2 to the latch circuit 204_ 2. Therefore, the latch circuit 204_2 does not store the input address a 2. The decoding circuit 201 receives the input address a2 and then selects the redundancy word line RWL1 corresponding to the bad address FA1 to be turned on. With the control signal CS and the comparison signal COM, the decoding circuit 201 only accesses a normal word line or a redundant word line according to an input address.

FIG. 3 is a block diagram of an automatic repair circuit of a memory according to a third embodiment of the present invention. Referring to fig. 3, the automatic repair circuit 300 includes a decoding circuit 301, a checking circuit 302, a latch enable circuit 303, two latch circuits 304_1 and 304_2, two E-type fuse circuits 305_1 and 305_2, and a comparison circuit 306. The operation principle of the checking circuit 302, the latch enable circuit 303, the latch circuits 304_1 and 304_2, the E-type fuse circuits 305_1 and 305_2, and the comparing circuit 306 is the same as that of the embodiment shown in fig. 2. The difference between the second embodiment and the third embodiment is that when the input address A1 is stored in the E-fuse circuit 305_1 as the bad address FA1, the E-fuse circuit 305_1 generates a blowing signal B1 to the latch circuit 304_ 1. When the fuse signal B1 is received by the latch circuit 304_1, the latch circuit 304_1 will not store any more input addresses. Similarly, when the input address A2 is stored in the E-fuse circuit 305_2 as the bad address FA2, the E-fuse circuit 305_2 generates a blowing signal B2 to the latch circuit 304_ 2. When the fuse signal B2 is received by the latch circuit 304_2, the latch circuit 304_2 will not store any more input addresses.

Then, after the power of the automatic memory repair circuit 300 is interrupted and the power is restored, if the E-fuse circuits 305_1 and 305_2 have stored the defective addresses FA1 and FA2 by the blowing signals B1 and B2, the latch circuits 304_1 and 304_2 will not store any more input addresses, thereby avoiding the problem of repeated selection.

FIG. 4 is a block diagram of an automatic repair circuit 400 for a memory according to a fourth embodiment of the present invention. Referring to fig. 4, the automatic repair circuit 400 includes a decoding circuit 401, a checking circuit 402, a latch enable circuit 403, two latch circuits 404_1 and 404_2, two E-type fuse circuits 405_1 and 405_2, and a comparison circuit 406. The operation principle of the decoding circuit 401, the checking circuit 402, the latch enable circuit 403, the latch circuits 404_1 and 404_2, the E-type fuse circuits 405_1 and 405_2, and the comparison circuit 406 is the same as that of the embodiment shown in fig. 2 and 3. The difference between the fourth embodiment and the former embodiment is that the latch circuits 404_1 and 404_2 are used for storing a specific address, such as the specific addresses SA1 and SA2 shown in FIG. 4, instead of storing the input addresses A1 and A2. Referring to FIG. 4, after the latch enable circuit 403 receives an Active Command (ACT) and test mode commands RT1/RT2, the memory automatic repair circuit 400 enters a specific test mode. During a specific test mode, the latch enable circuit 403 ignores the check result IR and the comparison signal COM, generates the enable signal EN1 in response to the test mode command RT1 and generates the enable signal EN2 in response to the test mode command RT 2. Then, the latch circuit 404_1 stores the address SA1 specified by the active command ACT when the enable signal EN1 is asserted, and the latch circuit 404_2 stores the address SA2 specified by the active command ACT instead of the bad address when the enable signal EN2 is asserted.

In the above embodiments, the addresses received by the decoding circuit, the checking circuit, the latching circuit and the comparing circuit in fig. 1 to 4 are row addresses (row addresses), and the decoding circuit only selects a normal word line or a redundant word line to be turned on according to the row addresses. However, the present invention should not be limited thereto. The decoding circuit, the checking circuit, the latch circuit and the comparison circuit can receive a column address, and the decoding circuit can access a normal bit line or a redundant bit line to be opened according to the column address. By generating the control signal CS, the comparison signal COM and the check result IR, the automatic repair circuit of the memory disclosed in the present invention can avoid the problem of repeated selection.

While the technical content and the technical features of the invention have been disclosed, those skilled in the art can make various substitutions and modifications based on the teaching and the disclosure of the invention without departing from the spirit of the invention. Accordingly, the scope of the present invention should not be limited to the embodiments disclosed, but should include various alternatives and modifications without departing from the invention, which are encompassed by the appended claims.

Claims

1. A memory auto-repair circuit comprising:

a decoding circuit for comparing the first input address with a plurality of bad addresses to generate a control signal;

the latch enabling circuit is used for selectively generating a first enabling signal at least according to the control signal; and

a first latch circuit for receiving the first input address and storing the first input address after receiving the first enable signal;

wherein, when the control signal indicates that one of the first input address and the bad address is the same, the latch enabling circuit prevents the enabling signal from being transmitted to the first latch circuit,

when the control signal indicates that the first input address is the same as one of the bad addresses, the first latch circuit does not store the first input address, and when the decoding circuit decodes the first input address, the decoding circuit accesses the redundant word line corresponding to the one of the bad addresses.

2. The memory auto-repair circuit of claim 1, further comprising:

a comparison circuit for comparing the first input address with the second input address to generate a comparison signal to the latch enable circuit;

when the comparison signal indicates that the first input address is different from the second input address, the latch enabling circuit generates a second enabling signal.

3. The memory auto-repair circuit of claim 2, further comprising:

a second latch circuit for receiving the second input address after the first input address is stored by the first latch circuit, and storing the second input address after the second enable signal is received by the second latch circuit.

4. The memory auto-repair circuit of claim 3, further comprising:

a first E-type fuse circuit, wherein the first latch circuit stores the first input address and transmits the first input address to the first E-type fuse circuit as a first bad address after the first enable signal is received by the first latch circuit; and

and a second E-type fuse circuit, wherein when the second enable signal is received by the second latch circuit, the second latch circuit stores the second input address and transmits the second input address to the second E-type fuse circuit as a second bad address.

5. The automatic repair circuit of claim 4, wherein the first E-type fuse circuit generates a first blowing signal to the first latch circuit when the first E-type fuse circuit stores the first input address as the first bad address, and the second E-type fuse circuit generates a second blowing signal to the second latch circuit when the second E-type fuse circuit stores the second input address as the second bad address.

6. The automatic repair circuit of claim 5, wherein the first latch circuit does not store any input address when the first latch circuit receives the first blowing signal, and the second latch circuit does not store any input address when the second latch circuit receives the second blowing signal.

7. The automatic repair circuit of claim 2, wherein the latch enable circuit generates the first enable signal ignoring the comparison signal after the latch enable circuit receives the active command and the test mode command, and the first latch circuit stores a third address designated by the active command when the first enable signal is generated.

8. The memory auto-repair circuit of claim 1, further comprising:

a checking circuit for receiving and checking the first input address to determine whether the first input address corresponds to a word line having a defect;

when the control signal indicates that the first input address and one of the bad addresses are different and the check circuit determines that the first input address does not correspond to the word line with the defect, the first latch circuit does not store the first input address, and the decoding circuit decodes the first input address and then accesses a normal word line corresponding to the first input address.