CN108398302B

CN108398302B - Microstructure sample preparation method

Info

Publication number: CN108398302B
Application number: CN201810134165.6A
Authority: CN
Inventors: 张雨田
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-02-09
Filing date: 2018-02-09
Publication date: 2021-04-02
Anticipated expiration: 2038-02-09
Also published as: CN108398302A

Abstract

The invention discloses a microstructure sample preparation method, which comprises the following steps: firstly, polishing a chip sample until a contact hole layer is exposed; secondly, heating hydrogen peroxide to remove the metal tungsten in the contact hole layer; thirdly, removing the interlayer medium; fourthly, drilling two deep holes in the back of the target floating gate and the control gate; fifthly, etching silicon nitride above the target floating gate and the control gate, and drilling a deep hole on the target floating gate and the control gate; sixthly, covering the target floating gate and the control gate by using platinum, cutting off and isolating the target control gate and the whole control gate after covering is finished, and removing all other structures; and seventhly, observing the exposed sharp corner of the floating gate. The invention fixes the floating gate to be observed on the surface of a sample, removes the rest unnecessary parts, and uses a method of depositing platinum after punching to fix the structure which is originally corroded and separated so as to reserve the structure for observation.

Description

Microstructure sample preparation method

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a microstructure sample preparation method.

Background

In the process of preparing a semiconductor integrated circuit sample, the process of micro-analysis of materials and the process of observing any microstructure, such as the Tip (sharp angle) structure of Floating gate of an E-flash chip, the observation technology which can be used currently is to cut a piece of sample by FIB, wherein the sample comprises a target Floating gate and a plurality of non-target Floating gates, and the sample is put into a TEM to be observed in a transmission mode. As shown in FIG. 1, the sample prepared by the above method has a depth of about 0.4 μm in total in the sharp angle as viewed from the direction of the drawing, and the sharp angle cannot be fully observed in the whole depth range.

If the remaining surrounding structures are removed by chemical means and then viewed, the structure to be viewed is also removed at the same time.

Therefore, the above methods cannot perfectly solve the problem of sample preparation in chip microstructure analysis, and cannot completely observe sharp corners in the microstructure.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a microstructure sample preparation method, which can observe the complete sharp angle of a floating gate.

In order to solve the above problems, the microstructure sample preparation method according to the present invention includes:

firstly, polishing a chip sample until a contact hole layer is exposed;

secondly, heating hydrogen peroxide to remove the metal tungsten in the contact hole layer;

thirdly, removing the interlayer medium;

fourthly, drilling two deep holes in the back of the target floating gate and the control gate;

fifthly, etching silicon nitride above the target floating gate and the control gate, and drilling a deep hole on the target floating gate and the control gate;

sixthly, driving platinum plating on the target to cover by using an e-beam electron beam driving sputtering method, cutting off and isolating the target control grid from the whole control grid after the covering is finished, and removing all other structures;

and seventhly, observing the exposed sharp corner of the floating gate.

Furthermore, in the third step, hydrofluoric acid with the concentration of 10-49% by volume is used for removing the interlayer medium.

Further, in the fourth step, holes are drilled in the back of the target floating gate and the control gate by using a focused ion beam method.

Further, in the fourth step, the size of the drilled hole ranges from 0.2 μm × 0.2 μm to 0.6 μm × 0.6 μm, and the depth of the drilled hole is 3 ± 1 μm.

Further, in the fifth step, a focused ion beam method is adopted to etch the target floating gate and the silicon nitride above the control gate.

Further, in the fifth step, the size of the drilled hole ranges from 0.1 μm × 0.1 μm to 0.5 μm × 0.5 μm, and the depth of the drilled hole is 3 ± 1 μm.

Further, in the sixth step, all the rest of the structure is removed by hydrofluoric acid.

The microstructure sample preparation method fixes the floating gate to be observed on the surface of a sample, removes the rest unnecessary parts, and uses a method of depositing platinum after punching to fix the structure which is originally corroded and separated so as to reserve the structure for observation.

Drawings

FIG. 1 is a microscopic view of a sharp-angled section of E-Flash.

FIG. 2 is a schematic diagram of the floating gate structure of E-Flash.

FIG. 3 is a flow chart of a sample preparation method of the present invention.

Detailed Description

The microstructure sample preparation method of the invention is directed at the semiconductor integrated circuit sample preparation process, the material micro-analysis process and the observation process for any microstructure, and comprises the following steps:

firstly, polishing a chip sample until a contact hole layer is exposed.

And secondly, heating by using hydrogen peroxide to remove the metal tungsten in the contact hole layer.

And thirdly, removing the interlayer medium by using hydrofluoric acid with the concentration of 10-49% by volume.

And fourthly, drilling two deep holes on the back of the target floating gate and the control gate by using a focused ion beam FIB (focused ion beam) method. The size of the drilled holes ranges from 0.2 μm to 0.6 μm 0.6. mu.m, and the depth of the drilled holes is 3. + -.1 μm.

Fifthly, etching the silicon nitride above the target floating gate and the control gate by using a focused ion beam FIB (focused ion beam) method, and drilling a deep hole on the target floating gate and the control gate, wherein the typical size range of the drilled hole is 0.1 mu m multiplied by 0.1 mu m to 0.5 mu m multiplied by 0.5 mu m, and the depth of the drilled hole is 3 +/-1 mu m.

And sixthly, driving platinum plating on the target to cover by using an e-beam electron beam driving sputtering method, cutting off and isolating the target control grid from the whole control grid after the coverage is finished, and removing all other structures by using hydrofluoric acid.

And seventhly, observing the sharp angle of the exposed floating gate after the target floating gate to be observed is completely exposed.

The key point of the method is that the method for depositing platinum is used for protecting and fixing the structure which is originally directly corroded and separated by a chemical method after drilling, and the structure to be observed can be effectively reserved, so that subsequent observation and analysis are facilitated.

The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A microstructure sample preparation method is characterized in that: comprises the following steps:

firstly, polishing a chip sample until a contact hole layer is exposed;

thirdly, removing the interlayer medium;

fourthly, drilling two deep holes in the back of the target floating gate and the control gate, wherein the size range of the drilled holes is between 0.2 mu m multiplied by 0.2 mu m and 0.6 mu m multiplied by 0.6 mu m, and the drilling depth is 3 +/-1 mu m;

fifthly, etching silicon nitride above the target floating gate and the control gate, and drilling a hole on the target floating gate and the control gate; the size range of the drilled hole is between 0.1 Mum x 0.1 Mum and 0.5 Mum x 0.5 Mum, and the drilling depth is 3 +/-1 Mum;

sixthly, covering the target floating gate and the control gate by using metal platinum, cutting off and isolating the target control gate and the whole control gate after covering is finished, and removing all other structures;

and seventhly, observing the sharp corners of the floating gate which are completely exposed.

2. The microstructure sampling method of claim 1, wherein: and in the third step, hydrofluoric acid with the concentration of 10-49% by volume is used for removing the interlayer medium.

3. The microstructure sampling method of claim 1, wherein: and in the fourth step, drilling holes in the back of the target floating gate and the control gate by adopting a focused ion beam method.

4. The microstructure sampling method of claim 1, wherein: and in the fifth step, etching the target floating gate and the silicon nitride above the control gate by adopting a focused ion beam method.

5. The microstructure sampling method of claim 1, wherein: in the sixth step, the platinum covers the target floating gate and the control gate by an electron beam driving sputtering method; all remaining structures were removed with hydrofluoric acid.