CN108366027A - A kind of binary cycle QPSK continuous phase phase-shift keying (PSK) modulation demodulation systems and method - Google Patents
A kind of binary cycle QPSK continuous phase phase-shift keying (PSK) modulation demodulation systems and method Download PDFInfo
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- CN108366027A CN108366027A CN201810441502.6A CN201810441502A CN108366027A CN 108366027 A CN108366027 A CN 108366027A CN 201810441502 A CN201810441502 A CN 201810441502A CN 108366027 A CN108366027 A CN 108366027A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2003—Modulator circuits; Transmitter circuits for continuous phase modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
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Abstract
The invention discloses a kind of binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation systems, GPIO0 pins in MCU microprocessors update control FQUD signals as frequency, GPIO1 pins are output to DDS waveform generator blocks as control word load clock WCLK signal, MCU microprocessors carry out logic control with CCS signals to DDS waveform generator blocks, control carrier frequency, initial phase, the waveform parameter of DDS waveform generators；Advantageous effect is the phase difference of real time monitoring simulation underground continuous wave pulse data signal stream and mock standard carrier signal, with generate meet underground " 0 " to be transmitted, " 1 " digital stream time domain waveform, realize that downhole data transmits upwards, drilling liquid pressure binary cycle QPSK is modulated under identical bandwidth, and the rate of information throughput and band efficiency double；Former and later two 10 bit symbols phases are effectively prevented to interfere with each other.
Description
Technical field
The present invention relates to oil, gas drilling equipment technical fields, and wireless drilling instrument is used for more particularly to one kind
Coding techniques field about the continuous wave phase PSK Modulation Technology of drilling fluid.
Background technology
Currently, wireless drilling measuring system is all made of the transmission mode of drilling fluid pulse.With wireless drilling geologic parameter
Increase, the transmission rate of positive pulse generator is difficult to meet site requirement.Drilling liquid pressure multiple phase-shift keying (QPSK)
Continuous wave is the effective ways for further increasing the downhole data rate of information throughput.QDPSK, QPSK, MPSK drilling hydraulic at present
During power carrier wave tune signal modulation, a bit period is made of four carrier cycles, and transmission speed and bandwidth availability ratio are low.
Therefore, there is an urgent need to a kind of binary cycle drilling hydraulic Reeb signal QPSK modulation schemes in market, to improve transmission speed
Degree and bandwidth availability ratio avoid interfering with each other for 10 binary element phases, cause code error.
Invention content
The technical problem to be solved by the invention is to provide a kind of binary cycle QPSK continuous phases phase-shift keying (PSK) modulation /demodulation
System and method.
The technical solution adopted in the present invention is a kind of binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system,
Including MCU microprocessor units 10, DDS waveform generators 20, carrier signal unit 30, phase shifter element 40, continuous phase phase
Move key cell 50, low pass filter unit 60, binary cycle QPSK signal elements 70, cosine signal unit 80, low-pass filter 1
Unit 90, judging module unit 100 and data outputting unit 110；Signal modulation part is led to by the MCU microprocessors 10
It crosses DDS waveform generator blocks 20 to be connected with each other with carrier signal unit 30 and phase shifter element 40 respectively, carrier signal unit
30 are connected with each other by phase shifter element 40 and low pass filter unit 60, continuous phase phase-shift keying (PSK) unit 50 and low-pass filtering
Device unit 60 is connected with each other；Signal demodulation part is by the binary cycle QPSK model units 70 and 80 phase of cosine signal unit
The multiplied signal arrived is output to judging module unit 100, the output of judging module unit 100 by 1 unit 90 of low-pass filter
Signal passes through the original signal after the output demodulation of data outputting unit 110.
The MCU microprocessor units 10 are STM32F373CCT6 using the model of integrated circuit, and DDS waveforms occur
Device 20 is AD9854 using the model of integrated circuit.
The processing procedure of signal is as follows：
(1), the GPIO0 pins in MCU microprocessor units 10 update control FQUD signals, GPIO1 pins as frequency
It is output to DDS waveform generator blocks 20 as control word load clock WCLK signal；
(2), MCU microprocessor units 10 carry out logic control with CCS signals to DDS waveform generator blocks 20, control
Carrier frequency, initial phase, the waveform parameter of DDS waveform generator blocks 20 generate 1024 kinds of simulation continuous wave impulses in underground
Signal data stream and mock standard carrier signal are finely adjusted the mutation of binary cycle QPSK signal phases, ensure the company of signal
Continuous property；
(3), the binary cycle QPSK signals that the process (2) generates are passed through and is believed by the cosine that low-pass filter 60 generates
After number carrying out single channel coherent demodulation, pass through double weeks after the output demodulation of the low-pass filter that is designed by microprocessor unit 10
Phase QPSK signal.
It is pulse to export the demodulation mode of modulated binary cycle QPSK signals for low-pass filter in the process (3)
The thresholding decision procedure of amplitude, thresholding is divided judges that formula is with the symbol codimg logic corresponding to impulse amplitude：
0<LQPSK<=1/7, symbol bits of coded " 00 "
1/7<LQPSK<=3/7, symbol bits of coded " 01 "
3/7<LQPSK<=5/7, symbol bits of coded " 10 "
5/7<LQPSK<=1, symbol bits of coded " 11 ".
The mathematical model expression formula of binary cycle continuous wave QPSK signals generated for the process (2) is,
The invention has the advantages that carrying out logic control, control waveform hair to DDS waveform generators by using CCS
Carrier frequency, initial phase, the waveform parameter of raw device generate 1024 kinds of simulation underground continuous wave pulse data signal streams and simulation
Standard carrier signal, according to the rotor operation rate constantly adjusted, the occurring mode of apparent out of phase waveform and each phase
Between transformation rule, with generate meet underground " 0 " to be transmitted, " 1 " digital stream time domain waveform, realize downhole data transmit upwards.
The phase difference of real time monitoring simulation underground continuous wave pulse data signal stream and mock standard carrier signal, is realized for binary cycle
The mutation of QPSK signal phases is finely adjusted, and ensures the continuity of signal；QPSK relative to drilling liquid pressure is modulated, drilling hydraulic
Power binary cycle QPSK is modulated under identical bandwidth, and the rate of information throughput and band efficiency double；Drilling fluid is continuous
In the QPSK modulation of wave binary cycle, the phase for starting and terminating waveform is consistent with the phase of carrier wave in the same time, before effectively preventing
Latter two 10 bit symbols phase interferes with each other.
Description of the drawings
Fig. 1 is that the analog signal generator of binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system of the present invention is overall
Structural schematic diagram；
Fig. 2 is the demodulation principle schematic diagram of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention；
Fig. 3 is the electrical schematic diagram of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention；
Fig. 4 is the electrical schematic diagram of binary cycle QPSK continuous phases phase-shift keying (PSK) demodulating system of the present invention；
Fig. 5 is the 0110110001,0110110010 of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention,
0110110011 time-domain signal figure；
Fig. 6 is that the rotary valve speed of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention and rotary valve generate
The phase difference rad tables of comparisons；
Fig. 7 is the adjustment waveform logic of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention.
In figure：
10, MCU microprocessor units 20, DDS waveform generator blocks
30, carrier signal unit 40, phase shifter element
50, continuous phase phase-shift keying (PSK) unit 60, low pass filter unit
70, binary cycle QPSK signal elements 80, cosine signal unit
90,1 unit 100 of low-pass filter, judging module unit
110, data outputting unit 110.
Specific implementation mode
Invention is further described in detail with reference to the accompanying drawings and detailed description：
Fig. 1 is the modulation circuit schematic diagram of binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system of the present invention；Fig. 2
It is the demodulation integrated circuit AD9854 schematic diagrams of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention；Such as Fig. 1 institutes
Show, binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system of the present invention, including, MCU microprocessor units 10, DDS waves
Shape generator 20, carrier signal unit 30, phase shifter element 40, continuous phase phase-shift keying (PSK) unit 50, low pass filter unit
60, binary cycle QPSK signal elements 70, cosine signal unit 80,1 unit 90 of low-pass filter, 100 sum number of judging module unit
According to output unit 110；Signal modulation part is distinguished by DDS waveform generator blocks 20 by the MCU microprocessors 10
It is connected with each other with carrier signal unit 30 and phase shifter element 40, carrier signal unit 30 passes through phase shifter element 40 and low pass filtered
Wave device unit 60 is connected with each other, and continuous phase phase-shift keying (PSK) unit 50 is connected with each other with low pass filter unit 60；Signal demodulates
Part is the signal being multiplied with cosine signal unit 80 by the binary cycle QPSK model units 70, passes through low-pass filtering
1 unit 90 of device is output to judging module unit 100, and the output signal of judging module unit 100 passes through data outputting unit 110
Original signal after output demodulation.
The MCU microprocessor units 10 are STM32F373CCT6 using the model of integrated circuit, and DDS waveforms occur
Device 20 is AD9854 using the model of integrated circuit.
The processing procedure of signal of the present invention is as follows：
(1), the GPIO0 pins in MCU microprocessor units 10 update control FQUD signals, GPIO1 pins as frequency
It is output to DDS waveform generator blocks 20 as control word load clock WCLK signal；
(2), MCU microprocessor units 10 carry out logic control with CCS signals to DDS waveform generator blocks 20, control
Carrier frequency, initial phase, the waveform parameter of DDS waveform generator blocks 20 generate 1024 kinds of simulation continuous wave impulses in underground
Signal data stream and mock standard carrier signal are finely adjusted the mutation of binary cycle QPSK signal phases, ensure the company of signal
Continuous property；
(3), the binary cycle QPSK signals that the process (2) generates are passed through and is believed by the cosine that low-pass filter 60 generates
After number carrying out single channel coherent demodulation, pass through double weeks after the output demodulation of the low-pass filter that is designed by microprocessor unit 10
Phase QPSK signal.
It is pulse to export the demodulation mode of modulated binary cycle QPSK signals for low-pass filter in the process (3)
The thresholding decision procedure of amplitude, thresholding is divided judges that formula is with the symbol codimg logic corresponding to impulse amplitude：
0<LQPSK<=1/7, symbol bits of coded " 00 "
1/7<LQPSK<=3/7, symbol bits of coded " 01 "
3/7<LQPSK<=5/7, symbol bits of coded " 10 "
5/7<LQPSK<=1, symbol bits of coded " 11 ".
The mathematical model expression formula of binary cycle continuous wave QPSK signals generated for the process (2) is,
Fig. 3 is the electrical schematic diagram of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention；As shown in figure 3, this
Invention continuous wave drilling fluid binary cycle QPSK pulse simulations signal generator is mainly by microprocessor and DDS waveform generator hardware
It is formed with associated peripheral circuits.
MCU microprocessor units 10 use integrated circuit STM32F373CCT6 to be handled for 32- floating-point high-performance centrals
Device, dominant frequency 150MHz.There are four types of memories on piece：FLASH memory, capacity 256K, bit length 16bit, access time 36ns；
SRAM memory, capacity 34K, bit length 16bit, 0 waits for；Boot ROM memories, capacity 8K, bit length 16bit, 0 waits for；OTP
ROM memory, capacity 1K, bit length 16bit, access time 36ns.Wherein OTP ROM memories, 16K*16- SRAM memory
It is provided with corresponding password with FLASH32 storages, to protect application program.10 master integrated circuit of MCU microprocessor units
The GPIO0 pins of STM32F373CCT6 update control FQUD signals as frequency, and GPIO1 pins load clock as control word
WCLK signal.4ALVC164245 is 16 dual power supply conversion transceivers, and 74HC373 latch realizes that data latch.Pass through CCS
Logic control is carried out to AD9854, controls carrier frequency, initial phase, the waveform parameter of AD9854, generates 1024 kinds of simulation wells
Lower continuous wave pulse data signal stream and mock standard carrier signal, and monitor simulation underground continuous wave pulse number in real time
According to the phase difference of stream and mock standard carrier signal, the mutation of binary cycle QPSK signal phases is finely adjusted, ensures signal
Continuity；The binary cycle QPSK signals of generation pass through carries out single channel coherent demodulation by the cosine signal that AD9854 is generated, and finally leads to
The low-pass filter designed by STM32F373CCT6 is crossed, modulated binary cycle QPSK signals are exported.
Fig. 4 is the electrical schematic diagram of binary cycle QPSK continuous phases phase-shift keying (PSK) demodulating system of the present invention；As shown in figure 4, DDS
(Direct Digital Synthesizer, direct digital frequency synthesis technology) is a kind of emerging frequency synthesis technique.It is main
The conversion of waveform is realized by using high-speed digital-analog switch technology and ultrahigh-speed comparator.DDS waveforms occur in the present invention
Device 20 includes mainly high-speed DDS, high-performance D/A converter and high-speed comparator using integrated circuit AD9854.High-speed DDS is collection
At the cores circuit AD9854, it includes 40 bit registers, is used for processing frequency/phase control words.Frequency update control
FQUD processed and control word load clock WCLK cooperations, can complete the input of frequency/phase control word, and control integrated circuit by frequency
Rate control word exports analog waveform.Frequency/phase control word has parallel, serial two kinds of input modes, present invention selection parallel defeated
Enter mode.The decoding of analogy Principle of Communication MPSK related algorithms, drilling fluid continuous wave binary cycle QPSK signals uses impulse amplitude
Thresholding criterion, the impulse amplitude gone out according to signal reconstruction judges the corresponding coding serial number of dicode tuple.According to above-mentioned brill
Well liquid presses QPSK signal modulation rules, and the average value of the control pulsed logic level corresponding to adjacent dicode tuple is respectively 1/
7、3/7、5/7、1.If the amplitude of the rotary valve rotating speed control impulse function L (t) of reconstruct is LQPSK, thresholding divides and pulse width
The corresponding symbol codimg logic of degree judges that formula can be expressed as
0<LQPSK<=1/7, symbol bits of coded " 00 "
1/7<LQPSK<=3/7, symbol bits of coded " 01 "
3/7<LQPSK<=5/7, symbol bits of coded " 10 "
5/7<LQPSK<=1, symbol bits of coded " 11 ".
Fig. 5 is the 0110110001,0110110010 of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention,
0110110011 time-domain signal figure；As shown in figure 5, time-domain signal of the present invention is illustrated for 0110110001.Drilling fluid
Pressure wave time-domain signal is opened completely in rotor and stator, and rotor is counterclockwise rotated with the angular speed of W around axis, when
When rotational displacement increment is 2 π, it is the startup waveform that f phases are 0 with reference wave difference, transmission to generate 1 complete frequency
“01”。
Rotor is with 3W/4 rates, rotation 8 π/3Ws (rotating 2 π angular displacements), generates an adjustment wave, then, rotor after
The continuous angular speed with W is counterclockwise rotated around axis；Rotor rotates 4 π/W s times (rotating 2 π angular displacements) with w/2 rates,
An adjustment wave is generated, then, rotor continues counterclockwise to rotate around axis with the angular speed of W, transmits " 11 ".
Rotor generates an adjustment wave, then, rotor with w/4 rates, rotation 8 π/Ws times (rotating 2 π angular displacements)
Continue counterclockwise to rotate around axis with the angular speed of W；It transmits " 00 ".
Rotor is with W rates, rotation 2 π/Ws times (rotating 2 π angular displacements), generates an adjustment wave, then, rotor after
The continuous angular speed with W is counterclockwise rotated around axis；It transmits " 01 ".
Rotor is with 3W/4 rates, rotation 8 π/3Ws (rotating 2 π angular displacements), generates an adjustment wave, then, rotor after
The continuous angular speed with W is counterclockwise rotated around axis.According to coherent demodulation theory, by drilling fluid binary cycle QSPSK signals and together
Step signal C (t)=2sin (w*t) is multiplied obtained signal by low-pass filter, filters out high fdrequency component and show that zero-frequency phase is defeated
Go out modulated signal, the phase output signal of zero-frequency modulation is not belonging to continuous monotonic function, and negating the phase obtained after cosine is more than
The codomain [- π, π] of inverse cosine function, causes phase identification error.It is obtained by calculus principle, Phase-shift function is reconstructed
To following formula,
In formula,The phase for entering zero-frequency spectrum modulation signal for multiple-frequency modulation signal is equivalent, and rad Ts adopt for signal
Sample period, s；N is sample ordinal number；M is sample number.
According to rotary valve control logic, the first rotary valve signal phase is constant, intermediate 10 binary numbers randomly generated
The phase summation of gained determines for following formula after word modulation：
N1+n2+n3+n4=5
In formula：N1 is 00 phase difference generated；N2 is 01 phase difference generated；N3 is 10 phase differences generated；N4 is 11
The phase difference of generation；Δ θ is the sum of the phase difference of 10 random binary numbers.
It is analyzed according to rotary valve control logic, 10 random digits generate altogether 210=1024 kinds of combinations, according to 1024
The statistical analysis of kind combination, the value that the phase difference of Δ θ generations is total is discrete fixed-value, is 2k π ± π/4,2k π ± 3 π/4,2k π
± 7 π/4 ± 5 π/4,2k π.Last two adjustment wave logic, the final phase difference obtained is modulated according to preceding 10 bit binary number
It is adjusted.
Fig. 6 is that the rotary valve speed of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention and rotary valve generate
The phase difference rad tables of comparisons, as shown in fig. 6, the four kinds of basic phase-shift keying (PSK)s generated control waveform, system is according to basic control wave
Shape, modulates the binary digit stream of different " 0 ", " 1 ", and control DDS completes system coding work.
Fig. 7 is the adjustment waveform logic table of binary cycle QPSK continuous phases phase-shift keying (PSK) modulating system of the present invention, adjusts wave
In logic such as Fig. 7 shown in list, waveform logic table is adjusted, is directly stored in the FLASH of DDS, by real-time to 10 bit symbols
The detection and calculating of waveform phase, compare the logical table in FLASH, and control DDS exports respective waveforms, ensures the end of 10 bit symbols
Tail phase is consistent with carrier phase.
The present invention carries out logic control by using CCS to DDS waveform generators, controls the carrier frequency of waveform generator
Rate, initial phase, waveform parameter generate the continuous wave impulse de signal data streams in 1024 kinds of simulation undergrounds and mock standard carrier wave letter
Number, according to the rotor operation rate constantly adjusted, the occurring mode of apparent out of phase waveform and each phasetophase transformation rule,
With generate meet underground " 0 " to be transmitted, " 1 " digital stream time domain waveform, realize downhole data transmit upwards.Real time monitoring simulation
The phase difference of underground continuous wave pulse data signal stream and mock standard carrier signal is realized for binary cycle QPSK signal phases
Mutation is finely adjusted, and ensures the continuity of signal；QPSK relative to drilling liquid pressure is modulated, drilling liquid pressure binary cycle QPSK
It is modulated under identical bandwidth, the rate of information throughput and band efficiency double；Drilling fluid continuous wave binary cycle QPSK
In modulation, the phase for starting and terminating waveform is consistent with the phase of carrier wave in the same time, effectively prevents former and later two 10 codes
First phase interferes with each other.
Claims (5)
1. a kind of binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system, which is characterized in that including MCU microprocessors
Unit（10）, DDS waveform generators（20）, carrier signal unit（30）, phase shifter element（40）, continuous phase phase-shift keying (PSK) list
Member（50）, low pass filter unit（60）, binary cycle QPSK signal elements（70）, cosine signal unit（80）, low-pass filter 1
Unit（90）, judging module unit（100）And data outputting unit（110）；Signal modulation part is by the MCU microprocessors
Device（10）Pass through DDS waveform generator blocks（20）Respectively with carrier signal unit（30）And phase shifter element（40）Mutually interconnect
It connects, carrier signal unit（30）Pass through phase shifter element（40）With low pass filter unit（60）It is connected with each other, continuous phase phase
Move key cell（50 and low pass filter unit（60 are connected with each other；Signal demodulation part is by the binary cycle QPSK models
Unit（70）With cosine signal unit（80）Be multiplied obtained signal, passes through low-pass filter Unit 1（90 are output to judging module
Unit（100）, judging module unit（100）Output signal, pass through data outputting unit（110）Former letter after output demodulation
Number.
2. binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system according to claim 1, which is characterized in that institute
The MCU microprocessor units stated（10）Model using integrated circuit is STM32F373CCT6, DDS waveform generators（20）It adopts
It is AD9854 with the model of integrated circuit.
3. the method for realizing binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system described in claim 1, feature
It is, the processing procedure of signal is as follows：
（1）, MCU microprocessor units（10）In GPIO0 pins update control FQUD signals as frequency, GPIO1 draws
Foot is output to DDS waveform generator blocks as control word load clock WCLK signals（20）；
（2）, MCU microprocessor units 10 with CCS signals to DDS waveform generator blocks（20）Logic control is carried out, DDS is controlled
Waveform generator block（20）Carrier frequency, initial phase, waveform parameter, generate the 1024 kinds of continuous wave impulses in simulation undergrounds letters
Number stream and mock standard carrier signal are finely adjusted the mutation of binary cycle QPSK signal phases, ensure the continuous of signal
Property；
（3）, for the process（2）The binary cycle QPSK signals of generation pass through by low-pass filter（60）The cosine signal of generation
After carrying out single channel coherent demodulation, by by microprocessor unit（10）Double weeks after the low-pass filter output demodulation designed
Phase QPSK signal.
4. the method for binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system according to claim 3, feature
It is, for the process（3）The demodulation mode that middle low-pass filter exports modulated binary cycle QPSK signals is pulse width
The thresholding decision procedure of degree, thresholding is divided judges that formula is with the symbol codimg logic corresponding to impulse amplitude：
0 <LQPSK<=1/7, symbol bits of coded " 00 "
1/7<LQPSK<=3/7, symbol bits of coded " 01 "
3/7<LQPSK<=5/7, symbol bits of coded " 10 "
5/7<LQPSK<=1, symbol bits of coded " 11 ".
5. the method for binary cycle QPSK continuous phases phase-shift keying (PSK) modulation demodulation system according to claim 3, feature
It is, the mathematical model expression formula of binary cycle continuous wave QPSK signals generated for the process (2) is,
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