CN108365639A - Based on the idle respectively control method of the parallel virtual synchronous machine recognized in line impedence - Google Patents
Based on the idle respectively control method of the parallel virtual synchronous machine recognized in line impedence Download PDFInfo
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- CN108365639A CN108365639A CN201810204010.5A CN201810204010A CN108365639A CN 108365639 A CN108365639 A CN 108365639A CN 201810204010 A CN201810204010 A CN 201810204010A CN 108365639 A CN108365639 A CN 108365639A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
- H02J3/46—Controlling of the sharing of output between the generators, converters, or transformers
- H02J3/50—Controlling the sharing of the out-of-phase component
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Abstract
The present invention provides based on the idle respectively control method of the parallel virtual synchronous machine recognized in line impedence, belong to control field, including：Direct-axis current is obtained, pulse current disturbance is added in the direct-axis current got, is sampled to the Current Voltage after disturbing is added, line impedance is obtained based on sampled result；It is thought of as obtained line impedance and electric current to obtain PCC point voltages, voltage control loop is added in control loop and power control loop realizes VSG controls；The voltage compensation value Δ U for causing error for eliminating power angle error interference is added during VSG controls.The voltage of point of common coupling point is obtained according to its pressure drop, is introduced into original VSG controls, the influence of line impedance is eliminated with this.In addition, being superimposed the relevant voltage offset calculated in traditional virtual synchronous machine control, error caused by being coupled by power is eliminated, realizes that accurate reactive power when more VSG parallel connections is divided equally.
Description
Technical field
It is the invention belongs to control field, more particularly to a kind of idle based on the parallel virtual synchronous machine recognized in line impedence
Divide control method.
Background technology
With the continuous development of technology, distributed energy (DG's) is more widely applied, the parallel running of multiple inverters
Also become current research hotspot.Virtual synchronous machine (VSG) technology increases inertia and resistance on the basis of traditional droop control
Buddhist nun's link so that inverter simulates the operation characteristic of synchronous generator, improves the stability of system transient modelling frequency.However, working as
In the case of multiple inverter parallels, reactive power distribution caused by the power coupling caused by line impedance difference is unbalanced
Problem can not be resolved.
Exist due to the presence of line drop, between active power and reactive power and couples.Due to power coupling presence,
When active power changes, the reactive power of inverter output generates change also with the variation of active power.Consider line
The influence of road resistance difference is answered method by being disturbed to current regulator superimposed current, is calculated according to response using pulsion phase first
Go out line impedance estimated value.Relevant voltage compensation after superposition is computed in traditional virtual synchronous machine control as a result, is eliminated
Error caused by being coupled by power, realizes that accurate reactive power when more VSG parallel connections is divided equally.
Invention content
In order to solve shortcoming and defect existing in the prior art, the present invention provides realize what reactive power was accurately distributed
Divide equally control method based on parallel virtual synchronous machine (VSG) reactive power recognized in line impedence.
In order to reach above-mentioned technical purpose, the present invention provides idle based on the parallel virtual synchronous machine recognized in line impedence
Respectively control method, the idle respectively control method, including：
Direct-axis current is obtained, pulse current disturbance is added in the direct-axis current got, to the electric current after disturbing is added
Voltage is sampled, and line impedance is obtained based on sampled result；
Be thought of as obtained line impedance and electric current to obtain PCC point voltages, be added in control loop voltage control loop and
Power control loop realizes VSG controls；
The voltage compensation value Δ U for causing error for eliminating power angle error interference is added during VSG controls.
Optionally, described that pulse current disturbance is added in the direct-axis current got, to the electric current electricity after disturbing is added
Pressure is sampled, and line impedance is obtained based on sampled result, including：
The output current of inverter is detected；
When detecting that output current reaches positive peak value, it is superimposed the disturbance of negative sense squared-pulse current on output current；
When detecting that output current reaches preset value, the current disturbing being superimposed is cancelled, after revocation current disturbing
Current Voltage corresponding signal is sampled, and line impedance is obtained.
Optionally, described that line impedance is obtained based on sampled result, including：
Obtain the output current response of the constant AC system of continuous two cycle of operation states；
Output current response is converted, the frequency-domain expression of impulse response is obtained；
Positive-negative sequence separation is carried out to frequency-domain expression to calculate, and obtains line impedance value expression.
Optionally, it is described it is idle divide equally control method, further include：
The voltage compensation value Δ U for causing error for eliminating power angle error interference is added during VSG controls.
The advantageous effect that technical solution provided by the invention is brought is：
By obtaining the voltage of point of common coupling (PCC) point according to its pressure drop, it is introduced into original VSG controls, with
This eliminates the influence of line impedance.It is mended in addition, being superimposed the relevant voltage calculated in traditional virtual synchronous machine control
Value is repaid, error caused by being coupled by power is eliminated, realizes that accurate reactive power when more VSG parallel connections is divided equally.
Description of the drawings
It, below will be to attached drawing needed in embodiment description in order to illustrate more clearly of technical scheme of the present invention
It is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, other drawings may also be obtained based on these drawings.
Fig. 1 is provided by the invention based on the idle stream for dividing equally control method of the parallel virtual synchronous machine recognized in line impedence
Journey schematic diagram；
Fig. 2 is provided by the invention theoretic active and reactive power oscillogram.
Specific implementation mode
To keep structure of the invention and advantage clearer, the structure of the present invention is made further below in conjunction with attached drawing
Description.
Embodiment one
The purpose of the present invention is to solve the transient oscillations for although solving active power using existing control method
The problems such as, but the problems such as reactive power can not be evenly distributed there are error and reactive power still exist, present invention offer is based on
Divide equally control method in parallel virtual synchronous machine (VSG) reactive power of line impedence identification, realizes that reactive power is accurately distributed.
The present invention provides based on the parallel virtual synchronous machine recognized in line impedence it is idle divide equally control method, such as Fig. 1 institutes
Show, the idle respectively control method, including：
11, direct-axis current is obtained, pulse current disturbance is added in the direct-axis current got, to the electricity after disturbing is added
Galvanic electricity pressure is sampled, and line impedance is obtained based on sampled result；
12, obtained line impedance and electric current are thought of as obtaining PCC point voltages, voltage control loop is added in control loop
VSG controls are realized with power control loop；
13, the voltage compensation value Δ U for causing error for eliminating power angle error interference is added during VSG controls.
In force, d-axis quadrature axis transient electromotive force is mentioned in the related Sections of synchronous motor in Electrical Motor, it is specific to hand over
Axis between axis-magnetic pole is quadrature axis (also referred to as q axis or horizontal axis), and d-axis-pole center line is d-axis (also referred to as d axis
Or the longitudinal axis).Based on aforementioned theoretical foundation, the idle particular content for dividing equally control method that the present embodiment proposes is：
Step 1: using d, q current control to system, pulse is added in given d shaft currents Idref in place
Current disturbing then samples the Current Voltage after Injection Current perturbation pulse, corresponding response signal is obtained, according to public affairs
Formula is analyzed to obtain line impedance.
Step 2: after previous step obtains line impedance value, it is multiplied with electric current, indirectly obtains the voltage of PCC points
Upcc, then voltage control loop and power control loop are added in control loop, realize complete VSG controls.
Step 3: since there are power angle error interference Δ δ in circuit so that idle when given active power changes
Power also generates deviation delta Q.A voltage compensation Δ U is added in the VSG of step (2) controls as a result, eliminates power angle error
Interfere error caused by Δ δ.
Wherein, it is the step of acquisition PCC point voltages in step 2：
The line impedance value Rl and Ll obtained according to step (1) obtains corresponding line impedance value.Under dq coordinates, pass through
It calculates, obtains the voltage Upcc of point of common coupling (PCC) point indirectly.
Wherein, P, Q, U respectively represent active power, reactive power and the voltage of DG outputs.
When multiple inverters carry out parallel running, line impedance is to influence an important parameter of its control and operation.
Voltage, current regulator and power control loop are added in control loop, realizes complete VSG controls.Herein
VSG refer to virtual synchronous generator (Virtual synchronous generator).
Since there is power angle error interference Δ δ in circuit so that reactive power also generates deviation delta Q.As a result, in step
A voltage compensation Δ U is added in rapid two VSG controls, eliminates error caused by being coupled by power.
Active and reactive power the formula that inverter is exported to power grid is as follows：
Z is inverter output impedance.
By above formula, small-signal model formula is as follows：
Wherein, U0 is the steady state output voltage of inverter, and δ 0 is steady state power angle.
The value of Δ Q is considered as 0, then additional output voltage compensation is only related to the error interference Δ δ of power angle, obtains
Formula is as follows：
Relevant voltage offset Δ U after middle superposition is computed on the basis of the VSG of step 2 is controlled as a result, is eliminated
Error caused by being coupled by power.
Optionally, described that pulse current disturbance is added in the direct-axis current got, to the electric current electricity after disturbing is added
Pressure is sampled, and line impedance is obtained based on sampled result, including：
The output current of inverter is detected；
When detecting that output current reaches positive peak value, it is superimposed the disturbance of negative sense squared-pulse current on output current；
When detecting that output current reaches preset value, the current disturbing being superimposed is cancelled, after revocation current disturbing
Current Voltage corresponding signal is sampled, and line impedance is obtained.
In force, specific way is to bear one when detecting that the output current of inverter reaches positive peak value
To squared-pulse current disturbance be superimposed upon on given current value, when output current reaches analog value, cancel current disturbing
Pulse.Corresponding Current Voltage response signal is sampled later, line impedance is obtained according to formula analysis.
Optionally, described that line impedance is obtained based on sampled result, including：
Obtain the output current response of the constant AC system of continuous two cycle of operation states；
Output current response is converted, the frequency-domain expression of impulse response is obtained；
Positive-negative sequence separation is carried out to frequency-domain expression to calculate, and obtains line impedance value expression.
In force, system is controlled with d, q shaft current and runs and work, when detecting that the output current of inverter reaches just
When to peak value, a negative sense squared-pulse current disturbance is superimposed upon on given d shaft currents Idref, when the output of inverter
When electric current reaches analog value, current disturbing pulse is cancelled.Current Voltage after disturbance is sampled, corresponding response letter is obtained
Number, line impedance is obtained according to formula analysis.
When analyzing AC system, it is assumed that continuous two basic cycle operating statuses are constant, obtain output current
Disturbance response is：
Δ x (t)=x, (t)-x (t)
Wherein, x (t) is electric current in the Injection Current perturbation pulse period, and x (t) is the electricity in its adjacent next period
Stream, Δ x (t) is the response of current disturbing.
It analyzes to obtain the frequency domain data of impulse response by DFT.DFT is defined as follows：
Wherein, x (n) represents the sample sequence of current signal, and N represents the number of sampled point, and X (k) represents corresponding frequency
Domain sequence.
Again after positive-negative sequence separation calculates, line impedance value Rl and Ll is as follows：
Z [1] be surveyed electric network impedance Z frequency domain sequence in first element, Re [Z [1]], Im [Z [1]] is respectively institute
Surveying line impedance is worth real part and imaginary part, is the frequency resolution of DFT analyses, wherein the sampling week of the corresponding voltage and currents of Ts
Phase.
The excitation electric gesture of two VSG is respectively U1 and U2.It assume that the ratio of the reactive power of two VSG is 2：1.
Two VSG parallel runnings and with common load.During 0~4s, the active power of common load is Pload, and reactive power is
Qload.During 4~8s, the active power of common load increases, and reactive power is still Qload.
Shown in attached drawing 2, during 0~4s, two VSG proportionally undertake the reactive power of common load.4~
During 8s, the active power of common load generates variation.Due to eliminating the error of power coupling, two VSG undertake idle
Watt level is constant.
The method that the present invention uses realizes the accurate of more VSG parallel runnings reactive powers and divides equally.
Under the control of virtual synchronous machine, multiple inverter parallels consider line impedance and power coupling to reactive power
Influence respectively.First, line impedance value is calculated using impulse response method, and point of common coupling is obtained according to its pressure drop
(PCC) voltage put is introduced into original VSG controls, the influence of line impedance is eliminated with this.In addition, in traditional void
It is superimposed the relevant voltage offset calculated in quasi- synchronous machine control, error caused by being coupled by power is eliminated, realizes more
Accurate reactive power when VSG parallel connections is divided equally.
The present invention's is intended to protect and is a little to need under the control of virtual synchronous machine, is mutually tied with the line impedance of on-line identification
It closes, it is proposed that realize the control program that reactive power is divided equally,.When active power increases, to keep reactive power is constant should
It is appropriate to increase voltage.The influence of the changes delta δ and voltage difference delta U at partial derivative available power angle to power is asked to power expression,
Again by P, the calculation formula of Q solves the size delta U for the voltage for needing to compensate, and is added in traditional VSG control rings.Realize removal by
Error caused by line impedance and power coupling, accurate reactive power when more VSG parallel connections are furthermore achieved are divided equally.
Each serial number in above-described embodiment is for illustration only, the assembling for not representing each component or the elder generation during use
Sequence afterwards.
Example the above is only the implementation of the present invention is not intended to limit the invention, all in the spirit and principles in the present invention
Within, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (3)
1. based on the idle respectively control method of the parallel virtual synchronous machine recognized in line impedence, which is characterized in that described idle equal
Divide control method, including：
Direct-axis current is obtained, pulse current disturbance is added in the direct-axis current got, to the Current Voltage after disturbing is added
It is sampled, line impedance is obtained based on sampled result；
It is thought of as obtained line impedance and electric current to obtain PCC point voltages, voltage control loop and power is added in control loop
Control ring realizes VSG controls；
The voltage compensation value Δ U for causing error for eliminating power angle error interference is added during VSG controls.
2. it is according to claim 1 based on the parallel virtual synchronous machine recognized in line impedence it is idle divide equally control method,
It is characterized in that, it is described that pulse current disturbance is added in the direct-axis current got, it is carried out to the Current Voltage after disturbing is added
Sampling, line impedance is obtained based on sampled result, including：
The output current of inverter is detected；
When detecting that output current reaches positive peak value, it is superimposed the disturbance of negative sense squared-pulse current on output current；
When detecting that output current reaches preset value, the current disturbing being superimposed is cancelled, to the electric current after revocation current disturbing
Voltage corresponding signal is sampled, and line impedance is obtained.
3. it is according to claim 2 based on the parallel virtual synchronous machine recognized in line impedence it is idle divide equally control method,
It is characterized in that, it is described that line impedance is obtained based on sampled result, including：
Obtain the output current response of the constant AC system of continuous two cycle of operation states；
Output current response is converted, the frequency-domain expression of impulse response is obtained；
Positive-negative sequence separation is carried out to frequency-domain expression to calculate, and obtains line impedance value expression.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734549A (en) * | 2015-04-14 | 2015-06-24 | 国家电网公司 | Island micro-grid multi-inverter parallel power split control method |
| CN106877386A (en) * | 2015-12-14 | 2017-06-20 | 李福来 | A kind of unbalance voltage compensation method of microgrid inverter |
| CN107121609A (en) * | 2017-05-22 | 2017-09-01 | 广西大学 | A kind of electric network impedance on-line identification method and device that injection is disturbed based on PRBS |
| CN107134798A (en) * | 2017-04-28 | 2017-09-05 | 华中科技大学 | PCC Voltage unbalances and harmonic suppressing method based on parallel virtual impedance |
| CN107482682A (en) * | 2017-09-14 | 2017-12-15 | 湖南大学 | Active filter and distributed power source cooperative control method under a kind of off-network pattern |
-
2018
- 2018-03-13 CN CN201810204010.5A patent/CN108365639B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734549A (en) * | 2015-04-14 | 2015-06-24 | 国家电网公司 | Island micro-grid multi-inverter parallel power split control method |
| CN106877386A (en) * | 2015-12-14 | 2017-06-20 | 李福来 | A kind of unbalance voltage compensation method of microgrid inverter |
| CN107134798A (en) * | 2017-04-28 | 2017-09-05 | 华中科技大学 | PCC Voltage unbalances and harmonic suppressing method based on parallel virtual impedance |
| CN107121609A (en) * | 2017-05-22 | 2017-09-01 | 广西大学 | A kind of electric network impedance on-line identification method and device that injection is disturbed based on PRBS |
| CN107482682A (en) * | 2017-09-14 | 2017-12-15 | 湖南大学 | Active filter and distributed power source cooperative control method under a kind of off-network pattern |
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