CN108365013B - Thin film transistor, array substrate, display panel, preparation method of display panel and terminal - Google Patents
Thin film transistor, array substrate, display panel, preparation method of display panel and terminal Download PDFInfo
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- CN108365013B CN108365013B CN201810164121.8A CN201810164121A CN108365013B CN 108365013 B CN108365013 B CN 108365013B CN 201810164121 A CN201810164121 A CN 201810164121A CN 108365013 B CN108365013 B CN 108365013B
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- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000035939 shock Effects 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 description 13
- 230000003068 static effect Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
Abstract
The invention provides a thin film transistor which comprises a substrate, an active layer and a grid electrode which are positioned on the substrate, and a grid electrode insulating layer arranged between the grid electrode and the active layer, wherein the periphery of the grid electrode is provided with a sharp corner part protruding towards the active layer. The invention also provides an array substrate, a display panel and a terminal, which comprise the thin film transistor. According to the array substrate and the display panel, electrostatic breakdown generated between the sharp corner of the grid and the active layer is utilized to form electrostatic discharge, so that lines and components in the edge area are protected from being damaged by electrostatic shock. The invention also provides a preparation method of the display panel, which is used for preparing the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, an array substrate, a display panel, a preparation method of the display panel and a terminal.
Background
Low Temperature polysilicon (LIPS) panels are widely studied for the development of lighting products and panel industry due to their high mobility, high resolution, simple structure and high stability. Existing electronic products such as Iphone 7 phones, LG G5 phones, and Kindle Fire Hdx tablet computers all use LTPS panels.
However, since the LTPS manufacturing process is complicated and is susceptible to Static Electricity (ESD), the display panel may malfunction or even be damaged due to the Static electricity, and the lifetime of the display panel is seriously affected, so that it is important to enhance the antistatic capability of the LTPS panel.
Disclosure of Invention
The invention aims to provide a thin film transistor which is used for preparing a display panel, preventing the display panel from being damaged by electrostatic shock, improving the yield of the display panel and reducing the manufacturing cost.
The invention further provides an array substrate, a display panel, a terminal and a preparation method of the display panel.
The thin film transistor comprises a substrate, an active layer and a grid electrode which are positioned on the substrate, and a grid electrode insulating layer arranged between the grid electrode and the active layer, wherein the periphery of the grid electrode is provided with a sharp corner part protruding towards the active layer.
Wherein a surface of the active layer facing the gate electrode includes a first region and a second region protruding the first region toward the gate electrode, and the sharp corner corresponds to a junction of the first region and the second region.
The substrate comprises a substrate base plate and a shading layer positioned on the substrate base plate, and the shading layer corresponds to the second area.
Wherein a surface of the gate insulating layer facing away from the active layer includes a third region and a fourth region protruding the third region toward the gate electrode, the fourth region corresponding to the second region, and the third region corresponding to the first region.
The substrate comprises a substrate body and a light shielding layer, wherein the substrate body comprises a buffer insulating layer covering the substrate body and the light shielding layer, the surface of the buffer insulating layer, which is far away from the light shielding layer, comprises a fifth area and a sixth area, which is far away from the light shielding layer and protrudes out of the fifth area, and the sixth area corresponds to the light shielding layer.
Wherein the gate insulating layer has a thickness of 100nm or less.
The array substrate comprises the thin film transistor.
The display panel comprises the array substrate.
The terminal comprises the display panel.
The preparation method of the display panel is used for preparing the display panel and comprises the following steps:
providing a substrate;
forming an active layer on the substrate;
forming a gate insulating layer on the active layer;
and forming a gate electrode on the gate insulating layer, wherein a peripheral edge of the gate electrode is provided with a sharp corner portion protruding toward the active layer.
The thin film transistor is positioned at the periphery of the display area of the display panel and outside the display area, the thin film transistor comprises a grid electrode with a plurality of sharp corners, the sharp corners are easy to cause point discharge like a lightning rod when encountering static electricity, the active layer is enabled to form high and low fluctuation due to the specific pattern design of the light shielding layer, a downward slope angle is formed between the active layer and the sharp corners, and due to the combined action of the extremely thin grid insulating layer and the downward slope angle, the static electricity is released due to the fact that the static electricity is easily broken down between the grid electrode and the active layer, and therefore normal lines and components in the edge area of the display panel are protected from static electricity interference.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a thin film transistor according to the present invention.
Fig. 2 is a top view of the thin film transistor of fig. 1.
Fig. 3 is a schematic structural diagram of the array substrate according to the present invention.
Fig. 4 is a schematic flow chart of a manufacturing method of the display panel according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a thin film transistor 100 for fabricating an array substrate is provided in the preferred embodiment of the present invention to protect normal circuits and devices outside a display area from electrostatic interference. The thin film transistor 100 includes a substrate 10, an active layer 40 and a gate electrode 60 on the substrate 10, and a gate insulating layer 50 between the gate electrode 60 and the active layer 40, wherein a peripheral edge of the gate electrode 60 is provided with a sharp corner 61 protruding toward the active layer 40. In this embodiment, the thickness of the gate insulating layer 50 is 100nm or less.
When the thin film transistor is subjected to static electricity, the sharp corner part at the periphery of the gate electrode attracts the static electricity as the static electricity to cause point discharge, and the sharp corner part protrudes towards the active layer and the gate insulating layer is extremely thin, so that the electrostatic discharge is formed between the gate electrode and the active layer and is extremely easy to break down by the static electricity.
The surface of the active layer 40 facing the gate electrode 60 includes a first region 41 and a second region 42 protruding the first region 41 toward the gate electrode 60, and a sharp corner 61 of the gate electrode 60 corresponds to a junction of the first region 41 and the second region 42. Preferably, the sharp corner 61 faces the position where the second region 42 protrudes from the first region 41, so that the distance between the sharp corner 61 and the active layer 40 is preferably small, and electrostatic breakdown is easily generated between the gate electrode 60 and the active layer 40 due to the thickness of the gate insulating layer 50 being less than 100nm, thereby forming electrostatic discharge. It is understood that the sharp corner 61 may be located near the position where the second region 42 protrudes from the first region 41, as long as the electrostatic breakdown effect is generated between the sharp corner 61 and the active layer 40. In this embodiment, the active layer 40 is made of a polysilicon material or a single crystal silicon material.
In this embodiment, the gate insulating layer 50 is disposed on the active layer 40. The surface of the gate insulating layer 50 facing away from the active layer 40 includes a third region 51 and a fourth region 52 protruding the third region 51 toward the gate electrode 60, the fourth region 52 corresponds to the second region 42, and the third region 51 corresponds to the first region 41. In this embodiment, the third region 51 corresponds to the first region 41, and the fourth region 52 corresponds to the second region 42, which means that the height and shape of the fourth region 52 protruding from the third region 51 are consistent with the height and shape of the second region 42 protruding from the first region 41. The gate insulating layer 50 is made of one selected from silicon oxide, silicon nitride layer, silicon oxynitride layer and combinations thereof
Referring also to fig. 2, the gate electrode 60 is located on the gate insulating layer 50. The periphery of the gate 60 is provided with a plurality of sharp corners 61, and in this embodiment, the specific shape of the gate 60 is not particularly limited, and the periphery of the gate 60 may be provided with the sharp corners 61. As shown in fig. 2, in an embodiment of the present invention, a projection of the gate 60 on the substrate is in a shape of a four-pointed star, the pointed portions 61 are four corners of the four-pointed star, the four corners are located in the third region 51, and the four-pointed star is located in the fourth region 52, that is, the four corners are located at a connection position where the fourth region 52 protrudes from the third region 51, and a distance between the pointed portions 61 and the active layer 40 is small, which is favorable for generating the electrostatic breakdown. It is understood that in other embodiments of the present embodiment, the projection of the gate 60 on the substrate may be a pentagram shape or a hexagram shape. The material of the grid electrode is selected from one of copper, tungsten, chromium, aluminum and combination thereof.
In this embodiment, the active layer 40, the gate insulating layer 50, and the gate electrode 60 are sequentially stacked on the substrate. The substrate includes a base substrate 10, a light-shielding layer 20 laminated on a surface of the base substrate 10, and a buffer insulating layer 30 covering the base substrate 10 and the light-shielding layer 20. Specifically, the light shielding layer 20 is protruded on the substrate 10, and the light shielding layer 20 corresponds to the second region 42. The surface of the buffer insulating layer 30 facing away from the light shielding layer 20 includes a fifth region 31 and a sixth region 32 protruding from the fifth region 31 facing away from the light shielding layer 20, the fifth region 31 corresponds to the first region 41, and the sixth region 32 corresponds to the light shielding layer 20 and the second region 42. Wherein, the substrate base plate 10 is a glass base plate. It is to be understood that in other embodiments, the substrate base plate 10 is not limited to a glass base plate. The light shielding layer 20 is made of light absorbing and shielding materials such as metal, and shields the backlight, so that the active layer is prevented from generating photon-generated carriers under strong light irradiation, the leakage current of the device is prevented from increasing, and the influence of the backlight on the electrical property of the semiconductor is reduced.
The thin film transistor 100 of the present invention further includes an insulating layer 70, a planarization layer 80, and a passivation insulating layer 90. The insulating layer 70 is disposed on the gate insulating layer 50 and covers the gate 60, for isolating the gate 60 from the source and drain metals. The planarization layer 80 and the passivation insulating layer are sequentially stacked on the insulating layer 70.
In the thin film transistor of the present embodiment, the gate electrode 60 having a plurality of sharp corners 61, the active layer 40, and the light-shielding layer 20 are spatially staggered. Because the light-shielding layer 20 is formed into a specific pattern, the surfaces of the buffer insulating layer 30, the active layer 20 and the gate insulating layer 30 above the light-shielding layer 20 are all provided with a rugged structure, the rugged structure of the active layer 40 is formed into a downward slope angle below the sharp corner 61, and the thickness of the gate insulating layer 30 is extremely thin, so that electrostatic breakdown is easily caused between the gate 60 and the active layer 40 to form electrostatic discharge.
Referring to fig. 3, the present invention further provides an array substrate 200, wherein the array substrate 200 includes the thin film transistor 100. The Array substrate 200 of the present invention includes a display region 201 and an edge region 202 surrounding the display region 201, wherein the edge region 202 includes a Gate Driver On Array (GOA) region 204 located at two sides of the display region 201, an Integrated Circuit (IC) region 203 located below the display region 202, and an electrostatic protection region 205 located near the GOA region 204. The thin film transistor 100 is located outside the display area 201 of the array substrate 200 or at the periphery of the display area 201 (i.e., inside the esd protection area 205 shown in fig. 3), when the array substrate 200 is subjected to static electricity, the sharp corner 61 in the thin film transistor 100, such as a lightning rod, attracts the static electricity to cause a tip discharge, and since the distance between the sharp corner 61 and the active layer 40 is small, the sharp corner 61 and the active layer 40 are easily broken down by the static electricity to form an esd discharge, thereby protecting normal lines and components in the edge area 202 from electrostatic interference. A gate driving circuit is disposed in the GOA region 204 of the array substrate 200, and is used for driving the gates to scan line by line.
The invention further provides a display panel, which comprises the array substrate 200.
The invention further provides a terminal which comprises the display panel.
As shown in fig. 4, the present invention further provides a method for manufacturing a display panel, which is used for manufacturing the display panel, and includes:
s1, providing a substrate. Specifically, the method comprises the following steps: providing a substrate 10, forming a light shielding layer 20 on the substrate 10, and forming a buffer insulating layer 30 on the substrate 10 and the light shielding layer 20. The light shielding layer 20 is disposed on the substrate 10 in a protruding manner. The surface of the buffer insulating layer 30 facing away from the light-shielding layer 20 includes a fifth region 31 and a sixth region 32 protruding from the fifth region 31, and the sixth region 32 corresponds to the light-shielding layer 20.
And S2, forming an active layer 40 on the substrate. Specifically, an active layer 40 is formed on the buffer insulating layer 30. Wherein the surface of the active layer 40 facing away from the substrate comprises a first region 41 and a second region 42 protruding the first region 41 away from the substrate. In the present embodiment, the first region 41 corresponds to the fifth region 31, and the second region 42 corresponds to the light shielding layer 20 and the sixth region 32.
S3, a gate insulating layer 50 is formed on the active layer 40. Wherein a surface of the gate insulating layer 50 facing away from the active layer 40 includes a third region 51 and a fourth region 52 protruding from the third region 51, the third region 51 corresponds to the first region 41, and the fourth region 52 corresponds to the second region 42. Further, the thickness of the gate insulating layer 50 is 100nm or less.
S4, a gate electrode 60 is formed on the gate insulating layer 50. Wherein, the periphery of the gate electrode 60 is provided with a plurality of sharp corners 61 protruding towards the active layer 40, and the sharp corners 61 are located at the connection of the third region 51 and the fourth region 52. Specifically, a metal material layer is coated on the gate insulating layer 50, and the metal material layer is patterned by a patterning process such as exposure and development to form the gate 60.
The preparation method of the display panel further comprises the following steps:
s5, forming an insulating layer 70 on the gate insulating layer 50 and the gate electrode 60, wherein the insulating layer 70 isolates the gate electrode 60 from the source and drain metals.
S6, a planarization layer 80 and a passivation insulating layer 90 are sequentially formed on the insulating layer 70.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. A thin film transistor comprises a substrate, an active layer and a grid electrode which are positioned on the substrate, and a grid electrode insulating layer arranged between the grid electrode and the active layer, wherein the surface of the active layer facing the grid electrode comprises a first area and a second area protruding out of the first area facing the grid electrode, the periphery of the grid electrode is provided with a sharp corner portion protruding out of the active layer, and the sharp corner portion corresponds to the connection position of the first area and the second area.
2. The thin film transistor according to claim 1, wherein the substrate includes a base substrate and a light-shielding layer on the base substrate, the light-shielding layer corresponding to the second region.
3. The thin film transistor according to claim 1, wherein a surface of the gate insulating layer facing away from the active layer includes a third region and a fourth region protruding the third region toward the gate electrode, the fourth region corresponding to the second region, and the third region corresponding to the first region.
4. The thin film transistor according to claim 2, wherein the substrate includes a buffer insulating layer covering the substrate and the light-shielding layer, a surface of the buffer insulating layer facing away from the light-shielding layer includes a fifth region and a sixth region protruding from the fifth region facing away from the light-shielding layer, the sixth region corresponding to the light-shielding layer.
5. The thin film transistor according to any one of claims 1 to 4, wherein a thickness of the gate insulating layer is 100nm or less.
6. An array substrate, comprising the thin film transistor according to any one of claims 1 to 5.
7. A display panel comprising the array substrate according to claim 6.
8. A terminal characterized in that it comprises a display panel as claimed in claim 7.
9. A method for manufacturing a display panel, comprising:
providing a substrate;
forming an active layer on the substrate, wherein a surface of the active layer facing away from the substrate comprises a first region and a second region protruding the first region facing away from the substrate;
forming a gate insulating layer on the active layer;
and forming a gate electrode on the gate insulating layer, wherein a peripheral edge of the gate electrode is provided with a sharp corner portion protruding toward the active layer, the sharp corner portion corresponding to a junction of the first region and the second region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810164121.8A CN108365013B (en) | 2018-02-27 | 2018-02-27 | Thin film transistor, array substrate, display panel, preparation method of display panel and terminal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810164121.8A CN108365013B (en) | 2018-02-27 | 2018-02-27 | Thin film transistor, array substrate, display panel, preparation method of display panel and terminal |
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| CN108365013A CN108365013A (en) | 2018-08-03 |
| CN108365013B true CN108365013B (en) | 2021-03-02 |
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| CN113690153B (en) * | 2021-08-10 | 2023-10-31 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT and preparation method of TFT |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0862626A (en) * | 1994-08-16 | 1996-03-08 | Hitachi Ltd | Liquid crystal display substrate |
| JP2010087098A (en) * | 2008-09-30 | 2010-04-15 | Epson Imaging Devices Corp | Display device |
| CN103250256A (en) * | 2010-12-17 | 2013-08-14 | 株式会社半导体能源研究所 | Oxide material and semiconductor device |
| CN103441130A (en) * | 2013-08-29 | 2013-12-11 | 京东方科技集团股份有限公司 | Substrate with static electricity self-protection capability and manufacturing method thereof |
| CN105487317A (en) * | 2016-01-25 | 2016-04-13 | 京东方科技集团股份有限公司 | Substrate and display device |
-
2018
- 2018-02-27 CN CN201810164121.8A patent/CN108365013B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0862626A (en) * | 1994-08-16 | 1996-03-08 | Hitachi Ltd | Liquid crystal display substrate |
| JP2010087098A (en) * | 2008-09-30 | 2010-04-15 | Epson Imaging Devices Corp | Display device |
| CN103250256A (en) * | 2010-12-17 | 2013-08-14 | 株式会社半导体能源研究所 | Oxide material and semiconductor device |
| CN103441130A (en) * | 2013-08-29 | 2013-12-11 | 京东方科技集团股份有限公司 | Substrate with static electricity self-protection capability and manufacturing method thereof |
| CN105487317A (en) * | 2016-01-25 | 2016-04-13 | 京东方科技集团股份有限公司 | Substrate and display device |
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