CN108345792A - Processing method, processing unit and the system of processor input-output operation - Google Patents
Processing method, processing unit and the system of processor input-output operation Download PDFInfo
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- CN108345792A CN108345792A CN201711360110.9A CN201711360110A CN108345792A CN 108345792 A CN108345792 A CN 108345792A CN 201711360110 A CN201711360110 A CN 201711360110A CN 108345792 A CN108345792 A CN 108345792A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/56—Computer malware detection or handling, e.g. anti-virus arrangements
- G06F21/566—Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The present invention provides a kind of processing method, processing unit and the system of processor input-output operation, which is applied to input-output record device.The input-output record device is set between processor CPU and peripheral hardware, for recording the data read-write operation between the CPU and the peripheral hardware.It the treating method comprises：Determine whether that the read operation response data packet that the CPU is initiated reaches the input-output record device；When the read operation response data packet for having the CPU to initiate reaches, read operation response data packet that the CPU is initiated and its data packet for reaching the data read-write operation that the peripheral hardware of the input-output record device is initiated before are sent to the CPU.The present invention can ensure data read-write operation event that the read operation event that processor CPU is initiated is initiated with the peripheral hardware not incorrect order, and can avoid the occurrence of Deadlock by controlling input-output record device to being buffered in transmission opportunity of data packet therein.
Description
Technical field
The present invention relates to a kind of processing method, processing unit and the systems of processor input-output operation.
Background technology
With the large-scale application of the new technologies such as Network Information, information security becomes increasingly serious problem.Usually I
The information security that discusses all be confined to network security, software security etc., but as Recent study shows that hardware is pacified
It should also attract attention entirely.
The scale of hardware design is increasingly promoted with the promotion of hardware design level so that hardware Trojan horse is possibly realized：When
The source of the preceding Hardware I P (intellectual property) with CPU (central processing unit) to be used in the large-scale circuit of representative is diversified, firmly
The flow of part design complicates, and manufactures and designs under the safely controllable property that the factors such as flow division of labor refinement cause hardware final products
Drop.Increased in the design by the possibility of injection malice wooden horse or loophole (hereinafter referred wooden horse), while the increasing of hardware size
Add the difficulty for also increasing that wooden horse is identified and finds.In recent years, with the development of information security concept, the safety of hardware by
Gradually become the research hotspot of information security.
Invention content
Inventor has found, is recorded using the data read-write operation between CPU and peripheral hardware, is examined to the hardware security of CPU
When survey, therefore, to assure that record obtains accurately entering output (Input/Output, I/O) sequence of events, to ensure these I/O things
Part can be restored correctly in detection process.
One aspect of the present invention provides a kind of processing method of processor input-output operation, is applied to input and output
Recording device.The input-output record device is set between processor CPU and peripheral hardware, for record the CPU with it is described
Data read-write operation between peripheral hardware.The processing method comprises determining whether the read operation response data that the CPU is initiated
Packet reaches the input-output record device, and when the read operation response data packet for having the CPU to initiate reaches, will be described
The read operation response data packet and its reach the data that the peripheral hardware of the input-output record device is initiated before that CPU is initiated
The data packet of read-write operation is sent to the CPU.
Optionally, the read operation response data packet for determining whether that the CPU is initiated reaches the input and output note
Recording device, including detection reach the type and/or mark of the data packet of the input-output record device, to determine whether for institute
State the read operation response data packet of CPU initiations.
Optionally, determine whether that the read operation response data packet that the CPU is initiated reaches the input and output described
Before recording device, the processing method further includes the data when the peripheral hardware initiation for reaching the input-output record device
When the data packet total amount of read-write operation reaches predetermined threshold value, request message is sent to the CPU, the request message is for asking
The CPU processing is stored in the data read-write operation of the initiation of the peripheral hardware in the input-output record device.
Optionally, after the transmission request message to the CPU, the processing method further includes described when receiving
CPU send to the response message of the request message when, send reading and writing data corresponding with the request message to the CPU
The data packet of operation.
Optionally, the read operation response data packet for initiating the CPU and its before reach the input and output
The data packet for the data read-write operation that the peripheral hardware of recording device is initiated is sent to after the CPU, and the processing method is also
Include recording the corresponding number of the response message when receiving that the CPU sends to the response message of the request message
Refresh type according to the mark of the data packet of read-write operation, and labeled as automatic.
Optionally, the data read-write operation of the peripheral hardware initiation includes：Direct memory access DMA (Direct Memory
Access, direct memory access) operation；And/or the read-write operation of communication between devices.
Optionally, the data read-write operation that the CPU is initiated includes memory mapping read-write MMIO (Memory mapped I/
O, memory map input and output) operation.
Another aspect of the present invention additionally provides a kind of processing unit of processor input-output operation, is set to processor
Between CPU and peripheral hardware, for recording the data read-write operation between the CPU and the peripheral hardware.The processing unit includes true
Cover half block and the first packet sending module.Determining module is used to determine whether the read operation response data that the CPU is initiated
Packet reaches the input-output record device.First packet sending module is used for when the read operation response for having the CPU to initiate
When data packet reaches, the input-output record device is reached read operation response data packet that the CPU is initiated and its before
The data packet of data read-write operation initiated of the peripheral hardware be sent to the CPU.
Optionally, the determining module includes detection sub-module.Detection sub-module reaches the input and output for detecting
The type and/or mark of the data packet of recording device, to determine whether the read operation response data packet initiated for the CPU.
Optionally, the processing unit further includes request message sending module.Request message sending module is used for described
Before determining whether that read operation response data packet total amount that the CPU is initiated reaches the input-output record device, when to
When the data packet total amount for the data read-write operation initiated up to the peripheral hardware of the input-output record device reaches predetermined threshold value,
Request message is sent to the CPU.The request message is for asking the CPU processing to be stored in the input-output record dress
The data read-write operation that the peripheral hardware in setting is initiated.
Optionally, the processing unit further includes the second packet sending module.Second packet sending module is used for
After the transmission request message to the CPU, when the response message to the request message for receiving the CPU transmissions
When, the data packet of data read-write operation corresponding with the request message is sent to the CPU.
Optionally, the processing unit further includes logging modle.Logging modle is used in the reading for initiating the CPU
The data read-write operation that operation response data packet and its peripheral hardware for reaching the input-output record device before are initiated
Data packet is sent to after the CPU, when receiving that the CPU sends to the response message of the request message, record
The mark of the data packet of the corresponding data read-write operation of the response message, and refresh type labeled as automatic.
Optionally, the data read-write operation that the peripheral hardware is initiated includes direct memory access dma operation；And/or equipment room
The read-write operation of communication.
Optionally, the data read-write operation that the CPU is initiated includes memory mapping read-write MMIO operation.
Another aspect of the present invention additionally provides a kind of processing system of processor input-output operation, including storage list
Member and the processing unit for being coupled to the memory.The processing unit is configured as being based on being stored in the memory
Instruction, execute the processing of processor input-output operation as described above.
Another aspect provides a kind of non-volatile memory mediums, are stored with computer executable instructions, institute
Instruction is stated when executed for realizing method as described above.
Another aspect provides a kind of computer programs.The computer program, which includes that computer is executable, to be referred to
It enables.Described instruction is when executed for realizing method as described above.
Description of the drawings
For a more complete understanding of the present invention and its advantage, referring now to being described below in conjunction with attached drawing, wherein：
Fig. 1 diagrammatically illustrates the processing method of processor input-output operation according to the ... of the embodiment of the present invention, processing dress
It sets and systematic difference scene；
Fig. 2 diagrammatically illustrates the flow of the processing method of the input-output operation of processor according to the ... of the embodiment of the present invention
Figure；
Fig. 3 diagrammatically illustrates the processing method of the input-output operation of processor according to another embodiment of the present invention
Flow chart；
Fig. 4 diagrammatically illustrates the processing method of the input-output operation of processor according to another embodiment of the present invention
Flow chart；
Fig. 5 diagrammatically illustrates the box of the processing unit of processor input-output operation according to the ... of the embodiment of the present invention
Figure；And
Fig. 6 diagrammatically illustrates the processing method according to the ... of the embodiment of the present invention for realizing processor input-output operation
System block diagram.
Specific implementation mode
Hereinafter, will be described with reference to the accompanying drawings the embodiment of the present invention.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present invention.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring idea of the invention.
Term as used herein is not intended to limit the present invention just for the sake of description specific embodiment.It uses herein
The terms "include", "comprise" etc. show the presence of the feature, step, operation and/or component, but it is not excluded that in the presence of
Or other one or more features of addition, step, operation or component.
There are all terms (including technical and scientific term) as used herein those skilled in the art to be generally understood
Meaning, unless otherwise defined.It should be noted that term used herein should be interpreted that with consistent with the context of this specification
Meaning, without should by idealization or it is excessively mechanical in a manner of explain.
It, in general should be according to this using " in A, B and C etc. at least one " such statement is similar to
Field technology personnel are generally understood the meaning of the statement to make an explanation (for example, " with system at least one in A, B and C "
Should include but not limited to individually with A, individually with B, individually with C, with A and B, with A and C, with B and C, and/or
System etc. with A, B, C).Using " in A, B or C etc. at least one " such statement is similar to, it is general come
Say be generally understood the meaning of the statement to make an explanation (for example, " having in A, B or C at least according to those skilled in the art
One system " should include but not limited to individually with A, individually with B, individually with C, with A and B, with A and C, have
B and C, and/or system etc. with A, B, C).It should also be understood by those skilled in the art that substantially arbitrarily indicating two or more
The adversative conjunction and/or phrase of optional project shall be construed as either in specification, claims or attached drawing
It gives including one of these projects, the possibility of these projects either one or two projects.For example, phrase " A or B " should
It is understood to include the possibility of " A " or " B " or " A and B ".
Shown in the drawings of some block diagrams and/or flow chart.It should be understood that some sides in block diagram and/or flow chart
Frame or combinations thereof can be realized by computer program instructions.These computer program instructions can be supplied to all-purpose computer,
The processor of special purpose computer or other programmable data processing units, to which these instructions can be with when being executed by the processor
Create the device for realizing function/operation illustrated in these block diagrams and/or flow chart.
Therefore, technology of the invention can be realized in the form of hardware and/or software (including firmware, microcode etc.).Separately
Outside, technology of the invention can take the form of the computer program product on the computer-readable medium for being stored with instruction, should
Computer program product uses for instruction execution system or instruction execution system is combined to use.In the context of the present invention
In, computer-readable medium can be the arbitrary medium can include, store, transmitting, propagating or transmitting instruction.For example, calculating
Machine readable medium can include but is not limited to electricity, magnetic, optical, electromagnetic, infrared or semiconductor system, device, device or propagation medium.
The specific example of computer-readable medium includes：Magnetic memory apparatus, such as tape or hard disk (HDD)；Light storage device, such as CD
(CD-ROM)；Memory, such as random access memory (RAM) or flash memory；And/or wire/wireless communication link.
The embodiment provides a kind of processing methods and processing unit of processor input-output operation.The processing
Method is applied to input-output record device.The input-output record device is set between processor CPU and peripheral hardware, for remembering
Record the data read-write operation between processor CPU and the peripheral hardware.The processing method includes：Determine whether processor CPU
The read operation response data packet of initiation reaches the input-output record device, and when the read operation for having processor CPU to initiate
When response data packet reaches, input and output note is reached the processor CPU read operation response data packets initiated and its before
The data packet for the data read-write operation that the peripheral hardware of recording device is initiated is sent to processor CPU.
It should be understood that when being reached with the fooled read operation response data packet for being stated CPU initiations, what is sent to CPU is outer
If the data packet for the data read-write operation initiated only includes the data packet of " uplink ", the data packet without including " downlink "." on
The data packet of row " is that the data packet of CPU is flowed to by peripheral hardware, and the data packet of " downlink " is that the data packet of peripheral hardware is flowed to by CPU.
In one embodiment, which is additionally operable to ask processor CPU processing peripheral hardware initiations
Data read-write operation, and when receiving the instruction that processor CPU is sent, the number for the data read-write operation that peripheral hardware is initiated
It is sent to processor CPU according to packet, the data read-write operation that peripheral hardware is initiated is snapped into the location of instruction.In this way, defeated inputting
Go out record in recording device and forms I/O sequences of events.
According to an embodiment of the invention, when the read operation response data packet for having processor CPU to initiate reaches, the input
The data packet for the data read-write operation that wherein stored peripheral hardware is initiated is sent to the processor by output recording device automatically
CPU, while the processor CPU read operation response data packets initiated are also sent to processor CPU.In this way, originally
The processing method and processing unit of inventive embodiments avoid the reading behaviour for waiting for processor CPU to initiate due to processor CPU
Make response data packet and suspend and execute current instruction stream, caused I/O sequences of events are out of order and processor CPU deadlocks are asked
Topic.
Specifically, if without using read operation response triggering input-output record used above provided in an embodiment of the present invention
The method of device transmission data packet, may bring following problem：
A kind of situation is the problem that I/O sequences of events can be brought out of order.To simplify the description, it is indicated using MMIO operation
The read-write operation that CPU is initiated indicates the data read-write operation that peripheral hardware is initiated using dma operation.What if processor CPU was initiated
MMIO reads response and is not suspended by the input-output record device, reaches the processor directly through the input-output record device
CPU, and DMA data packet can be suspended in input-output record device, only in processor CPU response input-output record dresses
Dma operation could be completed after setting the request of transmission.In this case, receive can be after after the MMIO reads response by processor CPU
It is continuous to execute current instruction stream, and the DMA data coating that input-output record device is reached before MMIO reads response pauses at
In input-output record device, thus advanced processing MMIO reads response before handling DMA data packet, and then results in I/O
Sequence of events is out of order.
Another situation is the problem of bringing processor CPU deadlocks.If that is, the MMIO that processor CPU is initiated is read
Response buffer pauses in the input-output record device, at the request processor CPU which sends
When the request message that reason is stored in its internal DMA data packet reaches processor CPU, processor CPU is waiting for caching
Or the MMIO paused in the input-output record device reads response, to which the request message will not be responded so that DMA data packet
Response is read with MMIO to be suspended always in input-output record device, so that processor CPU enters deadlock state.
In summary, the processing method and processing unit of processor input-output operation according to the ... of the embodiment of the present invention is led to
The transmission opportunity for controlling input-output record device to being buffered in data packet therein is spent, is being realized asynchronous event (i.e. peripheral hardware
The data read-write operation of initiation) while snap to the location of instruction, ensure the read operation event and the peripheral hardware that processor CPU is initiated
The data read-write operation event of initiation not incorrect order, and the problem of CPU deadlocks can be avoided the occurrence of.
Fig. 1 diagrammatically illustrates the processing method of processor input-output operation according to the ... of the embodiment of the present invention, processing dress
It sets and systematic difference scene.
It should be noted that being only the example for the scene that can apply the embodiment of the present invention shown in Fig. 1, to help this field
Technical staff understand the present invention technology contents, but be not meant to the embodiment of the present invention may not be usable for other equipment, system,
Environment or scene.
As shown in Figure 1, the application scenarios of the embodiment of the present invention include input-output record device 101, processor CPU (with
Lower abbreviation CPU) 102 and peripheral hardware 103.Peripheral hardware 103 can be video card 103, sound card 103 or hard disk 103 etc. any one or more
Peripheral hardware.
The input-output record device 101 of the embodiment of the present invention is set between CPU 102 and peripheral hardware 103, for recording
Data read-write operation between CPU 102 and peripheral hardware 103.The data read-write operation includes the reading and writing data behaviour that peripheral hardware 103 is initiated
Make the data read-write operation initiated with CPU 102.Wherein, input-output record device 101 can also ask CPU 102 to handle outer
If 103 data read-write operations initiated, and when receiving the instruction of the transmissions of CPU 102, the data that peripheral hardware 103 is initiated are read
The data packet of write operation is sent to CPU 102.Based on above technical scheme, input-output record device 101 is in record CPU 102
While data read-write operation between peripheral hardware 103, the data read-write operation that peripheral hardware is initiated can be aligned to the finger of CPU 102
Position is enabled, is ready for processor security detection.
In this way, measurement processor 104 can be according to the information that memory register core input-output record device records to CPU
102 carry out safety detection.For example, detection process is arranged in the initial operating state information of object run process according to CPU 102
CPU 102 is entered information as the defeated of measurement processor 104 by the initial operating state of device 104 during object run
Enter information.Make task of the measurement processor 104 in a manner of meeting deterministic behavior in performance objective operational process, is detected
The output information and/or termination running state information of processor 104.Wherein, deterministic behavior is the hardware behavior mark of CPU 102
Standard, hardware behavioral standard refer in the behavioral standard of parsing and CPU 102 during executing software instruction stream.Implement at one
In example, the hardware behavioral standard of CPU 102 can be behavior mark specified in 102 specifications of CPU or other standardization documents
It is accurate.For example, for instruction set CPU 102, deterministic behavior can include but is not limited to：The instruction that CPU 102 is realized
Dos command line DOS specified in collection is the response to interruption and the processing row such as behavior and the behavior of input/output port of CPU 102
For.When task during measurement processor 104 has executed object run, according to the output information of measurement processor 104 and/
Or running state information is terminated, determine whether CPU 102 is safe during object run, and export testing result.
As described above, input-output record device 101 is set between CPU 102 and peripheral hardware 103.In specific embodiment
In, input-output record device 101 can be integrated with 102 kernels of CPU.In such cases, input-output record device
101 to be set between CPU 102 and peripheral hardware 103 refer to that input-output record device 101 is set to 102 kernels of CPU and peripheral hardware
Between 103.Certainly, input-output record device 101 can also be embodied as the chip independently of CPU 102, or can also be real
It is now other device forms, this is not limited by the present invention.For example, the input-output record of the embodiment of the present invention can be filled
It is integrated on the same chip with CPU 102 to set 101 part of functions, and remaining other function realizations are independent chip,
These change case should all fall into protection scope of the present invention.It will also be appreciated that input-output record device 101 in logic can be with
The part for belonging to detection device constitutes detection device together with measurement processor 104 and other component parts.
Input-output record device 101 can record the data read-write operation between the CPU 102 and the peripheral hardware 103, packet
Include the data read-write operation that record CPU 102 is initiated and the data read-write operation that record peripheral hardware 103 is initiated.Wherein, 102 CPU
The data read-write operation of initiation for example may include：The data read-write operation of the types such as MMIO.The reading and writing data that peripheral hardware 103 is initiated
It operates and for example may include：The data read-write operation of the types such as DMA, P2P (Peer toPeer, communication between devices).It should be understood that
It is that the embodiment of the present invention can only record the P2P data read-write operations by CPU 102, without recording without CPU 102
P2P data read-write operations.It will also be appreciated that for different types of processor, the data read-write operation of the initiations of CPU 102
May include the read-write operation other than MMIO types, the data read-write operation that peripheral hardware 103 is initiated can also include DMA and P2P classes
Read-write operation other than type.The embodiment of the present invention can be applied to different types of processor, other outside type listed above
The read-write operation of type should also be fallen in the protection domain of the embodiment of the present invention.
The reading and writing data that input-output record device 101 can also ask the CPU 102 to handle the peripheral hardware 103 initiation is grasped
Make, and when receiving the instruction of the CPU 102 transmissions, the reading and writing data that the peripheral hardware 103 therein is initiated will be stored in and grasped
The data packet of work is sent to the CPU 102.
The data that the data read-write operation that CPU 102 is initiated and peripheral hardware 103 are initiated are recorded in input-output record device 101
During read-write operation, it can be divided into the data read-write operation of the initiations of CPU 102 according to the difference of initiator and peripheral hardware 103 is sent out
Two class of data read-write operation risen.Wherein, for opposite CPU 102, the data read-write operation that peripheral hardware 103 is initiated is asynchronous thing
Part.In recording process, input-output record device 101 can intercept PCI (Peripheral Component
Interconnect, external equipment interconnection standard) each chain road occurs in bus data read-write operation, and according to these numbers
The sequence occurred according to read-write operation is temporarily stored in input-output record device 101, forms I/O sequences of events.
According to the data flow for the I/O events that each chain road occurs in pci bus, I/O events can be divided into " under
Row " I/O events and " uplink " I/0 event two major classes.In conjunction with shown in Fig. 1, wherein data flow comes from CPU in " downlink " I/O events
102, flow to peripheral hardware from CPU 102.The terminal of data flow is CPU 102 in " uplink " I/O events.
For each link in pci bus, the I/O events that input-output record device 101 can intercept include " downlink "
I/O events and " uplink " I/O events.
For different types of processor, defined in " downlink " I/O events and " uplink " I/O events may be
Difference, the embodiment of the present invention are not construed as limiting this." downlink " I/O events and " uplink " I/O events is exemplified below.
For example, " downlink " I/O events may include below any one or more：MMIO write operates, and data packet can
To include address, data length and data；MMIO read requests, data packet may include address and data length；DMA readings are answered
It answers, data packet may include data length and data；P2P read requests, data packet may include address and data length；
P2P reads response, and data packet may include data length and data；P2P write operations, data packet may include address, data
Length and data.
For another example, " uplink " I/O events may include below any one or more：DMA write operation, data packet can be with
Including address, data length and data；DMA read request, data packet may include address and data length；MMIO reads response,
Its data packet may include data length and data；P2P read requests, data packet may include address and data length；P2P is read
Response, data packet may include data length and data；P2P write operations, data packet may include address, data length and
Data.
According to embodiments of the present invention, when have CPU 102 initiate read operation response data packet (such as MMIO read response data
Packet) reach when, the number for the data read-write operation for automatically initiating the peripheral hardware 103 stored in the input-output record device 101
It is sent to the CPU 102 according to packet, so that while asynchronous event is snapped to the location of instruction by realization, ensures CPU 102
The data read-write operation event that the read operation event of initiation and the peripheral hardware 103 are initiated not incorrect order, and it is dead to avoid the occurrence of CPU
The problem of lock.It should be understood that in another embodiment, when have read operation response data packet that CPU 102 initiates (for example,
MMIO read response data packet) reach when, can only the DMA data packet stored in the input-output record device 101 be sent out automatically
It send to the CPU 102, the data packet without sending the data read-write operation that all peripheral hardwares are initiated.
It should be noted that in embodiments of the present invention, input-output record device 101 in line direction unlimited can be fixed
Working method.
According to an embodiment of the invention, which can also include associated with CPU 102 any number of interior
It deposits, and/or memory register.
According to an embodiment of the invention, which can also include measurement processor 104.Measurement processor 104 can
With data such as the input/output data and the internal states that obtain processor CPU 102 by read module and memory, and
The I/O sequences of events wherein recorded are read from input-output record device 101.Measurement processor 104 can also be according to getting
CPU 102 input/output data and data and the I/O sequences of events such as internal state, analyze the operation of CPU 102
Instruction behavior in journey, to determine whether CPU hardware is safe.
The processing method of processor input-output operation according to the ... of the embodiment of the present invention is applied to input-output record device
101.Correspondingly, the processing unit or system of processor input and output according to the ... of the embodiment of the present invention can be placed in input and output note
In recording device 101.Alternatively, the processing unit or system of processor input and output according to the ... of the embodiment of the present invention can also be placed in inspection
It surveys in processor 104.Again alternatively, the processing unit or system of processor input and output according to the ... of the embodiment of the present invention can also be
The individual chips etc. being connect with input-output record device 101.
Fig. 2 diagrammatically illustrates the flow of the processing method of the input-output operation of processor according to the ... of the embodiment of the present invention
Figure.
As shown in Fig. 2, the processing method of processor input-output operation according to the ... of the embodiment of the present invention is defeated applied to inputting
Go out recording device 101.The input-output record device 101 is set between processor CPU 102 and peripheral hardware 103, for recording
Data read-write operation between the CPU 102 and the peripheral hardware 103.The processing method includes operation S201 and operation S202.
In operating S201, it is determined whether there is the read operation response data packet that the CPU 102 is initiated to reach the input and output
Recording device 101.
In operating S202, when the read operation response data packet for having the CPU 102 to initiate reaches, which is sent out
Rise read operation response data packet and its reach before the input-output record device 101 the peripheral hardware 103 initiate data read
The data packet of write operation is sent to the CPU 102.
According to an embodiment of the invention, it is determined whether there is the read operation response data packet that the CPU 102 is initiated to reach this defeated
When entering to export recording device 101, can by detection reach the input-output record device 101 data packet type and/or
Mark, to determine whether the read operation response data packet initiated for the CPU 102.
Specifically, the data packet for reaching input-output record device 101 can be detected in real time, to pass through the class of data packet
Type and/or mark determine whether the read operation response data packet initiated for the CPU 102.
For example, the type of data packet can be MMIO write operation, read request and read response, DMA write operation, read request and reading
Any one of response and P2P write operations, read request and reading response, and the mark of data packet can be data read-write operation
The mark of initiator or destination address etc..For example, the mark of data packet can be used to indicate that the initiation of the data read-write operation
Side is CPU 102 or peripheral hardware 103.Therefore, peripheral hardware can be determined whether it is according to the type of data packet and/or mark to initiate
Data read-write operation data packet.
For example, when detecting the type of a data packet as read operation response, or be the read operation data packet of " uplink ",
And the mark of the data packet shows that the data packet is that CPU 102 is initiated, then being assured that out that the data packet is CPU 102
The read operation response data packet of initiation.
According to an embodiment of the invention, the data read-write operation which initiates may include direct memory access DMA
The read-write operation of operation and/or P2P communication between devices.
According to an embodiment of the invention, the data read-write operation which initiates may include memory mapping read-write
MMIO operation.
According to an embodiment of the invention, when the read operation response data packet for having the CPU 102 to initiate reaches, it is defeated to trigger this
Enter to export recording device 101 and the data packet for the data read-write operation that the peripheral hardware 103 wherein cached is initiated is sent to this automatically
CPU 102, while the CPU 102 read operation response data packets initiated are also sent to CPU 102, so as to avoid due to this
CPU 102 wait for read operation response data packet and suspend execute current instruction stream caused by 102 deadlocks of CPU the problem of.
When according to the above aspect, by controlling transmission of the input-output record device 101 to being buffered in data packet therein
Machine ensure that the read operation event and the peripheral hardware that CPU 102 is initiated while asynchronous event is snapped to the location of instruction by realization
The 103 data read-write operation events not incorrect orders initiated, and Deadlock can occur to avoid CPU.
Fig. 3 diagrammatically illustrates the processing method of the input-output operation of processor according to another embodiment of the present invention
Flow chart.
As shown in figure 3, the processing method division operation S201 of the input and output of processor according to the ... of the embodiment of the present invention and behaviour
Make except S202, can also include operation S301 and operation S302.
In operating S301, when the data read-write operation that the peripheral hardware 103 for reaching the input-output record device 101 is initiated
Data packet total amount when reaching predetermined threshold value, send request message to the CPU 102.The request message is for asking the CPU
102 processing are stored in the data read-write operation that the peripheral hardware 103 in the input-output record device 101 is initiated.
In operating S302, when receive the CPU 102 transmissions to the response message of the request message when, to the CPU
102 send the data packet of data read-write operation corresponding with the request message.
According to an embodiment of the invention, when the asynchronous event number kept in input-output record device 101 reaches default threshold
When value, request message can be sent to CPU 102, to ask CPU 102 to handle the asynchronous thing in input-output record device 101
Part.Later, it is possible that two kinds of situations：In the first scenario, when CPU 102 is connected to the request message, CPU
102 are not at the state for waiting for read operation response data packet, and CPU 102 can carry out timely processing to present instruction stream at this time；
In the latter case, when CPU 102 is connected to the request message, CPU 102, which is in, waits for read operation response data
The state of packet, at this time CPU 102 will suspend the processing to present instruction stream.
In the first scenario, it after CPU 102 receives the request message, can be sent out to input-output record device 101
Send instruction, with indicate input-output record device 101 will temporary all or part of asynchronous event therein be sent to CPU 102 into
Row processing.It is thus possible to execute operation S302.
In the latter case, CPU 102 is waiting for the read operation response data packet that the CPU 102 is initiated, CPU 102
It will not send and indicate to input-output record device 101.To which operation S302 will not be temporarily performed.Reality according to the present invention
Example is applied, after the read operation response data packet that CPU 102 is initiated only is sent to CPU 102 by operation S202, CPU 102
It can just handle receiving the request message, the response to the request message is sent to input-output record device 101
Message.Then, operation S302 can be just performed.That is, in the latter case, after operating S301, can only wait for
S202 is operated, and after the request message of CPU response CPU transmissions, operation S302 is carried out.It should be understood that due to operating
The input-output record device 101 has been reached read operation response data packet that CPU 102 is initiated and its before in S202
The data packet for the data read-write operation that the peripheral hardware 103 is initiated is sent to CPU 102, can't actually be sent out in operating S302 at this time
Send data packet.
It will also be appreciated that operation S301 is executed before can operating S201.In further embodiments, S301 is operated
It can parallel execute with operation S201, or be executed after operating S201.
It will also be appreciated that predetermined threshold value can be arbitrary positive integer in embodiments of the present invention, or it is this field skill
After art personnel consider the factors such as processor performance, the numerical value that is rule of thumb arranged.For example, predetermined threshold value can be 1, that is, work as
When thering is the data read-write operation that peripheral hardware 103 is initiated to reach the input-output record device 101, just sends and ask to the CPU 102
Message.
The request message can be interrupt requests, and to ask the processing of CPU 102 after receiving the interrupt requests, pause is held
Instruction stream before the trade, records the data read-write operation that the current location of instruction and pending peripheral hardware 103 are initiated, and to defeated
Enter to export recording device 101 and sends instruction.
It should be understood that the embodiment of the present invention do not limit CPU 102 receive it is performed each after the interrupt requests
The sequencing of action.
In operating S302, input-output record device 101 receives the sound to the request message of the transmission of CPU 102
After answering message, the data packet for the data read-write operation that peripheral hardware 103 is initiated is sent to CPU 102.Also, CPU 102 is completed
After the data read-write operation that peripheral hardware 103 is initiated, stream can be executed instruction according to the current instruction position recovery recorded when interrupting.
Fig. 4 diagrammatically illustrates the processing method of the input-output operation of processor according to another embodiment of the present invention
Flow chart.
As shown in figure 4, the processing method of the input and output of processor according to the ... of the embodiment of the present invention, division operation S301, behaviour
Make except S201 and operation S202, further includes operation S404.Wherein operation S404 is located at after operation S202.
In operation S404, when receive the CPU 102 transmissions to the response message of the request message when, record the response
The mark of the data packet of the corresponding data read-write operation of message, and refresh type labeled as automatic.
Specifically, according to an embodiment of the invention, when the reading for thering is the CPU 102 to initiate in input-output record device 101
When operating response data packet arrival, reached from before the read operation response data packet that trend CPU 102 sends the CPU 102 initiations
The input-output record device 101 the peripheral hardware 103 initiate data read-write operation data packet.In such manner, it is possible to ensureing
Reach the read operation that the data read-write operation of the peripheral hardware 103 initiation of the input-output record device 101 is initiated with the CPU 102
Response under the premise of incorrect order, does not avoid the problem that CPU deadlocks.
Request message therein is reached to which, CPU 102 can be handled, and according to the responding process of the request message to defeated
Enter to export recording device 101 and sends response message, while the mark of the data packet of the corresponding data read-write operation of recording responses message
Know.
It should be understood that since the data packet for the data read-write operation that actually peripheral hardware 103 is initiated is in CPU 102
CPU 102 is reached before the read operation response data packet of initiation, therefore need to be automatic by packet marking in the embodiment of the present invention
Refresh type, actually above-mentioned peripheral hardware is had been completed before the request message of response input-output record device for indicating
103 data read-write operations initiated.In this way, analyzing the instruction behaviors of CPU 102 in the process of running in measurement processor 104
When, it can CPU 102 is real to execute sequence according to be recovered with the automatic record for refreshing type identification.
As DMA write operation data packet, CPU 102 is sent out the data packet for the data read-write operation initiated below using the peripheral hardware 103
The read operation response data packet risen is for MMIO reads response data packet, in schematically illustrating according to the method for the embodiment of the present invention
The flow of I/O events.Specially：
The first step, CPU 102 are carrying out the MMIO read operations of some link in pci bus；It is sent out in CPU 102
After MMIO read requests, because wait for MMIO read in response to due to be in the lock state.
Second step, if at this point, DMA write operation has occurred in the link, which reaches input-output record
Suspend wherein after device 101.
Third walks, when the DMA write operation data packet total amount in input-output record device 101 reaches predetermined threshold value,
Operation S301 can be executed.That is, input-output record device 101 sends request to CPU 102 handles the DMA write operation data packet
Request message.
When the request message reaches CPU 102, lock is in since CPU 102 is waiting for MMIO to read response for 4th step
Determine state, therefore cannot respond to the request message.
5th step, discovery have MMIO to read response data packet arrival input-output record device 101 (in data packet arrival input
When exporting recording device 101, operation S201 can be executed to determine its type).
6th step executes operation S202 and the MMIO is read response data packet and its reaches input-output record device before
101 DMA write operation data packet is sent to CPU 102 successively according to the sequencing of generation.
7th step, CPU 102 handle each DMA write operation data packet and MMIO read operation number of responses successively in order
According to packet.CPU 102 is no longer locked at this time.
8th step, the request message that is sent in the third step of the processing of CPU 102, so as to input-output record
Device 101 initiates the response message for the request message.
9th step, input-output record device 101 receive the response message, are carried out to operate S302.As before
Described, the DMA write operation data packet in input-output record device 101 and MMIO read response data packet in the 6th step at this time
In be sent to CPU 102, therefore actually there is no send DMA write operation data packet in operating S302.
Tenth step records the mark of the data packet of the corresponding data read-write operation of the response message in operating S404, and
Refresh type labeled as automatic.So that when measurement processor 104 analyzes the instruction behaviors of CPU 102 in the process of running,
It can CPU 102 is real to execute sequence according to be recovered with the automatic record for refreshing type identification
Therefore, the embodiment of the present invention can be in the number for ensureing that the read operation event that processor CPU is initiated is initiated with the peripheral hardware
According to read-write operation event not incorrect order while, avoid the occurrence of Deadlock.
Fig. 5 diagrammatically illustrates the box of the processing unit of processor input-output operation according to the ... of the embodiment of the present invention
Figure.
As shown in figure 5, the processing unit 500 includes determining module 510 and the first packet sending module 520.The processing
Device 500 can be the component part of input-output record device 101.The processing unit 500 can be set to processor CPU
Between 102 and peripheral hardware 103, for recording the data read-write operation between the CPU 102 and the peripheral hardware 103.
According to an embodiment of the invention, which can be used to implement is handled with reference to described in 2~Fig. 4 of figure
The processing method of device input-output operation.
It is defeated that determining module 510 is used to determine whether that the read operation response data packet that the CPU 102 is initiated reaches the input
Go out recording device 101.
Wherein it is determined that module 510 may include detection sub-module 511.
Detection sub-module 511 can be used for detect reach the input-output record device 101 data packet type and/or
Mark, to determine whether the read operation response data packet initiated for the CPU 102.
First packet sending module 520 is used for when the read operation response data packet for having the CPU 102 to initiate reaches, will
The read operation response data packet of the CPU 102 initiations and its peripheral hardware 103 hair for reaching the input-output record device 101 before
The data packet of the data read-write operation risen is sent to the CPU 102.
According to an embodiment of the invention, which further includes request message sending module 530.Request message is sent out
Send module 530 for determine whether the CPU 102 initiate read operation response data packet reach the input-output record dress
Before setting 101, when the data packet for the data read-write operation that the peripheral hardware 103 for reaching the input-output record device 101 is initiated is total
When amount reaches predetermined threshold value, request message is sent to the CPU 102, the request message is for asking the CPU102 processing to be stored in
The data read-write operation that the peripheral hardware 103 in the input-output record device 101 is initiated.
According to an embodiment of the invention, which further includes the second packet sending module 540.Second data
Packet sending module 540 be used for this to the CPU 102 send request message after, when receive the CPU 102 transmission to this
When the response message of request message, the data packet of data read-write operation corresponding with the request message is sent to the CPU 102.
According to an embodiment of the invention, which further includes logging modle 550.Logging modle 550 is used at this
Reach the CPU 102 read operation response data packets initiated and its before the peripheral hardware 103 of the input-output record device 101
The data packet of the data read-write operation of initiation is sent to after the CPU 102, when receive the CPU 102 transmission to the request
When the response message of message, the mark of the data packet of the corresponding data read-write operation of the response message is recorded, and labeled as automatic
Refresh type.
According to an embodiment of the invention, the data read-write operation of the peripheral hardware 103 initiation includes：Direct memory access DMA behaviour
The read-write operation of work and/or communication between devices.
According to an embodiment of the invention, the data read-write operation which initiates includes memory mapping read-write MMIO behaviour
Make.
Processing unit 500 according to the ... of the embodiment of the present invention, when the read operation response data packet for having the CPU 102 to initiate reaches
When, the data packet for the data read-write operation that the peripheral hardware 103 cached in the input-output record device 101 is initiated is sent automatically
It is also sent to CPU 102 to the CPU 102, while by the CPU 102 read operation response data packets initiated, so as to avoid this
CPU 102 suspends due to the read operation response data packet for waiting for the CPU 102 to initiate and executes current instruction stream, caused by
I/O sequences of events are out of order and 102 Deadlocks of CPU.
It is understood that determining module 510, the first packet sending module 520, request message sending module 530,
Two data include sending module 540 and logging modle 550 may be incorporated in a module and realize or therein any one
A module can be split into multiple modules.Alternatively, at least partly function of one or more of these modules module can be with
It is combined at least partly function of other modules, and is realized in a module.According to an embodiment of the invention, determining module
510, the first packet sending module 520, request message sending module 530, the second data include sending module 540 and record
At least one of module 550 can at least be implemented partly as hardware circuit, such as field programmable gate array (FPGA),
Programmable logic array (PLA), system on chip, the system on substrate, the system in encapsulation, application-specific integrated circuit (ASIC), or
It can be realized with carrying out the hardware such as any other rational method that is integrated or encapsulating or firmware to circuit, or with software, hard
The appropriately combined of part and firmware three kinds of realization methods is realized.Alternatively, determining module 510, the first packet sending module
520, request message sending module 530, the second data include at least one of sending module 540 and logging modle 550 can
To be at least implemented partly as computer program module, when the program is run by computer, corresponding module can be executed
Function.
Fig. 6 diagrammatically illustrates the processing method according to the ... of the embodiment of the present invention for realizing processor input-output operation
System block diagram.
As shown in fig. 6, system 600 includes processor 610, computer readable storage medium 620.The robot 600 can be with
The method described above with reference to Fig. 2~Fig. 4 is executed, to realize the processing to processor input-output operation.
Specifically, processing unit 610 for example may include general purpose microprocessor, reconfigurable processor, instruction set processor
And/or related chip group and/or special microprocessor (for example, application-specific integrated circuit (ASIC)), etc..Processing unit 610 is also
It may include the onboard storage device for caching purposes.Processing unit 610 can be performed for reference to figure 2~Fig. 4 descriptions
Single treatment unit either multiple processing units of the different actions of flow according to the method for the embodiment of the present invention.
Computer readable storage medium 620, such as can include, store, transmitting, propagating or transmitting appointing for instruction
Meaning medium.For example, readable storage medium storing program for executing can include but is not limited to electricity, magnetic, optical, electromagnetic, infrared or semiconductor system, device,
Device or propagation medium.The specific example of readable storage medium storing program for executing includes：Magnetic memory apparatus, such as tape or hard disk (HDD)；Optical storage
Device, such as CD (CD-ROM)；Memory, such as random access memory (RAM) or flash memory；And/or wire/wireless communication chain
Road.
Computer readable storage medium 620 may include computer program 621, which may include generation
Code/computer executable instructions make processing unit 610 execute for example above in conjunction with Fig. 2 when being executed by processing unit 610
Method flow and its any deformation described in~Fig. 4.
Computer program 621 can be configured with such as computer program code including computer program module.Example
Such as, in the exemplary embodiment, the code in computer program 621 may include one or more program modules, such as including
621A, module 621B ....It should be noted that the dividing mode and number of module are not fixed, those skilled in the art can
To be combined using suitable program module or program module according to actual conditions, when these program modules are combined by processing unit
610 when executing so that processing unit 610 can execute for example above in conjunction with method flow described in Fig. 2~Fig. 4 and its any
Deformation.
According to an embodiment of the invention, determining module 510, the first packet sending module 520, request message sending module
530, the second data include that at least one of sending module 540 and logging modle 550 can be implemented as describing with reference to figure 6
Corresponding operating described above may be implemented when being executed by processor 610 in computer program module.
It will be understood by those skilled in the art that the feature described in each embodiment and/or claim of the present invention can
To carry out multiple combinations or/or combination, even if such combination or combination are not expressly recited in the present invention.Particularly, exist
In the case of not departing from spirit of that invention and introduction, the feature described in each embodiment of the invention and/or claim can
To carry out multiple combinations and/or combination.All these combinations and/or combination each fall within the scope of the present invention.
Although the present invention, art technology has shown and described with reference to the certain exemplary embodiments of the present invention
Personnel it should be understood that in the case of the spirit and scope of the present invention limited without departing substantially from the following claims and their equivalents,
A variety of changes in form and details can be carried out to the present invention.Therefore, the scope of the present invention should not necessarily be limited by above-described embodiment,
But should be not only determined by appended claims, also it is defined by the equivalent of appended claims.
Claims (16)
1. a kind of processing method of processor input-output operation is applied to input-output record device, the input and output note
Recording device is set between processor CPU and peripheral hardware, for recording the data read-write operation between the CPU and the peripheral hardware,
It is characterized in that, the treating method comprises：
Determine whether that the read operation response data packet that the CPU is initiated reaches the input-output record device；
When the read operation response data packet for having the CPU to initiate reaches, by the CPU read operation response data packets initiated and
Reach before it data read-write operation that the peripheral hardware of input-output record device is initiated data packet be sent to it is described
CPU。
2. processing method according to claim 1, which is characterized in that the reading behaviour for determining whether the CPU and initiating
Make response data packet and reaches the input-output record device, including：
Detection reaches the type and/or mark of the data packet of the input-output record device, to determine whether to send out for the CPU
The read operation response data packet risen.
3. processing method according to claim 1 or 2, which is characterized in that determine whether what the CPU was initiated described
Before read operation response data packet reaches the input-output record device, the processing method further includes：
When the data packet total amount for the data read-write operation that the peripheral hardware for reaching the input-output record device is initiated reaches pre-
If when threshold value, sending request message to the CPU, the request message is for asking the CPU processing to be stored in the input
Export the data read-write operation that the peripheral hardware in recording device is initiated.
4. processing method according to claim 3, which is characterized in that after the transmission request message to the CPU,
The processing method further includes：
When receiving that the CPU sends to the response message of the request message, is sent to the CPU and ask to disappear with described
Cease the data packet of corresponding data read-write operation.
5. processing method according to claim 3, the read operation response data packet for initiating the CPU and its it
The data packet for the data read-write operation that the preceding peripheral hardware for reaching the input-output record device is initiated be sent to the CPU it
Afterwards, the processing method further includes：
When receiving that the CPU sends to the response message of the request message, the corresponding number of the response message is recorded
Refresh type according to the mark of the data packet of read-write operation, and labeled as automatic.
6. processing method according to claim 1 or 2, which is characterized in that the data read-write operation packet that the peripheral hardware is initiated
It includes：
Direct memory access dma operation；And/or
The read-write operation of communication between devices.
7. processing method according to claim 1 or 2, which is characterized in that the data read-write operation that the CPU is initiated includes
Memory mapping read-write MMIO operation.
8. a kind of processing unit of processor input-output operation, is set between processor CPU and peripheral hardware, described for recording
Data read-write operation between CPU and the peripheral hardware, which is characterized in that the processing unit includes：
Determining module is used to determine whether that the read operation response data packet that the CPU is initiated reaches the input-output record
Device；
First packet sending module, for when the read operation response data packet for having the CPU to initiate reaches, by the CPU
The data that the read operation response data packet of initiation and its peripheral hardware for reaching the input-output record device before are initiated are read
The data packet of write operation is sent to the CPU.
9. processing unit according to claim 8, which is characterized in that the determining module includes：
Detection sub-module, type and/or mark for detecting the data packet for reaching the input-output record device, with determination
Whether it is read operation response data packet that the CPU is initiated.
10. processing unit according to claim 8 or claim 9, which is characterized in that the processing unit further includes：
Request message sending module, for determining whether that the read operation response data packet that the CPU is initiated reaches institute described
Before stating input-output record device, when the data read-write operation that the peripheral hardware for reaching the input-output record device is initiated
Data packet total amount when reaching predetermined threshold value, send request message to the CPU, the request message is for asking the CPU
Processing is stored in the data read-write operation that the peripheral hardware in the input-output record device is initiated.
11. processing unit according to claim 10, which is characterized in that the processing unit further includes：
Second packet sending module, for after the transmission request message to the CPU, being sent out when receiving the CPU
Send to the response message of the request message when, send data read-write operation corresponding with the request message to the CPU
Data packet.
12. processing unit according to claim 10, the processing unit further include：
Logging modle, for the read operation response data packet for initiating the CPU and its before reach it is described input it is defeated
The data packet for going out the data read-write operation of the peripheral hardware initiation of recording device is sent to after the CPU, described when receiving
CPU send to the response message of the request message when, record the data of the corresponding data read-write operation of the response message
The mark of packet, and refresh type labeled as automatic.
13. processing unit according to claim 8 or claim 9, which is characterized in that the data read-write operation packet that the peripheral hardware is initiated
It includes：
Direct memory access dma operation；And/or
The read-write operation of communication between devices.
14. processing unit according to claim 8 or claim 9, which is characterized in that the data read-write operation packet that the CPU is initiated
Include memory mapping read-write MMIO operation.
15. a kind of system of processor input-output operation, including：
Storage unit；And
It is coupled to the processing unit of the memory, the processing unit is configured as based on being stored in the storage unit
Instruction, executes the processing method of processor input-output operation according to any one of claims 1 to 7.
16. a kind of non-volatile memory medium, be stored with computer executable instructions, described instruction when executed for realizing
The processing method of processor input-output operation according to any one of claims 1 to 7.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58172729A (en) * | 1982-04-05 | 1983-10-11 | Nippon Telegr & Teleph Corp <Ntt> | Diagnosing circuit of input and output controller |
| US4446516A (en) * | 1980-03-31 | 1984-05-01 | Hitachi, Ltd. | Data compaction system with contiguous storage of non-redundant information and run length counts |
| CN101989191A (en) * | 2010-10-22 | 2011-03-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Realizing method of multi-Ready input CPU (central processing unit) |
| CN104866766A (en) * | 2015-06-05 | 2015-08-26 | 中国电子科技集团公司第五十八研究所 | Detection method aiming at CPU internal hidden instruction type hardware trojan |
-
2017
- 2017-12-15 CN CN201711360110.9A patent/CN108345792B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4446516A (en) * | 1980-03-31 | 1984-05-01 | Hitachi, Ltd. | Data compaction system with contiguous storage of non-redundant information and run length counts |
| JPS58172729A (en) * | 1982-04-05 | 1983-10-11 | Nippon Telegr & Teleph Corp <Ntt> | Diagnosing circuit of input and output controller |
| CN101989191A (en) * | 2010-10-22 | 2011-03-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Realizing method of multi-Ready input CPU (central processing unit) |
| CN104866766A (en) * | 2015-06-05 | 2015-08-26 | 中国电子科技集团公司第五十八研究所 | Detection method aiming at CPU internal hidden instruction type hardware trojan |
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