CN108345337B - Power management system and method thereof - Google Patents
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- CN108345337B CN108345337B CN201710058795.5A CN201710058795A CN108345337B CN 108345337 B CN108345337 B CN 108345337B CN 201710058795 A CN201710058795 A CN 201710058795A CN 108345337 B CN108345337 B CN 108345337B
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention relates to a power management system, comprising: an input power detector configured to generate a first enable signal by detecting whether a first voltage is supplied; a first output stage connected to the input power detector and configured to receive and regulate a first voltage upon receiving a first enable signal; an error operational amplifier connected to the first output stage, a first input port of the error operational amplifier configured to receive a first reference voltage, a second input port of the error operational amplifier connected to a connection point of a first resistor and a second resistor, the first resistor connected to the first output stage, the second resistor grounded, and a system output port at a connection of an output port of the first output stage and the first resistor to drive a load. The invention has the advantage that the stable and efficient working state of the chip can be ensured when the power supply is switched under the condition that a plurality of different types of input power supplies are arranged.
Description
Technical Field
The present invention relates to the field of circuit chip applications, and more particularly but not exclusively to a power management system and method thereof.
Background
In modern chip applications, circuits often have two or more power inputs, and the chips of the circuits may operate at any power input. For example, under normal circumstances, the chip is powered by a lithium battery. When the lithium battery is drained of power and charged through the USB port, the chip will operate on the USB power source, which requires the chip to switch between the two power sources. Therefore, a multiple input power supply solution is desired.
Disclosure of Invention
According to one embodiment of the invention, a power management system comprises: a first output stage configured to receive and regulate a first voltage; an error operational amplifier having a power supply terminal connected to the system input port, an output terminal connected to the input port of the first output stage, a first input port configured to receive a first reference voltage, a second input port connected to a connection point of a first resistor and a second resistor, the first resistor connected to the output port of the first output stage, the second resistor grounded, and a system output port placed on a connection of the output port of the first output stage and the first resistor to drive a load.
According to another embodiment of the present invention, a power management method includes: receiving and regulating a first voltage through a first output stage connected to an output power detector; comparing the first reference voltage and the divided voltage by an error operational amplifier, wherein a power supply terminal of the error operational amplifier is connected to a system output port, an output terminal of the error operational amplifier is connected to an output port of the first output stage, the first output port of the error operational amplifier is configured to receive the first reference voltage, a second output port of the error operational amplifier is connected to a connection point of a first resistor and a second resistor, the connection point outputs the divided voltage, the first resistor is connected to the output port of the first output stage, the second resistor is grounded, and the system output port is placed at a connection of the output port of the first output stage and the first resistor, wherein the method further comprises: an error operational amplifier is operated by the system output port at a system output voltage, wherein the system output voltage is lower than the first voltage and a load is driven by the system output voltage.
Compared with the prior art, the invention has the main advantages that: 1. the automatic power supply switching under the power supply of a plurality of different types of power supplies can be efficiently and quickly realized, and the continuity of power supply is ensured; 2. because only part of the circuit works under higher voltage, the safety of the circuit is greatly ensured; 3. when switching of different types of power supplies is carried out, stable and efficient work of the chip can be guaranteed.
Drawings
Non-limiting, non-exhaustive embodiments of the present invention are described below with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
FIG. 1 is a circuit schematic of a power management system of one embodiment of the invention.
Fig. 2 is a circuit schematic of a power management system of another embodiment of the invention.
Fig. 3A shows a circuit diagram of an input voltage detector in an embodiment of the invention.
Fig. 3B shows a circuit diagram of an input voltage detector in another embodiment of the present invention.
Fig. 4A shows a circuit diagram of a first output stage in an embodiment of the invention.
Fig. 4B shows a circuit diagram of the first output stage in an embodiment of the invention.
Fig. 5 shows a circuit diagram of a selector in an embodiment of the invention.
Fig. 6 shows a circuit diagram of an initial circuit in an embodiment of the invention.
FIG. 7 shows a flow diagram for a power management method in an embodiment of the invention.
Fig. 8 shows waveforms of input and output voltage signals.
Detailed Description
Various aspects and embodiments of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of the embodiments. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. Additionally, some well-known structures or functions may not be shown or described in detail to avoid unnecessarily obscuring the relevant description.
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
FIG. 1 is a schematic circuit diagram for a power management system 100 in one embodiment of the invention. In fig. 1, only a single power input V is shownCCL. Note that in another embodiment, a single power input may include VCCHInstead of VCCL。VCCIs a positive voltage supply and typically the collector of a bipolar transistor is connected to either VCC supply or to and VCCAn associated load. VCCHRepresents VCCHigh value of (V)CCLRepresents VCCLLow value of (c).
The power management system 100 includes a first output stage 110, and an error operational amplifier (ERR OPAMP) 120. The first output stage 110 receives and regulates a first voltage (V)CCL). The power supply terminal of the error operational amplifier 120 is connected to the system output port VOUTThe output terminal of the error operational amplifier 120 is connected to the input port of the first output stage 110. First input port (e.g., positive input) of error operational amplifierThe input port is denoted by +) receives a first reference voltage vref 1. A second input port (e.g., a negative input port represented by-) of the error operational amplifier is connected to a junction of the first resistor RFB1 and the second resistor RFB 2. The first resistor RFB1 is connected to the output port of the first output stage 110. The second resistor RFB2 is grounded. That is, the output port of the error operational amplifier 120, the first output stage 110, and the first resistor RFB1 form a negative feedback loop. The system output port VOUT is placed at the connection of the output port of the first output stage 110 and the first resistor RFB1 to drive a load. According to fig. 1, the positive input port and the negative input port of the error operational amplifier 120 are virtually grounded, or in other words, the voltages of the positive input port and the negative input port are the same.
In another embodiment, the power management system 100 further includes a Bandgap (BG) voltage generator 130. The bandgap reference voltage generator 130 is connected to the error operational amplifier 120 and is configured to output a first reference voltage vref1 to a first input port of the error operational amplifier 120. The reference voltage vref1 output by bandgap reference voltage generator 130 is constant.
Fig. 2 is a circuit schematic for a power management system 200 in another embodiment of the invention.
The power management system 200 includes a first output stage 210, an error operational amplifier 220, and a bandgap reference voltage generator 230, each of which is similar with respect to the first output stage 110, the error operational amplifier 120, and the bandgap reference voltage generator 130 discussed with respect to fig. 1. The power management system 200 further comprises a second output stage 240, an input power detector 250, the input power detector 250 being connected to the first output stage 210 and the second output stage 240. The input power detector 250 detects whether the first voltage V is provided or notCCLOr a second voltage VCCHGenerating a first enable signal VCCLenOr the second enable signal VCCHen. The first output stage 210 receives the first enable signal V onceCCLenReceive and regulate the first voltage VCCL. The second output stage 240 receives the second enable signal V onceCCHenReceive and regulate the second voltage VCCH. The output port of the second output stage 240 is connected to the output port of the first output stage 210. The input port of the second output stage 240 is connected to the output port of the error operational amplifier 220.
During operation, VCCLOr VCCHWhen energized, the output stage produces a voltage Vstart, which is less than vref R, as shown in FIG. 2FB2/(RFB1+RFB2). The output voltage should be vref R after start-upFB2/(RFB1+RFB2). If Vstart>vref*RFB2/(RFB1+RFB2) Meaning that the negative feedback loop cannot operate properly, the output Vout will be Vstart. Therefore Vstart should be less than vref RFB2/(RFB1+RFB2). The bandgap reference voltage generator 230 and the error operational amplifier 220 operate at the Vstart voltage. When the bandgap voltage generator 230 and the error operational amplifier 220 are stabilized, in other words, the bandgap voltage reaches the target design value, all the feedback loops operate, and thus the output voltage VOUTStabilized at vref RFB2/(RFB1+RFB2)。
Fig. 2 shows a circuit comprising two power supply inputs. The circuit generates a stable VOUTAnd (6) outputting. Note that the power supply detector 250, the first output stage 210, and the second output stage 240 are at VCCLAnd VCCHAnd (4) working. The bandgap reference voltage generator 230 and the error operational amplifier 220 are at a voltage VOUTAnd (4) working.
In fact, VCCL、VCCHThe voltage is higher than the CMOS device can withstand. For example, a 3VN channel metal oxide semiconductor field effect transistor (NMOS FET) can withstand a maximum voltage of 3.65V, where VCCLUp to 4.2V and VCCHUp to 5.7V.
As with the circuit shown in fig. 2, only the power supply detector 250, the first output stage 210 and the second output stage 240 operate at high voltages, and the devices in these blocks need to perform voltage conversion to avoid over-voltages. On the other hand, the bandgap reference voltage generator 230 and the error operational amplifier 220 are at a voltage VOUTLower job, lowerMaximum sustainable pressure on the apparatus, e.g. VOUTBelow 3.6V, this eliminates the need for overpressure treatment.
Fig. 3A is a circuit diagram showing an output voltage detector 300A in one embodiment of the invention. The output voltage detector 300A includes a comparator 310, first and second NOT gates (NOT gate)320 and 330, a resistor R1, and a resistor R2. Resistor arrays R1 and R2 are used to detect VCCH. The comparator 310 determines whether the output voltage is the first voltage by comparing the output voltage with the second reference voltage vref 2. The value of the second reference voltage verf2 may be according to the first input voltage VCCLAnd a second input voltage VCCHThe relationship of (c) is set. For example, vref2 may be 1.2V or other values. If the input voltage is lower than or equal to the second reference voltage vref2 (R1+ R2)/R2, the comparator 310 outputs the first enable signal V through the second not gate 330CCLenAnd a second disable signal VCCHenb. If the input voltage is higher than the second reference voltage vref2, the comparator 310 outputs a second enable signal V through the first NOT gate 320CCHenAnd a first disable signal VCCLenb。
Fig. 3B is a circuit diagram showing an input voltage detector 300B in another embodiment of the present invention. In addition to the comparator 310, which has been discussed with respect to fig. 3A, the input voltage detector 300B further includes a first level shifter 340 and a second level shifter 350. The first and second level shifters 340 and 350 are connected to an output port of the comparator 310. The first level shifter 340 is configured to output a first enable signal VCCLenAnd a first disable signal VCCLenbAnd the second level shifter 350 is configured to output a second enable signal VCCHenAnd a second disable signal VCCHenb. For the first and second level shifters 340 and 350, the highest input voltage is Vout and the lowest input voltage is 0. For the output range of the first level shifter 340, if VCCLThe output stage is enabled, the highest output voltage is VCCLThe lowest output voltage is VCCL3.6V and 0V (max { V)CCL-3.6, 0}) larger. For the output of the second level shifter 350, if VCCHThe output stage is enabled, the high output voltage is VCCHThe low output voltage is VCCH3.6V and 0V (max { V)CCH-3.6, 0 }).
Fig. 4A is a circuit diagram showing a first output stage 400A in one embodiment of the invention. As shown in fig. 4A, the first output stage further includes a first PMOS P1, a second PMOS P2, a third PMOS P3, a fourth PMOS P4, and a first NMOS N1. The source of the first NMOS N1 is configured to receive the output of the error op amp 220, as in the example shown in fig. 2. The drain of the first NMOSN1 is connected to the drains and gates of all of the second PMOS P2, the gate of the fourth PMOS P4, and the drain of the third PMOS P3. The source of the second PMOS P2 is connected to the drain of the first PMOS P1. The source of the first PMOS P1 and the source of the third PMOSP3 are configured to receive a first voltage equal to the first voltage VCCL. The gate of the first PMOS P1 receives the first disable signal VCCLenbThe gate of the third PMOS P3 receives the first enable signal VCCLen. A combination of the first, second, third, and fourth PMOS P1, P2, P3, and P4 is connected to an output port of the selector NWELL _ SEL 410. The first input port of the selector NWELL _ SEL410 is connected to a first voltage VCCL. A second input port of selector NWELL _ SEL410 is connected to the system output port, i.e., at least the output port of error op amp 220 as shown in fig. 2. The detailed structure of the selector NWELL _ SEL410 will be discussed below with reference to fig. 5. The input port of the start-up circuit 420 receives a first input voltage VCCLThe output port of the start-up circuit is connected to the system output port. According to the circuit shown in FIG. 4A, VOUTIs protected to V of not more than 3.6VOUTThe voltage and therefore the circuit element will not be damaged. Selector NWELL _ SEL410 is used to generate the bias voltage for the PMOS NWELL. The third PMOS P3 and the first PMOS P1 are used to enable the output stage. The first NMOS N1 may be removed. The second PMOS P2 and the fourth PMOS P4 are devices of the first output stage. For example, the output stage 1210 may include a second PMOS P2 and a fourth PMOS P4. If Vcclen is high, then the third PMOS P3 is turned on, the first PMOS P1 is turned off, and Vout is pulledTo VCCL. The output stage is powered off. Vout can be higher or lower than VCCL. On the contrary, if VCCLenbVery high, the first PMOS P1 is turned on and the third PMOS P3 is turned off. The output stage is powered on. Vout is therefore lower than VCCL. The start-up circuit 420 is a start-up step for generating an initial output voltage.
Fig. 4B is a circuit diagram showing a first output stage 400B in another embodiment of the invention. Fig. 4B is similar to fig. 4A, except that the first NMOS N1 is removed in fig. 4B.
Note that although it is not shown that the second output stage includes the same structure as the first output stage 400, the second output stage is different in that the first input voltage V isCCLIs replaced by a second input voltage VCCHAnd VCCLenAnd VCCLenbAre respectively replaced by VCCHenAnd VCCHenb。
Specifically, the second output stage further includes a first PMOS P1 ', a second PMOS P2 ', a third PMOS P3 ', a fourth PMOS P4 ', and a first NMOS N1 '. The source of the first NMOS N1' receives the output of the error op amp. The drain of the first NMOSN1 'is connected to the drains and gates of all of the second PMOS P2', the gate of the fourth PMOS P4 ', and the source of the third PMOS P3'. The source of the second PMOS P2 'is connected to the drain of the first PMOS P1'. The drain of the first PMOS P1 'and the drain of the third PMOS P3' receive a second voltage VCCH. The gate of the first PMOS P1' receives the second disable signal VCCHenb. The gate of the third PMOS P3' receives the second enable signal VCCHen. The combination of the first PMOS P1 ', the second PMOS P2', the third PMOS P3 ', the fourth PMOS P4' is connected to the output port of the selector. The selector has a first input port connected to the second voltage and a second input port connected to the system output port. The input port of the startup circuit is configured to receive the second input voltage, and the output port of the startup circuit is connected to the system output port.
Fig. 5 is a circuit diagram showing the selector 500 in one embodiment of the present invention. The selector 500 may be the selector NWELL _ SEL410 shown in fig. 4A. The selector 500 further includes a fifth PMOS P5, a sixth PMOS P5PMOS P6, seventh PMOSP7, eighth PMOS P8, ninth PMOS P9, and tenth PMOS P10. The sources of all of the fifth, sixth, and ninth PMOS P5, P6, and P9 are configured to receive the first input voltage VCCL. The gates of the fifth PMOS P5, seventh PMOS P7, and tenth PMOS P10 are connected to the drains of the fifth PMOS P5 transistor and sixth PMOS transistor P6, and the first current source I1. The sources of the seventh PMOS P7, the eighth PMOS P8, and the tenth PMOS P10 are connected to the system output port VOUT. The gates of the eighth PMOS 8, the sixth PMOS P6, and the ninth PMOS P9 are connected to the drains of the eighth PMOS P8 and the seventh PMOS P7, and the second current source I2. The drain of the ninth PMOS P9 is connected to the drain of the tenth PMOS P10.
Although not shown in fig. 5, the selector included in the second output stage further includes a fifth PMOS P5 ', a sixth PMOS P6', a seventh PMOS P7 ', an eighth PMOS P8', a ninth PMOS P9 ', and a tenth PMOS P10'. The sources of all of the fifth PMOS P5 ', the sixth PMOS P6 ', and the ninth PMOS P9 ' are configured to receive the second input voltage VCCL. The gates of the fifth, seventh, and tenth PMOS P5 ', P7', P10 'are connected to the drains of the fifth and sixth PMOS transistors P5', P6 ', and the first current source I1'. The sources of the seventh, eighth, and tenth PMOS P7 ', P8 ', P10 ' are connected to the system output port VOUT. The gates of the eighth PMOS P8 ', sixth PMOS P6', and ninth PMOS P9 'are connected to the drains of the eighth PMOS 8' and seventh PMOS P7 ', and the second current source I2'. The drain of the ninth PMOS P9 'is connected to the drain of the tenth PMOSP 10'. The selector 500 is used to select from VCCLAnd vout the higher one of the voltages is selected. If vout>VCCLThe output of selector 500, Vnw, will be vout if VCCL>vout, then vo will be VCCL. Note that Vnw in fig. 4A and 4B refers to Vo in fig. 5.
E.g. VCCL>vout, V2 will be lower than V1, P6 will be energized, V1 will be pulled up to V by P6CCL. P10 and P7 will be powered off, v2 is lower than vout, v2 is vout-vgs _ P8, vout-v2>I vth _ P9 i, so P9 will be energized, vo is VCCL。
At another placeIn the examples, if VCCL<Vout, V2 will be higher than V1, P7 will be energized, and V2 will be pulled high by P7 to Vout, P9 and P6 will be de-energized, V1 will be lower than V1CCL,v1=VCCL-vgs_P5,VCCL-v1>I vth _ P10 i, so P10 is powered on, vo Vout.
Fig. 6 is a circuit diagram showing a startup circuit 600 in one embodiment of the invention. The startup circuit 600 may be the startup circuit 420 as shown in fig. 4A. The start-up circuit 600 further includes an eleventh PMOS P11, a twelfth PMOS P12, a second NMOS NTM2, a third NMOS N3, a fourth NMOS N4, a fifth NMOS N5, and a sixth NMOS N6. The gates of the eleventh PMOS P11 and the twelfth PMOS P12 are connected to the drain of the eleventh PMOS P11 and the drain of the second NMOS NTM 2. The second NMOS NTM2 may be a homemade MOS. When vgs is 0V, domestic mos may be used, however when vgs is>vth (with a vth of about 0.7v, which will be different for different processes, but which is>0) When the normal NMOS will be used. The sources of the eleventh PMOS P11 and the twelfth PMOS P12, and the drain of the fifth NMOS N5 are configured to receive a first voltage VCCLen. The drain of the twelfth PMOSP12 is connected to the gate of the fifth NMOS N5. The drain and gate of the fourth NMOS N4 are connected to the gate of the fifth NMOS N5. The source of the fourth NMOS N4 is connected to the drain and gate of the sixth NMOS N6. The source of the sixth NMOS N6 is connected to the drain and gate of the third NMOS N3. The start-up circuit 600 is used to generate an initial voltage. The second NMOS NTM2 generates the bias current I3. The mirror current I4 is a mirror current of the bias current I3. The mirror current I4 is injected into N4, N6, N3 to generate the voltage vg, vout-vg — N5. The bias current I3 and the mirror current I4 may be current sources.
Voltages greater than 1.8V may be generated for generating the initial voltage VOUT. Because some modules (band gap reference voltage generator, error operational amplifier) are at voltage VOUTWorking down if there is no initial voltage V once energizedOUTThen the bandgap reference voltage generator and the error operational amplifier will not work normally, resulting in operation failure of the whole system. Although fig. 6 shows three cascaded NMOS transistors N4, N6, and N3, a diode connected NMOS transistor and a current flowing through the NMOThe current of S is related to the IC process and can be determined from simulations.
Although not shown in fig. 6, the start-up circuit in the second output stage further includes an eleventh PMOS P11 ', a twelfth PMOS P12 ', a second NMOS NTM2 ', a third NMOS N3 ', a fourth NMOS N4 ', a fifth NMOS N5 ', and a sixth NMOS N6 '. Gates of the eleventh PMOS P11 ' and the twelfth PMOS P12 ' are connected to a drain of the eleventh PMOS P11 ' and a drain of the second nmostm 2 ', a source of the eleventh PMOS P11 ' and a source of the twelfth PMOS P12 ', and a drain of the fifth NMOS N5 ' receives the second voltage VCCH. The drain of the twelfth PMOS P12 'is connected to the gate of the fifth NMOS N5'. The drain and gate of the fourth NMOSN4 'are connected to the gate of the fifth NMOS N5'. The source of the fourth NMOS N4 'is connected to the drain and gate of the sixth NMOS N6'. The source of the sixth NMOS N6 'is connected to the drain and gate of the third NMOS N3'.
Fig. 7 is a flow diagram illustrating a power management method 700 in one embodiment of the invention.
The power management method 700 comprises: at step 710, receiving and regulating a first voltage through a first output stage connected to an input power detector; at step 720, the first reference voltage and the divided voltage are compared by an error operational amplifier, wherein a power supply terminal of the error operational amplifier is connected to a system output port, an output terminal of the error operational amplifier is connected to an output port of the first output stage, a first input port of the error operational amplifier is configured to receive the first reference voltage, a second input port of the error operational amplifier is connected to a connection point of the first resistor and the second resistor, the connection point outputting the divided voltage, the first resistor is connected to the output port of the first output stage, the second resistor is grounded, and the system output port is located at a connection of the output port of the first output stage and the first resistor. The power management method 700 further comprises: at step 730, operating an error operational amplifier at a system output voltage via the system output port, wherein the system output voltage is lower than the first voltage; and, at step 740, the load is driven at the system output voltage.
In another embodiment, the voltage management system further comprises a bandgap reference voltage generator, wherein the bandgap reference voltage generator is connected to the error operational amplifier and configured to output a first reference voltage to the first input port of the error operational amplifier.
In another embodiment, the voltage management system further comprises a second output stage, an input power detector connected to the first output stage and the second output stage. The power management method 700 further includes (not shown in fig. 7): generating a first enable signal or a second enable signal by detecting whether the first voltage or the second voltage is supplied, by the input power detector; receiving and regulating a first voltage through a first output stage upon receiving a first enable signal; receiving and regulating a second voltage through a second output stage upon receiving a second enable signal; wherein the output port of the second output stage is connected to the output port of the first output stage; the input port of the second output stage is connected to the output port of the error operational amplifier.
In another embodiment, the power management method 700 further comprises (not shown in fig. 7): determining, by a comparator, whether the input voltage is a first voltage by comparing the input voltage with a second reference voltage; outputting a first enable signal and a second disable signal through a comparator if the input voltage is less than or equal to a second reference voltage; if the input voltage is higher than the second reference voltage, the second enable signal and the first disable signal are output through the comparator.
Fig. 8 shows waveforms of input and output voltage signals. Vout first reaches Vstart and then settles at V, as shown in FIG. 8OUT. Note that if there is no VCCHThen VCCWill be VCCLOtherwise, VCCWill be VCCH。
From the foregoing, it will be appreciated that specific embodiments of the technology described herein are provided for purposes of illustration; various modifications may be made without deviating from the spirit and scope of the invention. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The invention also relates to embodiments comprising all these functions, even if specific features are recited in different dependent claims. Any reference signs in the claims shall not be construed as limiting the scope.
The features and aspects of the various embodiments may be integrated into other embodiments, and the embodiments shown herein may be practiced without all of the features or aspects shown or described. It will be appreciated by those skilled in the art that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Furthermore, features of one embodiment may be incorporated into other embodiments, even where those features are not described together in a single embodiment, in this document. Accordingly, the invention is described by the appended claims.
Claims (11)
1. A power management system, comprising:
a first output stage configured to receive and regulate a first voltage;
an error operational amplifier, wherein a power supply terminal of the error operational amplifier is connected to a system output port, an output terminal of the error operational amplifier is connected to an input port of the first output stage, a first input port of the error operational amplifier is configured to receive a first reference voltage, a second input port of the error operational amplifier is connected to a connection point of a first resistor and a second resistor, the first resistor is connected to an output port of the first output stage, the second resistor is connected to ground, and the system output port is located at a connection of the output port of the first output stage and the first resistor to drive a load;
further comprising a bandgap reference voltage generator, wherein the bandgap reference voltage generator is connected to the error operational amplifier and configured to output the first reference voltage to the first input port of the error operational amplifier;
and further comprising a second output stage, an input power detector connected to the first output stage and the second output stage, wherein,
the input power detector is configured to generate a first enable signal or a second enable signal by detecting whether a first voltage or a second voltage is provided;
the first output stage is configured to receive and regulate the first voltage upon receiving the first enable signal;
the second output stage is configured to receive and regulate the second voltage upon receiving the second enable signal;
an output port of the second output stage is connected to an output port of the first output stage;
an input port of the second output stage is connected to the output terminal of the error operational amplifier;
wherein the bandgap reference voltage generator is connected to output ports of the first output stage and the second output stage.
2. The power management system of claim 1, wherein the input power detector further comprises:
a comparator configured to determine whether an input voltage is the first voltage by comparing the input voltage with a second reference voltage;
the comparator is configured to output the first enable signal and a second disable signal if the input voltage is less than or equal to the second reference voltage;
the comparator is configured to output a second enable signal and a first disable signal if the input voltage is higher than the second reference voltage.
3. The power management system of claim 2, wherein the input power detector further comprises a first level shifter and a second level shifter, wherein the first level shifter and the second level shifter are connected to the output port of the comparator, the first level shifter is configured to output the first enable signal and the first disable signal, and the second level shifter is configured to output the second enable signal and the second disable signal.
4. The power management system of claim 2, wherein the first output stage further comprises a first PMOS, a second PMOS, a third PMOS, a fourth PMOS, a first NMOS,
a source of a first NMOS configured to receive an output of the error operational amplifier, a drain of the first NMOS connected to a drain and a gate of the second PMOS, a gate of the fourth PMOS, and a drain of the third PMOS, a source of the second PMOS connected to a drain of the first PMOS, a source of the first PMOS and a source of the third PMOS configured to receive the first voltage, a gate of the first PMOS configured to receive the first disable signal, a gate of the third PMOS configured to receive the first enable signal;
wherein a combination of the first PMOS, the second PMOS, the third PMOS, and the fourth PMOS is connected to an output port of a selector having a first input port connected to the first voltage and a second input port connected to the system output port;
wherein an input port of a startup circuit is configured to receive the first voltage and an output port of the startup circuit is connected to the system output port.
5. The power management system of claim 4, wherein the selector further comprises a fifth PMOS, a sixth PMOS, a seventh PMOS, an eighth PMOS, a ninth PMOS, and a tenth PMOS, wherein sources of the fifth PMOS, the sixth PMOS, and the ninth PMOS are configured to receive the first voltage; gates of the fifth, seventh, and tenth PMOSs are connected to a drain of the fifth PMOS transistor and a first current source, sources of the seventh, eighth, and tenth PMOSs are connected to the system output port, gates of the eighth, sixth, and ninth PMOSs are connected to a drain of the eighth PMOS and a second current source, and a drain of the ninth PMOS is connected to a drain of the tenth PMOS.
6. The power management system of claim 4 wherein the startup circuit further comprises an eleventh PMOS, a twelfth PMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a sixth NMOS;
wherein gates of the eleventh PMOS and the twelfth PMOS are connected to a drain of the eleventh PMOS and a drain of the second NMOS, sources of the eleventh PMOS and the twelfth PMOS and a drain of the fifth NMOS are configured to receive the first voltage, a drain of the twelfth PMOS is connected to a gate of the fifth NMOS, a drain and a gate of the fourth NMOS, a source of the fourth NMOS is connected to a drain and a gate of the sixth NMOS, and a source of the sixth NMOS is connected to a drain and a gate of the third NMOS.
7. The power management system of claim 2, wherein the second output stage further comprises a first PMOS, a second PMOS, a third PMOS, a fourth PMOS, and a first NMOS, wherein,
a source of the first NMOS configured to receive the output of the error operational amplifier, a drain of the first NMOS connected to drains and gates of all of the second PMOS, a gate of the fourth PMOS, and a source of the third PMOS, a source of the second PMOS connected to a drain of the first PMOS, a source of the first PMOS and a source of the third PMOS configured to receive the second voltage, a gate of the first PMOS configured to receive the second enable signal, a gate of the third PMOS configured to receive the second disable signal;
wherein a combination of the first PMOS, the second PMOS, the third PMOS, and the fourth PMOS is connected to an output port of a selector, a first input port of the selector is connected to the second voltage, and a second input port of the selector is connected to the system output port;
wherein an input port of a startup circuit is configured to receive the second voltage and an output port of the startup circuit is connected to the system output port.
8. The power management system of claim 7, wherein the selector further comprises a fifth PMOS, a sixth PMOS, a seventh PMOS, an eighth PMOS, a ninth PMOS, and a tenth PMOS, wherein sources of all of the fifth PMOS, the sixth PMOS, and the ninth PMOS are configured to receive the second voltage, gates of the fifth PMOS and the seventh PMOS are connected to a fifth PMOS transistor and a sixth PMOS transistor and a first current source, sources of the seventh PMOS, the eighth PMOS, and the tenth PMOS are connected to the system output port, gates of the eighth PMOS and the sixth PMOS are connected to drains of the eighth PMOS and the seventh PMOS and a second current source, and a drain of the ninth PMOS is connected to a drain of the tenth PMOS.
9. The power management system of claim 7 wherein the startup circuit further comprises an eleventh PMOS, a twelfth PMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a sixth NMOS,
wherein gates of the eleventh PMOS and the twelfth PMOS are connected to a drain of the eleventh PMOS and a drain of the second NMOS, sources of the eleventh PMOS and the twelfth PMOS, and a drain of the fifth NMOS are configured to receive the second voltage, a drain of the twelfth PMOS is connected to a gate of the fifth NMOS, a drain and a gate of the fourth NMOS are connected to a gate of the fifth NMOS, a source of the fourth NMOS is connected to a drain and a gate of the sixth NMOS, and a source of the sixth NMOS is connected to a drain and a gate of the third NMOS.
10. A method of power management, comprising the steps of:
receiving and regulating a first voltage through a first output stage connected to an input power detector;
comparing a first reference voltage and a divided voltage by an error operational amplifier, wherein a power supply terminal of the error operational amplifier is connected to a system output port, an output terminal of the error operational amplifier is connected to an output port of the first output stage, a first input port of the error operational amplifier is configured to receive the first reference voltage, a second input port of the error operational amplifier is connected to a connection point of a first resistor and a second resistor, the connection point outputting the divided voltage; the first resistor being connected to an output port of the first output stage, the second resistor being connected to ground, a system output port being located at the connection of the first resistor and the aforementioned output port of the first output stage,
wherein the method further comprises:
operating the error operational amplifier at a system output voltage through the system output port, wherein the system output voltage is lower than the first voltage; and
driving a load according to the system output voltage;
further comprising a bandgap reference voltage generator, wherein said bandgap reference voltage generator is connected to said error operational amplifier and configured to output said first reference voltage to said first input port of said error operational amplifier;
further comprising a second output stage, an input power detector connected to the first output stage and the second output stage, wherein the method further comprises:
generating, by the input power detector, a first enable signal or a second enable signal by detecting whether the first voltage or the second voltage is supplied;
receiving and regulating the first voltage by the first output stage upon receiving the first enable signal;
receiving and regulating the second voltage by the second output stage upon receiving the second enable signal; wherein,
an output port of the second output stage is connected to the output port of the first output stage;
an input port of the second output stage is connected to the output terminal of the error operational amplifier;
wherein the bandgap reference voltage generator is connected to output ports of the first output stage and the second output stage.
11. The power management method of claim 10, further comprising the steps of:
determining, by a comparator, whether an input voltage is the first voltage by comparing the input voltage with a second reference voltage;
outputting, by the comparator, the first enable signal and a second disable signal if the input voltage is less than or equal to the second reference voltage;
outputting a second enable signal and a first disable signal through the comparator if the input voltage is higher than the second reference voltage.
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