CN108319804A - A kind of 8192 bases, 2 DIT ASIC circuit design methods that low-resource calls - Google Patents
A kind of 8192 bases, 2 DIT ASIC circuit design methods that low-resource calls Download PDFInfo
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- CN108319804A CN108319804A CN201810341207.3A CN201810341207A CN108319804A CN 108319804 A CN108319804 A CN 108319804A CN 201810341207 A CN201810341207 A CN 201810341207A CN 108319804 A CN108319804 A CN 108319804A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The present invention relates to 8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource calls.（1）Calculate main body module：Based on 2 DIT thoughts of base, using state machine as main body, realize the description to DIT butterfly diagrams, and inside state machine by the way of blocking assignment, every level-one of DIT butterfly diagrams by two groups of register groups at, it when being realized with state machine, is converted according to weighted value using the data update between two groups of register groups, is made of real part and imaginary part in every group of register group back and forth；（2）Trigonometric function generation module：For generating trigonometric function, the trigonometric function calling after Fast Fourier Transform (FFT), Euler's transformation is carried out in order to calculate main body module.The present invention is called by the repetition between every grade of master register group in butterfly diagram, computation complexity is reduced, improves accuracy so that the accumulating value of error superposition is greatly lowered layer by layer in every grade of time domain selection process, it quickly realizes Fast Fourier Transform (FFT) time domain selection process, reaches and realize that low-resource calls.
Description
Technical field
The present invention relates to 8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource calls.
Background technology
In the current DSP Technology applications more and more frequent epoch, the importance of fast fourier transform algorithm design is also opened
Beginning attracts attention, and the quality of Fast Fourier Transform (FFT) is often a key factor of decision processor performance, and with calculation
The exploitation that method is used, Fast Fourier Transform (FFT) also receive favor in the treatment effect of image and video etc., not only exist
In daily life is used.The generation process of Fast Fourier Transform (FFT) determines its remarkable application status in terms of military project,
Filtering in terms of the processing of satellite-signal, audio signal also functions in denoising that radar signal receives etc. national defense construction
Vital status.Therefore for how more stably to realize the hardware circuit design about fast fourier transform algorithm
While, also to the resource transfer degree of circuit, more stringent requirements are proposed with speed speed.
The scheme of existing DIT design is various, it is contemplated that the sustainable multiplexing of the register in calculating process is to subtract
Whole system structure is more simplified to analyze the calculating tune for calculating weights at different levels in the calling and design process of few resource
With the structure calculated using butterfly diagram is clearly best selection.By investigation, in the mistake of most FFT designs before
Cheng Zhong, it is most of using piece external storage weighted value state to be called at any time for the small design for calculating point.And it calculates greatly
Point design again often use using e as the calculating of the exponential function of the truth of a matter, due to using e as the distributed process of the exponential function at bottom
Too high for the required precision of argument, when argument is close to 0, numerical transformation converges on 1, when argument is relatively large, obtains
Result of calculation often changes too greatly again, is difficult to reach the effect for obtaining result of calculation with extremely low resource in the design of digital circuit
Fruit, and the effect done so makes the evaluation precision after design calculating itself not high, and consumption largely calculates list
Member, when required precision is higher and higher, the resource of consumption just reaches a considerable stage.Therefore the design adopts herein
With the thinking of Software for Design, the advantages of extracting above two design method, the weight calculation during DIT is designed passes through Euler's formula
Transformation, be converted into the form of trigonometric function, obtain the result of calculation about real part and imaginary part respectively, in conjunction with the two calculating knot
Fruit, which is multiplied, obtains the result of plural number calculating.And for the design of trigonometric function, use CORDIC design methods and Thailand considering
After strangling the trigonometric function result of calculation after being unfolded, when the design is called with regard to trigonometric function, interior angle is within the same period
It is consistent, it is contemplated that between 0 to 180, the design uses for the symmetry of trigonometric function itself and the variation range of angle
Be look-up table after optimization, make about the result of variations between 90 degree of SIN function, then arrived 0 using SIN function
Symmetric relation between 180, the correspondence between SIN function and cosine function immediately arrive at later by simple conversion
The numerical value of calling, the relatively easy convenience of calculating process.
By the characteristic of base 2, compared to the design philosophy of base 4 and base 8, limitation of 2 design of base for calculating point itself
It is small, allocating register group repeatedly can be achieved the purpose that by butterfly diagram, reach and told as possible with extremely low resource consumption
8192 point DIT designs result.By investigation, most of design about the big calculating points of FFT now is substantially based oneself upon
In multi-core processor or high performance processor design, operation is carried out in the form of flowing water, this results in adjusting in calculating process
With a large amount of arithmetic elements and memory, the expense of power consumption has been had more.Therefore, the design is the case where ensureing the speed of service and precision
Under, optimization algorithm structure realizes that low-resource calls in a manner of state machine.
Invention content
The purpose of the present invention is to provide 8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource calls, and lead to
It crosses the repetition in butterfly diagram between every grade of master register group to call, reduces computation complexity, improve accuracy so that every grade of time domain
The accumulating value of error superposition is greatly lowered layer by layer in selection process, quickly realizes Fast Fourier Transform (FFT) time domain selection process,
Optimization design flow reaches and realizes that low-resource calls.
To achieve the above object, the technical scheme is that：A kind of 8192 bases, 2 DIT ASIC that low-resource calls
Circuit design method includes the design of following two parts module：
（1）The calculating main body module of calculation processing is designed for DIT：
The calculating main body module that calculation processing is designed for DIT is based on 2 DIT thoughts of base, using state machine as main body, realizes
Description to DIT butterfly diagrams, and inside state machine by the way of blocking assignment, every level-one of DIT butterfly diagrams is by two groups
Register group at, when being realized with state machine, converted back and forth according to weighted value using the data update between two groups of register groups,
It is made of real part and imaginary part in every group of register group；
（2）Trigonometric function generation module：
For generating trigonometric function, in order to calculate the triangle letter after main body module carries out Fast Fourier Transform (FFT), Euler's transformation
Number calls.
In an embodiment of the present invention, the DIT butterfly diagrams are 8192 point DIT butterfly diagrams.
In an embodiment of the present invention, the main body module that calculates for being used for DIT design calculation processings realizes the specific of DIT designs
Flow is as follows：
First to DIT butterfly diagrams series, each series in group corresponding timing point, the count number of total counting, with e be
The angle value of the trigonometric function of the exponential function argument at bottom initializes；When the first order butterfly diagram in DIT butterfly diagrams, read
Enter the calculated value of timing point, and 256 times are expanded to each numerical value, is i.e. each binary value moves to left 8, and what is read in herein is several
The real part of value, and need when first order butterfly diagram all to take 0 to the corresponding imaginary part of each real part, reading in real part
After imaginary part, the timing point per a small group according to location determination is needed, and inverted order is handled, and then calculates corresponding triangle letter
Several numerical value is added or subtracts each other to obtain the result of calculation for being one group with 2 timing points in first order butterfly diagram, after calculating
It needs complement code to be converted into true form deposit among register group, the calculating of first order butterfly diagram is completed with this, later regeneration class
Number, corresponding timing point in series group, total calculating count number, come as the exponential function argument at bottom using e three
The angle value of angle function starts the calculating of new round butterfly diagram；The mutual of the calculating of butterfly diagram, complement code and true form is repeated per level-one
After conversion, repeat to update initial value, cycle calculations deposit is until terminating.
Compared to the prior art, the invention has the advantages that：The present invention passes through every grade of master register in butterfly diagram
Repetition between group is called, and computation complexity is reduced, and improves accuracy so that error superposition layer by layer in every grade of time domain selection process
Accumulating value be greatly lowered, quickly realize Fast Fourier Transform (FFT) time domain selection process, optimization design flow, reach realize it is low
Resource transfer.
Description of the drawings
Fig. 1 is the 8192 point fft butterfly diagrams that the present invention uses.
Fig. 2 is resource transfer figure.
Fig. 3 is component register result.
Fig. 4 is initialization data figure.
Fig. 5 is result oscillogram.
Fig. 6 is fit indices functional arrangement.
Fig. 7 is design flow diagram.
Specific implementation mode
Below in conjunction with the accompanying drawings, technical scheme of the present invention is specifically described.
8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource of the present invention calls, including following two parts
The design of module：
（1）The calculating main body module of calculation processing is designed for DIT：
The calculating main body module that calculation processing is designed for DIT is based on 2 DIT thoughts of base, using state machine as main body, realizes
Description to DIT butterfly diagrams, and inside state machine by the way of blocking assignment, every level-one of DIT butterfly diagrams is by two groups
Register group at, when being realized with state machine, converted back and forth according to weighted value using the data update between two groups of register groups,
It is all made of real part and imaginary part in every group of register group；
（2）Trigonometric function generation module：
For generating trigonometric function, in order to calculate the triangle letter after main body module carries out Fast Fourier Transform (FFT), Euler's transformation
Number calls.
The DIT butterfly diagrams are 8192 point DIT butterfly diagrams（As shown in Figure 1）.
The main body module that calculates that calculation processing is designed for DIT realizes that the detailed process of DIT designs is as follows：
First to DIT butterfly diagrams series, each series in group corresponding timing point, the count number of total counting, with e be
The angle value of the trigonometric function of the exponential function argument at bottom initializes；When the first order butterfly diagram in DIT butterfly diagrams, read
Enter the calculated value of timing point, and 256 times are expanded to each numerical value, is i.e. each binary value moves to left 8, and what is read in herein is several
The real part of value, and need when first order butterfly diagram all to take 0 to the corresponding imaginary part of each real part, reading in real part
After imaginary part, the timing point per a small group according to location determination is needed, and inverted order is handled, and then calculates corresponding triangle letter
Several numerical value is added or subtracts each other to obtain the result of calculation for being one group with 2 timing points in first order butterfly diagram, after calculating
It needs complement code to be converted into true form deposit among register group, the calculating of first order butterfly diagram is completed with this, later regeneration class
Number, corresponding timing point in series group, total calculating count number, come as the exponential function argument at bottom using e three
The angle value of angle function starts the calculating of new round butterfly diagram；The mutual of the calculating of butterfly diagram, complement code and true form is repeated per level-one
After conversion, repeat to update initial value, cycle calculations deposit is until terminating.
It is the specific implementation process of the present invention below.
The method of the present invention relates generally to three modules composition, call random function generate the module about 8192 test points,
Main body module, the trigonometric function generation module of calculation processing are designed for DIT.It is to call to generate about the module of 8192 test points
SYSTEM VERILOG in random function generate, not counting during entire ASIC circuit designs, only bring verification
The accuracy of the result of algorithm and provide an access about data-processing interface for circuit.Before it is many about
In the engineering of FFT designs, the classification butterfly diagram that FFT is designed calculates so that stream treatment is relatively to be not suitable in FFT designs.One
As using each classification of parallel processing partial results, the drawbacks of handle COMPREHENSIVE CALCULATING again later, having done so is
This way is usually sub-module execution parallel procedure, and before this parallel processing, it can be inputted there are one mass data
Clock consumes the data transmission period after stand-by period, and data receiver.For small calculating point, need not be located parallel
Reason process, and for big calculating point, the later stage to be the result of calculation after parallel modules access data output to seem again
Logical construction is excessively intricate.For the considerations of simplifying to logical construction in classification calculating process, the design uses here
State machine realize serial process effect, due in state machine to DIT butterfly diagrams description present configuration process more
It is clear, reduce the complexity in design process.During design, when adoption status machine designs, in order to enable circuit
As a result supplement and the linking that subsequent step can be obtained in time, inside state machine by the way of blocking assignment, great Liang Jie
The about clock of state machine internal calculation consumption so that the register group of docking is able to transmit numerical value and erasing original number in time
According to, data transfer balances between achieving the effect that register group, most importantly, after transmitting data, original registers
The possessed data of group are just in useless state, we can be reached using this component register group between register group in time
Data newer mode mutually, and per level-one in per a small group in two calculate between point be can be in a state machine clock
Inside reach this effect.
Fast Fourier Transform (FFT) is one that the signal for the domain portion that original signal is possessed changes to frequency domain part
Process：
During Fast Fourier Transform (FFT), for using e as the exponential function multiplier part at bottom, the design passes through Euler's formula
Conversion, the plural form of exponential function is changed into the plural form of trigonometric function form, be able to isolate real part with
And it is hidden in using e as the data of the imaginary part of the exponential function at bottom, the following institute of a form of specific Euler's formula conversion
Show：
Calculate using e as the exponential function data at bottom when, if calculating, in digital circuit if by Taylor expansion
If, it is simulated by matlab softwares, when needing to be deployed into the 10th, Taylor expansion, which can be only achieved, to be fitted with original function
Effect, when being deployed into the 5th, numerical value causes error gradually to increase as index improves.Function trend is illustrated in fig. 6 shown below.
With matlab to the Taylor expansion of the exponential function using e the bottom of as to the 5th when with the 10th when formula it is as follows：
So when using Taylor expansion, it is very big for the accuracy requirement of the fractional part of evaluation, and calculate
The positive and negative transformation of variables calculating of complexity and raw value institute band needs to be converted into complement form in digital circuit, substantially increases
The difficulty of design, reduces the accuracy of data.So just having embodied herein triangle letter is converted into using Euler's formula
The importance of number process, substantially increases the accuracy of data, reduces the accumulation of error in iterative process, reduce circuit and set
The complexity of meter.
In design DIT（The time domain of Fast Fourier Transform (FFT) is selected）When, the design has been used here when DSP designs FFT
Butterfly diagram in the selection of domain, carries out DIT designs with more intuitively more having levels, and with the raising of level series, can
Conveniently and efficiently to obtain the corresponding numerical computations of series in weight.
It calls random function to generate in global design and mainly calls random data life about the module of 8192 test points
At function the data of 8192 point DIT designs are set, then after can be there are two types of method of calling.One is directly pass through IO
Mouth input 8192 point datas input, one is directly write in this engineering when original initialization input data generates
In txt texts, this txt text is called to read in data in body design module, in storage to register group.Herein in order to make
Its last digital circuit can integrate, and while generating txt documents, not do the function called about text temporarily in main body module
It reads in, 8192 point datas is read in using I/O port.As shown in the initialization data generation in attached drawing 4.
After trigonometric function calls the module of data to be mainly reflected in and converted by Euler's formula, answering for trigonometric function is utilized
Number form formula marks off real part and imaginary part, will directly be calculated by the plural form of the exponential function at bottom of e, becomes more simple real
Calculating between portion and real part, imaginary part and imaginary part, between real part and imaginary part, last data preparation is at real part and imaginary part two
Point.The SIN function of this part trigonometric function can be arrived with cosine function by transferring the 0 of sine function in simple transformation
Data between 90 degree differentiate that positive negative transfers numerical value later, look-up table are used here, in conjunction with trigonometric function formula, by sinusoidal letter
It is averagely divided according to the result of SIN function between number 0 to 90, stores trigonometric function value.
Since the DIT main body module main bodys for designing calculation processing are realized using state machine, in the realization work of state machine
Cheng Zhong, the obstruction assignment of use, substantial saved due to non-calculating and the synchronised clock assignment problem for renting plug assignment and caused by
Mass data transfers the deposit that storage stationary problem is calculated in non-obstruction assignment in clock waiting and logic design process
Device group wastes.When being realized with state machine, the main data update using between two groups of register groups becomes according to weighted value back and forth
It changes, is made of real part and imaginary part in every group of register group.Real part and imaginary part separate computations, are combined with each other, cause in the calculation
The two needs, which synchronize, to be updated, and unborn data are wiped.Why can back and forth be updated the data with two groups of register groups
Without causing big waste, the base 2 DIT designs that mainly we use, so being all with two between every grade for one group of synchronization
It is newer, do not have to consider other extra situations, each register group among every level-one only needs update primary, by layer by layer
The relationship of superposition reaches the demand of last each data and the calculating of other all data.
The design of whole DIT is corresponding in group to series, each series first as shown in 7 design flow diagram of attached drawing
Timing point, the count number of total calculating, the angle value of the trigonometric function to come using e as the exponential function argument at bottom are initial
Change, when the first order in butterfly diagram, reads in the calculated value for calculating point, 256 times are expanded to each numerical value here, that is, often
One binary value moves to left 8, and what is read in here is the real part of numerical value, and is needed to each when first order butterfly diagram
The corresponding imaginary part of a real part all takes 0, this is because when starting to calculate, for ease of calculation with the mistake of writing design circuit
The real-time simple authentication to register group in journey judges design result, so even if the imaginary part merging imaginary number in this level-one goes to count
It calculates, it is if certain part that this entire 8192 points DIT as some n*8192 point are designed and feasible.It is reading in
After real part and imaginary part, the calculating point per a small group according to location determination is needed, it is assumed here that have passed through inverted order in advance, count
The numerical value for calculating corresponding trigonometric function is added or subtracts each other to obtain to be calculated by 2 in first order butterfly diagram and put in terms of for one group
It calculates as a result, during calculating addition or subtracting each other, it should be noted that the presence of signed number, since the calculating of signed number is opposite
The item paid attention to is relatively more, be easy to cause chaos in computation, so achievableization of the convenience and algorithm for design, manually every
The leftmost binary number set symbol number of one number will consider the symbol problem of result when so being not only multiplied, for cannot
It determines the numerical value for calculating symbol, needs that true form is first converted into complement code calculating, avoid chaos in computation.It is needed after calculating benefit
Code is converted among true form deposit to register group, and the calculating of the first order is completed with this, and it is right in series, series group to update later
The count number of the timing point, total calculating answered, using the angle value of the e trigonometric functions to come as the exponential function argument at bottom,
Start the calculating of new round butterfly diagram.It converts, protect with numerical value since the calculating of every level-one butterfly diagram will pass through a large amount of calculating
It deposits, so the calculating per level-one will expend a large amount of computing resource and register group.Here namely it is proposed that low-resource
The big meaning for calculating point DIT circuits of design.The calculating of butterfly diagram, complement code and true form are repeated per level-one mutually converts it
Afterwards, update initial value is repeated, cycle calculations deposit is until terminating.
For the simulation result that entirely designs as shown in the oscillogram of Fig. 5, this oscillogram shows in design process
Waveform of the part signal called during entire circuit simulation.In the case of big calculating point, design and operation is answered
Miscellaneous degree is directly proportional to 2 exponential size, and for the design in the case of high complexity, global design simulation time is 1.8 millis
Second, subtract 0.2 millisecond of the time of the assignment initialization institute expense to internal register at first, the time of entire circuit operation
It it is 1.6 milliseconds, the fundamental clock frequency of circuit access is 100MHz.Simulation results show that the algorithm circuit of this optimization exists
Under the premise of low-resource calls, the effect of high-speed cruising is had also achieved.The simulation result of circuit includes the calculating of register section
It is worth size, the simulation result of this part is as shown in figure 3, the evaluation of component register is shown in Fig. 3, by entire electricity
After the operation on road, result is divided into real part and is deposited with imaginary part two parts.By the algorithm after optimization for circuit accuracy
There is larger promotion, be real part data shown in Fig. 3 in this design, each numerical value in a register is expanded according to 256 times
To ensure after the algorithm of optimization, the numerical value of decimal is not intercepted its size.Ensure that the error after multiple Iterative calculation method subtracts
It is small.
This design is with low-resource calling for main design direction.By to algorithm improvement and to the excellent of circuit structure
Change, to reach the target of low-resource calling.As shown in Fig. 2, the resource run out of after the design is comprehensive in VIVADO softwares uses
Situation.It is that chip model shows Slice LUTs for xc7vx485tffg1157-1, wherein VIVADO used in entire design
131 are used, a unit accounts for the 0.04% of sum.Slice Registers have used 0.03%, have used 195 units.It is whole
A design occupies 600 Nets, 419 Leaf Cells.In this design, circuit resource high recycling rate saves resource
Hardware spending, the cycle of operation are short.
The above are preferred embodiments of the present invention, all any changes made according to the technical solution of the present invention, and generated function is made
When with range without departing from technical solution of the present invention, all belong to the scope of protection of the present invention.
Claims (3)
1. 8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource calls, which is characterized in that including following two
The design of sub-module：
（1）The calculating main body module of calculation processing is designed for DIT：
The calculating main body module that calculation processing is designed for DIT is based on 2 DIT thoughts of base, using state machine as main body, realizes
Description to DIT butterfly diagrams, and inside state machine by the way of blocking assignment, every level-one of DIT butterfly diagrams is by two groups
Register group at, when being realized with state machine, converted back and forth according to weighted value using the data update between two groups of register groups,
It is made of real part and imaginary part in every group of register group；
（2）Trigonometric function generation module：
For generating trigonometric function, in order to calculate the triangle letter after main body module carries out Fast Fourier Transform (FFT), Euler's transformation
Number calls.
2. 8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource according to claim 1 calls, special
Sign is that the DIT butterfly diagrams are 8192 point DIT butterfly diagrams.
3. 8192 bases, the 2 DIT ASIC circuit design methods that a kind of low-resource according to claim 2 calls, special
Sign is that the main body module that calculates for DIT design calculation processings realizes that the detailed process of DIT designs is as follows：
First to DIT butterfly diagrams series, each series in group corresponding timing point, the count number of total counting, with e be
The angle value of the trigonometric function of the exponential function argument at bottom initializes；When the first order butterfly diagram in DIT butterfly diagrams, read
Enter the calculated value of timing point, and 256 times are expanded to each numerical value, is i.e. each binary value moves to left 8, and what is read in herein is several
The real part of value, and need when first order butterfly diagram all to take 0 to the corresponding imaginary part of each real part, reading in real part
After imaginary part, the timing point per a small group according to location determination is needed, and inverted order is handled, and then calculates corresponding triangle letter
Several numerical value is added or subtracts each other to obtain the result of calculation for being one group with 2 timing points in first order butterfly diagram, after calculating
It needs complement code to be converted into true form deposit among register group, the calculating of first order butterfly diagram is completed with this, later regeneration class
Number, corresponding timing point in series group, total calculating count number, come as the exponential function argument at bottom using e three
The angle value of angle function starts the calculating of new round butterfly diagram；The mutual of the calculating of butterfly diagram, complement code and true form is repeated per level-one
After conversion, repeat to update initial value, cycle calculations deposit is until terminating.
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