CN108319453A - A kind of algorithm configuration software design approach based on FPGA control logics - Google Patents
A kind of algorithm configuration software design approach based on FPGA control logics Download PDFInfo
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- CN108319453A CN108319453A CN201711384293.8A CN201711384293A CN108319453A CN 108319453 A CN108319453 A CN 108319453A CN 201711384293 A CN201711384293 A CN 201711384293A CN 108319453 A CN108319453 A CN 108319453A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/20—Software design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
Abstract
The invention belongs to nuclear power station DCS digital monitorings and protection technique field, and in particular to a kind of algorithm configuration software design approach based on FPGA control logics.The present invention provides a kind of algorithm configuration software design approach based on FPGA control logics, to the integrated debugging development environment applied to nuclear power station controller algorithm control logic, a series of functions such as management, off-line simulation, in-service monitoring, the controls of models such as algorithm configuration, algorithms library, variable are realized.
Description
Technical field
The invention belongs to nuclear power station DCS digital monitorings and protection technique field, and in particular to one kind is controlled based on FPGA
The algorithm configuration software design approach of logic.
Background technology
In nuclear power station security level DCS Digitizing And Control Units, each control station needs to be realized according to preset algorithm
Various control relay protective schemes, the algorithm configuration tool that these relay protective schemes need utilizing works teacher to stand carry out the configuration of logic, together
When need that these algorithm logics are debugged and monitored.
FBD (Function Block Diagram) Function Block Diagram refers to a kind of patterned programming language, excessively program-controlled
Field processed be widely used and IEC 61131-3 specifications in one of five kinds of programming languages.
The operations such as FBD is a kind of visible language, and user can be dragged by mouse, be dragged, with the plain mode that plays with building blocks into
The algorithm requirement of project operation can be completed without complicated programming process for the graphical configuration of row algorithm control logic.Cause
This, there is an urgent need for develop a kind of host computer application software based on FPGA control algolithms.
Invention content
The technical problem to be solved in the present invention is to provide a kind of algorithm configuration Software for Design sides based on FPGA control logics
Method, to applied to nuclear power station controller algorithm control logic integrated debugging development environment, realize algorithm configuration, algorithms library,
A series of functions such as management, off-line simulation, in-service monitoring, the control of the models such as variable.
In order to realize the purpose, the technical solution adopted by the present invention is that：
A kind of algorithm configuration software design approach based on FPGA control logics, including following aspect：
1) Function Block specified in algorithm configuration software reference PLC Logical Configurations IEC61131-3 standards
Diagram realizes the graphical configuration of algorithm logic, realizes the management to algorithm map sheet, variable, algorithms library；
2) algorithm configuration software is only responsible for realizing the encapsulation and definition of algorithm logic, the reality of not responsible specific algorithm logic
Existing, the realization of specific algorithm logic is realized by algorithm performs device of the programming in FPGA and algorithmic block；
3) according to the logic generating algorithm mapped file of graphical algorithm configuration, by variable reference, the calculation in algorithm configuration
Method block example and line are converted into the binary map file that FPGA algorithm performs devices can recognize that and execute, and according to this document
Data content adds the header packet information of maintenance agreement, generates the download file of controller；
4) by customized link layer communication protocols, network interface card is written and read by trawl performance and realizes that algorithm logic reflects
The lower dress penetrated and the monitoring under controller service mode, control debugging function；
5) the interface mappings relationship for the Algorithm mapping file reflection algorithm logic that host computer is generated, passes through FPGA controller
Realize the algorithm.
The advantageous effect of technical solution of the present invention is：
1) the graphical configuration of functional block based on FPGA does not need the ability that user has programming；
2) algorithm configuration and variable configuration integrated, variable is managed collectively by variable manager, need not be in algorithm configuration
Defined variable reduces workload, makes Project Configuration with the integrated and appropriate encapsulation of entire DCS system engineer station general control software
By once.
Using technical solution of the present invention NicSys8000N platforms algorithm configuration function with it is traditional based on PLC or
ARM, POWERPC etc. are using generation programming code after upper computer software programming and pass through cross-compiler compiling and then lower dress
Different to the scheme in controller CPU, the former is the algorithm logic realized by host computer and code building and compiling, therein
Process, which has, to be not easy to realize, it is difficult to prove safety, the feature of real-time difference.
This system is an advantage bright spot of entire Logical Design Scenarios so that the design of algorithm logic can not only pass through
Patterned mode is easily realized and is debugged in host computer, and algorithm logic is made to realize and execute all in the controller
It carries out, improves the reliability and efficiency of system, low verification cost.
Specific implementation mode
Technical solution of the present invention is described in detail with reference to specific embodiment.
A kind of algorithm configuration software design approach based on FPGA control logics of the present invention, including following aspect：
1) Function Block specified in algorithm configuration software reference PLC Logical Configurations IEC61131-3 standards
Diagram realizes the graphical configuration of algorithm logic, realizes the management to algorithm map sheet, variable, algorithms library；
2) algorithm configuration software is only responsible for realizing the encapsulation and definition of algorithm logic, the reality of not responsible specific algorithm logic
Existing, the realization of specific algorithm logic is realized by algorithm performs device of the programming in FPGA and algorithmic block；
3) according to the logic generating algorithm mapped file of graphical algorithm configuration, by variable reference, the calculation in algorithm configuration
Method block example and line are converted into the binary map file that FPGA algorithm performs devices can recognize that and execute, and according to this document
Data content adds the header packet information of maintenance agreement, generates the download file of controller；
4) by customized link layer communication protocols, network interface card is written and read by trawl performance and realizes that algorithm logic reflects
The lower dress penetrated and the monitoring under controller service mode, control debugging function；
5) the interface mappings relationship for the Algorithm mapping file reflection algorithm logic that host computer is generated, passes through FPGA controller
Realize the algorithm.
Above-mentioned technical proposal can be applied to algorithm logic design configuration, off-line simulation debugging, the dimension at field engineer station
The tool software of monitoring is protected, realizes the integrated of following several big functions：
1. patterned algorithm configuration editing machine.
2. the tree-like hierarchical structure management of control station algorithm engineering, algorithms library, variable
3. by host computer generating algorithm configuration to the driving mapping relations of FGPA algorithm logics；
It is being emulated and patterned monitoring and brute-force algorithm logic and its data under on-line mode 4. realizing；
5. pair algorithm logic completed carries out the miscellaneous functions such as filing and the printing of engineering drawing；
6. follow the specification of IEC61131-3, while the characteristics of according to the concrete condition and FPGA controller of application scenarios,
It can either realize the higher and complicated algorithm logic of real-time, and eliminate more complex multitask, local variable, it is self-defined
The characteristics such as POU, realize customized, reduce the complexity of system and the probability of error, improve entire algorithm logic
Reliability, safety and execution efficiency.
Claims (1)
1. a kind of algorithm configuration software design approach based on FPGA control logics, which is characterized in that including following aspect：
1) Function Block Diagram specified in algorithm configuration software reference PLC Logical Configurations IEC61131-3 standards
It realizes the graphical configuration of algorithm logic, realizes the management to algorithm map sheet, variable, algorithms library；
2) algorithm configuration software is only responsible for realizing the encapsulation and definition of algorithm logic, the realization of not responsible specific algorithm logic, tool
The realization of body algorithm logic is realized by algorithm performs device of the programming in FPGA and algorithmic block；
3) according to the logic generating algorithm mapped file of graphical algorithm configuration, by the variable reference in algorithm configuration, algorithmic block
Example and line are converted into the binary map file that FPGA algorithm performs devices can recognize that and execute, and according to the data of this document
Content adds the header packet information of maintenance agreement, generates the download file of controller；
4) by customized link layer communication protocols, network interface card is written and read by trawl performance and realizes algorithm logic mapping
Lower dress and the monitoring under controller service mode, control debugging function；
5) the interface mappings relationship for the Algorithm mapping file reflection algorithm logic that host computer is generated, is realized by FPGA controller
The algorithm.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109558163A (en) * | 2018-11-09 | 2019-04-02 | 中国核动力研究设计院 | A kind of version generation and management method based on operating file in controller |
| CN109976723A (en) * | 2019-03-12 | 2019-07-05 | 北京国电智深控制技术有限公司 | A kind of algorithm development platform, algorithm development method and computer readable storage medium |
| CN110519892A (en) * | 2019-09-27 | 2019-11-29 | 中山新驱动电子科技有限公司 | A kind of control method and system of ZigBee-network |
| CN112363975A (en) * | 2020-10-27 | 2021-02-12 | 国核自仪系统工程有限公司 | Interaction method and interaction system for configuration software and FPGA |
| CN113433905A (en) * | 2021-06-23 | 2021-09-24 | 华能山东石岛湾核电有限公司 | Voltage-reduction rate calculation logic configuration structure, method and system |
| CN113688037A (en) * | 2021-08-19 | 2021-11-23 | 上海核工程研究设计院有限公司 | Nuclear power plant instrument control system software configuration debugging and packaging integrated method |
| CN114115840A (en) * | 2021-11-10 | 2022-03-01 | 中国核动力研究设计院 | Variable skipping method and device for nuclear power station DCS system application software |
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| CN109558163A (en) * | 2018-11-09 | 2019-04-02 | 中国核动力研究设计院 | A kind of version generation and management method based on operating file in controller |
| CN109976723A (en) * | 2019-03-12 | 2019-07-05 | 北京国电智深控制技术有限公司 | A kind of algorithm development platform, algorithm development method and computer readable storage medium |
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| CN112363975A (en) * | 2020-10-27 | 2021-02-12 | 国核自仪系统工程有限公司 | Interaction method and interaction system for configuration software and FPGA |
| CN112363975B (en) * | 2020-10-27 | 2024-02-06 | 国核自仪系统工程有限公司 | Interaction method and interaction system for configuration software and FPGA |
| CN113433905A (en) * | 2021-06-23 | 2021-09-24 | 华能山东石岛湾核电有限公司 | Voltage-reduction rate calculation logic configuration structure, method and system |
| CN113433905B (en) * | 2021-06-23 | 2022-08-02 | 华能山东石岛湾核电有限公司 | Voltage-reduction rate calculation logic configuration structure, method and system |
| CN113688037A (en) * | 2021-08-19 | 2021-11-23 | 上海核工程研究设计院有限公司 | Nuclear power plant instrument control system software configuration debugging and packaging integrated method |
| CN114115840A (en) * | 2021-11-10 | 2022-03-01 | 中国核动力研究设计院 | Variable skipping method and device for nuclear power station DCS system application software |
| CN114115840B (en) * | 2021-11-10 | 2024-04-23 | 中国核动力研究设计院 | Variable jump method and device for nuclear power station DCS system application software |
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