CN108305835A - Method for manufacturing fin type transistor device - Google Patents
Method for manufacturing fin type transistor device Download PDFInfo
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- CN108305835A CN108305835A CN201810223692.4A CN201810223692A CN108305835A CN 108305835 A CN108305835 A CN 108305835A CN 201810223692 A CN201810223692 A CN 201810223692A CN 108305835 A CN108305835 A CN 108305835A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title abstract description 21
- 239000000463 material Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 130
- 239000000758 substrate Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 239000012212 insulator Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004156 TaNx Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a method for manufacturing a fin type transistor device. Because the first epitaxial layer is made of a material different from that of the second epitaxial layer, the first epitaxial layer and the second epitaxial layer have etching selectivity, and the first epitaxial layer is used as an etching stop layer in the etching process of forming the fin, so that the formed fin can be stopped on the first epitaxial layer, the etching depth is effectively controlled, the height of the fin is controllable, and the uniformity of the fin is improved.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, more particularly to a kind of manufacturer of fin transistor device
Method.
Background technology
With the continuous development of the technology of integrated circuit, the characteristic size of device constantly reduces, and integrated level is continuously improved, by
It is more notable in short-channel effect, become the leading factor for influencing device performance, traditional planar device is difficult to be further continued for reducing
Size.
At present, it is proposed that the three-dimensional device architecture of fin transistor device (FIN-FET), Fin-FET are with fin ditch
The transistor of road structure, it is using several surfaces of thin fin as raceway groove, so as to prevent the short channel in conventional transistor
Effect, while operating current can be increased.
In the formation process of fin transistor device, fin is formed by etched substrate, and it is continuous with the density of fin
Increase so that etching technics is also increasingly difficult to control, and causes the height for etching skeg not easy to control, there are uneven for the height of fin
Property so that the leakage current between fin is uncontrollable.
Invention content
In view of this, the purpose of the present invention is to provide a kind of manufacturing method of fin transistor device, fin is effectively controlled
Height, improve the uniformity of fin.
To achieve the above object, the present invention has following technical solution：
A kind of manufacturing method of fin transistor device, including：
Semiconductor substrate is provided；
First epitaxial layer of epitaxial growth of semiconductor material on the semiconductor substrate；
The second epitaxial layer of epitaxial growth of semiconductor material on first epitaxial layer, first epitaxial layer have same
The different material of second epitaxial layer；
Using first epitaxial layer as etching stop layer, second epitaxial layer is etched, to form fin；
Isolation structure is formed between the fin, and forms grid on the fin.
Optionally, after the fins are formed, formed isolation structure before, further include：
Remove the first epitaxial layer of the fin both sides；
The first epitaxial layer under the fin is oxidized to oxygen buried layer.
Optionally, the first epitaxial layer under the fin is oxidized to oxygen buried layer, including：
Protective layer is formed on the side wall of the fin；
Oxidation technology is carried out, forms surface oxide layer in the substrate surface of the fin surface and exposure, and will be described
The first epitaxial layer under fin is oxidized to oxygen buried layer；
Remove the surface oxide layer and the protective layer.
Optionally, the thickness of first epitaxial layer is 2-20 nanometers.
Optionally, the thickness of second epitaxial layer is 50-500 nanometers.
Optionally, the semiconductor substrate and second epitaxial layer have identical material.
Optionally, the semiconductor substrate is silicon substrate, and second epitaxial layer is epitaxial silicon, and first epitaxial layer is
Germanium silicon.
Optionally, grid is formed on the fin, including：
The false grid on the fin are formed at the middle part of the fin；
Side wall is formed on the side wall of the false grid；
Source-drain area is formed in the fin of the false grid both sides；
Form the interlayer dielectric layer of covering two lateral fin of the false grid；
The false grid of removal, to form opening；
Alternative gate is formed in the opening.
Optionally, the alternative gate includes high K medium material and metal gate electrode thereon.
The manufacturing method of fin transistor device provided in an embodiment of the present invention, is epitaxially grown on the substrate the first extension
Layer, then the second epitaxial layer of epitaxial growth then etches the second epitaxial layer on the first epitaxial layer, forms fin.Outside first
Prolonging layer has the material different from the second epitaxial layer so that and the two has Etch selectivity, in the etching process for forming fin, with
First epitaxial layer is etching stop layer, in this way, the fin to be formed can be made all to stop on the first epitaxial layer, effectively control etches
Depth so that fin it is highly controllable, to, improve the uniformity of fin.
It is possible to further further be etched to the first epitaxial layer, oxygen is buried to be formed between fin and substrate
Layer, in order to formed complete depletion type ETSOI fin transistor device, improve the performance of device
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the flow chart of the manufacturing method of fin transistor device according to the ... of the embodiment of the present invention；
Fig. 2-8 shows that the device architecture formed in fin transistor device process according to the method for the embodiment of the present invention cuts open
Face schematic diagram.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented different from other manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, three-dimensional space that should be comprising length, width and depth in actual fabrication.
As the description in background technology, in the formation process of fin transistor device, formed by etched substrate
Fin, and as the density of fin constantly increases so that etching technics is also increasingly difficult to control, and causes the height for etching skeg not easily-controllable
System, there are inhomogeneities for the height of fin so that the leakage current between fin is uncontrollable.
For this purpose, present applicant proposes a kind of manufacturing method of fin transistor device, it is epitaxially grown on the substrate outside first
Prolong layer, then the second epitaxial layer of epitaxial growth then etches the second epitaxial layer on the first epitaxial layer, forms fin.Due to first
Epitaxial layer has the material different from the second epitaxial layer so that and the two has Etch selectivity, in the etching process for forming fin,
Using the first epitaxial layer as etching stop layer, in this way, the fin to be formed can be made all to stop on the first epitaxial layer, effectively control is carved
Lose depth so that fin it is highly controllable, to, improve the uniformity of fin.
The technical solution and technique effect of the application in order to better understand, below with reference to flow chart Fig. 1 and attached drawing 2-8
Specific embodiment is described in detail, wherein attached drawing 2-8 be in each manufacturing process device along the section of fin width direction
Schematic diagram.
Refering to what is shown in Fig. 1, in step S01, semiconductor substrate 100 is provided, with reference to shown in figure 2.
In embodiments of the present invention, semiconductor substrate 100 can be Si substrates, Ge substrates, SiGe substrate, SOI (insulators
Upper silicon, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc..In other realities
It applies in example, the semiconductor substrate can also be the substrate for including other elements semiconductor or compound semiconductor, such as GaAs,
InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (insulators
Upper germanium silicon) etc..
In the present embodiment, the semiconductor substrate 100 is body silicon substrate, as shown in Figure 2.
In step S02, first epitaxial layer 110 of epitaxial growth of semiconductor material in the semiconductor substrate 100, reference
Shown in Fig. 3.
In step S03, second epitaxial layer 120 of epitaxial growth of semiconductor material, described on first epitaxial layer 110
First epitaxial layer 110 has the material different with second epitaxial layer 120, with reference to shown in figure 3.
In embodiments of the present invention, the second epitaxial layer is used to form fin, and the first epitaxial layer is that the second epitaxial layer of etching is formed
Etching stop layer when fin, the first epitaxial layer and the second epitaxial layer can be formed by epitaxial growth technology (EPI), it is ensured that
The second epitaxial layer formed has preferable crystal orientation, can form the fin of high quality.First epitaxial layer 110 and the second epitaxial layer
120 be different semi-conducting materials, so that having Etch selectivity therebetween.
It in a particular application, can be according to different substrate materials, the first and second extensions of growth selection suitable material
Layer, so that formation and the first epitaxial layer that the second epitaxial layer can be as fin can be used as etching stop layer.It can be according to specific
The thickness for needing that they are arranged, in some applications, the thickness range of the first epitaxial layer can be about 2-20 nanometers, second
The thickness range of epitaxial layer can be about 50-500 nanometers.
In the present embodiment, first epitaxial layer 110 is epitaxial Germanium silicon (GxS1-x, 0 ＜ x ＜ 1), second extension
Layer 120 is epitaxial silicon, and germanium silicon and silicon have close crystal orientation, convenient for forming the epitaxial silicon of good quality, for the formation of fin,
And there is preferable Etch selectivity with silicon.
It is etching stop layer with first epitaxial layer 110 in step S04, second epitaxial layer 120 is etched, with shape
At fin 122, with reference to shown in figure 4.
During etching the second epitaxial layer 120, using the first epitaxial layer as etching stop layer, that is to say, that outside second
Prolong the etching stopping of layer on the first epitaxial layer, in this way, the height of the fin formed is all essentially the thickness of the second epitaxial layer, effectively
Ground controls etching depth so that fin it is highly controllable, to, improve the uniformity of fin.
In specific application, mask layer (not shown) can be first formed on the second epitaxial layer 120, using every different
Property etching, such as method that RIE (reactive ion etching) may be used carries out the etching of the second epitaxial layer 120, when etching into the
When one epitaxial layer, stop etching.
In more preferably embodiment, the second epitaxial layer 120 can also further be etched, so as in fin and substrate
Between form oxide skin(coating), to, formed oxygen buried layer, in order to form ETSOI (the eltra thin Silicon of complete depletion type
On insulator) fin transistor device, improve the performance of device.
In this preferred embodiment, the thickness of the first epitaxial layer 110 can be able to be 2- in 2-20nm, more preferably
5nm, formed oxygen buried layer the step of may include：
First, the first epitaxial layer 120 of 122 both sides of the fin is removed with reference to shown in figure 5.
The first epitaxial layer 120 of dry or wet etch removal fin 122 both sides may be used, only retain the under fin 120
One epitaxial layer 112.
In the present embodiment, the first epitaxial layer 120 of acetic acid mixed solution removal 122 both sides germanium silicon of fin may be used.
Then, the first epitaxial layer 112 under the fin 122 is oxidized to oxygen buried layer 114, with reference to shown in figure 6.
Oxidation technology can be first carried out, after oxidation, the first epitaxial layer complete oxidation under the fin buries to be formed
Oxygen layer, meanwhile, the substrate surface of fin surface and exposure can also be aoxidized, and surface oxide layer is formed.Later, acid solution can be passed through
It is rinsed, such as hydrofluoric acid, removes surface oxide layer, to form oxygen buried layer 112 between fin 122 and substrate 100.It is logical
The thickness and oxidization time for crossing the first epitaxial layer of control, can form sufficiently thin oxygen buried layer 122, in order to form fully- depleted
The fin transistor device of the ETSOI (eltra thin Silicon on insulator) of type, improves the performance of device.
More preferably, before carrying out oxidation technology, protective layer can be formed on the sidewall of the fins, can be adopted in the present embodiment
The protective layer of one layer of silicon nitride is deposited with the mode of CVD, then carries out dry etching, top and bottom is exposed, to
The protective layer of silicon nitride is only formed on the sidewall of the fins, and oxidation technology subsequent in this way can not consume the side wall of fin, aoxidize
After technique, protective layer can be removed with hot phosphoric acid.
So far, it is formed the fin of the embodiment of the present invention, passes through highly controllable, the uniformity of fin for the fin that this method is formed
It is good, ultra-thin oxygen buried layer can also be further formed, later, can be as needed, select suitable technique to form it on fin
His device architecture.
In step S05, isolation structure 130 is formed between the fin 122, and grid is formed on the fin 122
140,142, with reference to shown in figure 8.
Isolation structure 130 separates the isolated material that fin hooks, and can be silica in the present embodiment.
Grid includes gate dielectric layer 140 and gate electrode 142, which can be silica or high-k gate dielectric material
Material (for example, being compared with silica, the material with high-k) or other suitable dielectric materials, high K medium material example
Such as hafnium base oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc..Gate electrode 142 can be able to be one with metal gate electrode
Layer or multilayered structure, may include metal material or polysilicon or their combination, metal material such as Ti, TiAlx、TiN、
TaNx、HfN、TiCx、TaCxEtc..
In the present embodiment, can be by filling the isolated material (not shown) of silica, and carry out chemical machinery
Planarization；Then, can use the certain thickness isolated material of hydrofluoric acid erosion removal, the isolated material of member-retaining portion fin it
Between, so as to form isolation structure 130, as shown in Figure 7.
In the present embodiment, rear grid technique may be used and form grid, specifically, including the following steps.
First, the false grid on the fin are formed at the middle part of the fin.
False grid may include pseudo- dielectric layer and dummy grid, which is the gate regions of resulting devices.It can lead to
It crosses and is sequentially depositing pseudo- dielectric layer and dummy grid, pseudo- dielectric layer such as can be silica, and dummy grid for example can be polysilicon, and
Afterwards, it using lithographic technique, is patterned, to form false grid.
Then, side wall is formed on the side wall of the false grid.
Side wall can be single or multi-layer structure, can be mixed by silicon nitride, silica, silicon oxynitride, silicon carbide, fluoride
Miscellaneous silica glass, low k dielectric material and combinations thereof and/or other suitable materials are formed.Can by deposit spacer material,
Then by anisotropic etch process, side wall is formed.
Then, source-drain area is formed in the fin of false grid both sides.
Ion implanting may be used or other suitable modes form source-drain area, in order to improve the carrier of device channel region
Mobility has the source-drain area of stress using epitaxial growth.
When forming the source-drain area with stress, specifically, it is possible, firstly, to by etching technics, such as dry etch process,
Depressed area is formed on the fin of the false grid both sides.Then, it by selective epitaxial growth process, is formed and is had in the depressed area
There is the source-drain area of stress, wherein for PMOS device, the material of the source-drain area provides compression, described in NMOS device
The material of source-drain area provides tensile stress.In the present embodiment, fin is epitaxial silicon material, and for NMOS device, source-drain area can be
SiC；For PMOS device, source-drain area can be SiGe, Ge, GeSn or three-five material.
Then, the interlayer dielectric layer of covering two lateral fin of the false grid is formed.
Dielectric material, such as undoped silica (SiO can be deposited by suitable deposition process2), doping oxygen
SiClx (such as Pyrex, boron-phosphorosilicate glass), silicon nitride (Si3N4) or other low k dielectric materials, it is then planarized, example
Such as CMP (chemically mechanical polishing), to form interlayer dielectric layer.
Then, false grid are removed, to form opening.
Wet etching and/or dry ecthing can be used to remove false grid, to which in former false gate region, formation exposes opening for fin
Mouthful
Finally, alternative gate is formed in the opening.
The gate dielectric layer that suitable deposition technique formation high K medium material may be used then is filled out in the opening
It fills, to form the metal gate electrode of one or more layers structure.
So far, the fin transistor device of the embodiment of the present invention is formd.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not limited to the present invention.Any technical person familiar with the field is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or it is revised as the equivalent embodiment of equivalent variations.Therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (9)
1. a kind of manufacturing method of fin transistor device, which is characterized in that including：
Semiconductor substrate is provided；
First epitaxial layer of epitaxial growth of semiconductor material on the semiconductor substrate；
The second epitaxial layer of epitaxial growth of semiconductor material on first epitaxial layer, first epitaxial layer have with described
The different material of second epitaxial layer；
Using first epitaxial layer as etching stop layer, second epitaxial layer is etched, to form fin；
Isolation structure is formed between the fin, and forms grid on the fin.
2. manufacturing method according to claim 1, which is characterized in that after the fins are formed, formed before isolation structure, also
Including：
Remove the first epitaxial layer of the fin both sides；
The first epitaxial layer under the fin is oxidized to oxygen buried layer.
3. manufacturing method according to claim 2, which is characterized in that be oxidized to the first epitaxial layer under the fin and bury oxygen
Layer, including：
Protective layer is formed on the side wall of the fin；
Oxidation technology is carried out, forms surface oxide layer in the substrate surface of the fin surface and exposure, and will be under the fin
The first epitaxial layer be oxidized to oxygen buried layer；
Remove the surface oxide layer and the protective layer.
4. manufacturing method according to any one of claim 1-3, which is characterized in that the thickness of first epitaxial layer is
2-20 nanometers.
5. manufacturing method according to any one of claim 1-3, which is characterized in that the thickness of second epitaxial layer is
50-500 nanometers.
6. manufacturing method according to any one of claim 1-3, which is characterized in that the semiconductor substrate and described
Two epitaxial layers have identical material.
7. manufacturing method according to claim 6, which is characterized in that the semiconductor substrate be silicon substrate, described second
Epitaxial layer is epitaxial silicon, and first epitaxial layer is germanium silicon.
8. manufacturing method according to claim 1, which is characterized in that grid is formed on the fin, including：
The false grid on the fin are formed at the middle part of the fin；
Side wall is formed on the side wall of the false grid；
Source-drain area is formed in the fin of the false grid both sides；
Form the interlayer dielectric layer of covering two lateral fin of the false grid；
The false grid of removal, to form opening；
Alternative gate is formed in the opening.
9. manufacturing method according to claim 8, which is characterized in that the alternative gate includes high K medium material and thereon
Metal gate electrode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810223692.4A CN108305835A (en) | 2018-03-19 | 2018-03-19 | Method for manufacturing fin type transistor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810223692.4A CN108305835A (en) | 2018-03-19 | 2018-03-19 | Method for manufacturing fin type transistor device |
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| CN108305835A true CN108305835A (en) | 2018-07-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| KR20200049468A (en) * | 2018-10-26 | 2020-05-08 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Buried power rail and method forming same |
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| KR102209956B1 (en) * | 2018-10-26 | 2021-02-02 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Buried power rail and method forming same |
| DE102019106763B4 (en) | 2018-10-26 | 2023-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | METHOD FOR FORMING AN INTEGRATED CIRCUIT STRUCTURE AND INTEGRATED CIRCUIT STRUCTURE |
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