CN108293294A - For encapsulating the microwire coil apparatus with the inductance compensation for being directed to the assembly with blind hole and buried via hole in PCB - Google Patents
For encapsulating the microwire coil apparatus with the inductance compensation for being directed to the assembly with blind hole and buried via hole in PCB Download PDFInfo
- Publication number
- CN108293294A CN108293294A CN201680070022.2A CN201680070022A CN108293294A CN 108293294 A CN108293294 A CN 108293294A CN 201680070022 A CN201680070022 A CN 201680070022A CN 108293294 A CN108293294 A CN 108293294A
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- China
- Prior art keywords
- conductive layer
- pth
- coil structures
- bga
- microwire
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
Abstract
For encapsulating the method and apparatus with the inductance compensation for being directed to the assembly with blind hole and buried via hole in PCB.The device uses the microwire coil structures that electroplating ventilating hole (PTH) structure is electrically connected to ball grid array (BGA) pad.The inductive effect that microwire coil structures generate is offset the capacitance caused by forming PTH the and PGA pad structures of natural plate capacitor and is reflected.Furthermore it is possible to adjust inductive effect by the quantity for changing coil windings and/or the size of loop construction.
Description
Background technology
In recent years, it is reported that high speed communications link has the transmission rate of up to 100 gigabit (Gb/s) per second, and
400Gb/s links or more are just in exploitation.For example, IEEE 802.3bj-2014 standards are defined using printed circuit board
(PCB) the 100Gb/s ether network chains of 4 25Gb/s accesses of the transmitting path parallel work-flow in the copper backboard and communications package in
The specification on road.In order to meet these high bandwidth capabilities, complicated analog signal processing is executed to reduce otherwise in physics (PHY) layer
It will cause by link and by encapsulating the various types of abnormal signals introduced in the analogue signalling that transmitting path is sent
Mistake.
A problem for handling high speed analog signal is the mistake caused by the undesirable capacitance in signal transfer circuit.
Specifically, introducing undesirable capacitance by the transmitting path formed in PCB and communications package.Electricity is compensated using inductance
Appearance is well known engineering philosophy.However, it is not known to build inductor in multilayer encapsulation in such a way that wires design is transparent
's.Realize the construction of fine tuning nor known.
Description of the drawings
The in terms of foregoing and many adjoint advantages of the present invention will become more clearly understood from, because by reference to following tool
Body embodiment, and when in conjunction with attached drawing, the in terms of foregoing of the present invention and many adjoint advantages may be better understood,
In identical reference numeral refer to identical part always in various views, unless otherwise indicated：
Fig. 1 is shown for using the electroplating ventilating hole for being electrically coupled to BGA pads and BGA soldered balls (forming capacitance structure)
(PTH) schematic diagram of the conventional packaging scheme of high-speed communication；
Fig. 2 a show side view of the explanation across the PCB and encapsulating structure of the electroplating ventilating hole of the sandwich layer of PCB；
Fig. 2 b show the 3D views of the physical model for a pair of of PTH that corresponding BGA pads are electrically coupled to via crankshaft structure；
Fig. 3 a show the 3D of the physical model for a pair of of PTH structures that corresponding BGA pads are electrically coupled to via crankshaft structure
View；
Fig. 3 b show the physical model for a pair of of PTH structures that corresponding BGA pads are electrically coupled to via microwire coil structures
3D views；
Fig. 4 a show the physical model for a pair of of PTH structures that corresponding BGA pads are electrically coupled to via microwire coil structures
Another 3D views；
Fig. 4 b show the detailed of a part for the physical model for showing 2 coil type microwire coil structures according to one embodiment
Thin 3D views；
Fig. 5 shows the detailed view that six exemplary microwire coil structures configure and uses Ansys HFSS all-wave 3D electromagnetism
Modeling software shows the curve graph of effective inductance level；
Fig. 6 is to show that the COM as defined in IEEE 802.3bj-2014 standards refers to the schematic diagram of packaging model；
Fig. 7 a are to show that COM refers to packaging model, are encapsulated with the COM that PTH, bent axle via and BGA balls are sealing end, and with
PTH, micro-coil and BGA balls are the curve graph of the differential insertion loss test result of the COM encapsulation of sealing end；
Fig. 7 b are to show that COM refers to packaging model, are encapsulated with the COM that PTH, bent axle via and BGA balls are sealing end, and with
PTH, micro-coil and BGA balls are the curve graph of the reflectance difference loss test result of the COM encapsulation of sealing end；
Fig. 8 is the schematic diagram for the circuit model of IEEE 100G BASE KR4COM tests；
Fig. 9 is to show that there is the ISI COM encapsulation in the short channels FCI, the ISI with the short channels FCI crosstalk bent axle to be added to block
Encapsulation and ISI with the short channels FCI add encapsulation that crosstalk micro-coil blocks modelling measurement result curve graph；With
And
Figure 10 is the cross-sectional view for the circuit board group piece installing for including the first COM encapsulation and the 2nd COM encapsulation, the first COM
Encapsulation and the 2nd COM encapsulation have along the signal path across the microwire coil structures formed in the pcb it is coupled to each other first
Semiconductor device and the second semiconductor device.
Specific implementation mode
This document describes for encapsulate and PCB in for the assembly with blind hole and buried via hole inductance compensation method and
The embodiment of device.In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the present invention.
However, those skilled in the relevant art it will be recognized that can in the case of one or more of no detail or
Implement the present invention using other methods, component, material etc..In other cases, well known structure, material or operation are not shown
Go out or is described in detail to avoid the aspect of the fuzzy present invention.
The spy that the reference of " one embodiment " or " embodiment " is meaned that the embodiment is combined to describe through this specification
Determine feature, structure or characteristic is included at least one embodiment of the invention.Therefore, occur everywhere through this specification
The phrase " in one embodiment " is not necessarily all referring to the same embodiment " in embodiment ".In addition, special characteristic, structure or spy
Property can combine in one or more embodiments in any suitable manner.
For the sake of clarity, the individual component in attached drawing can also be quoted by their label in the accompanying drawings, and
It is not to be quoted by specific reference numeral.Furthermore it is possible to the attached drawing mark for being followed by " (typ) " (indicating " typical ")
Remember to show to refer to the reference numeral of certain types of component (opposite with particular elements).It should be understood that the configuration of these components
To be typically there may be the like being still not shown in the accompanying drawings for brevity and clarity or without using list
The otherwise similar component that only reference numeral is marked.On the contrary, " (typ) " should not be construed as meaning that portion
Part, element etc. are typically used in its disclosed function, realization, purpose etc..
As discussed above, undesirable capacitance is introduced by the transmitting path formed in PCB and communications package.This
It is shown in Fig. 1, Fig. 1 shows the encapsulation 100 including pcb board 102.The transmitting path in PCB in a package is (partly by electricity
Trace 105 is described) between electrical connection realized using solder ball grid array (BGA) connection etc., as being shown in detail on the right side of Fig. 1.It is all
As semiconductor element or the component for encapsulating (not shown) are installed to BGA.As shown, being combined with BGA pads 108 and soldered ball 110
Electroplating ventilating hole (PTH) 106 for via forms capacitor arrangement.Specifically, top plates of the PTH 106 as capacitor, and BGA
Pad 108 and soldered ball 110 are used as bottom plate.This is not by design but due to the specific physical arrangement of PTH and BGA in encapsulation
Caused by, the result is that capacitance structure has negative effect due to reflection to system margins.
The more details of PTH structures are shown in Fig. 2 a and Fig. 2 b.As shown, PTH 106 extends through PCB's 100
Sandwich layer 200.As shown in the 3D detail views of Fig. 2 b, bottom and top encapsulate via transition region and are referred to herein as " bent axle via
Region " 202.As further shown, bottom bent axle via area 202 is in " shade " of BGA pads 108.
According to aspects of the present invention, the structure in the bent axle via area with microwire coil structures to replace the prior art.Example
Such as, Fig. 3 a and Fig. 3 b respectively illustrate the prior art construction including bent axle via area 202 and have used microwire coil structures 300
Replace the new configuration of bent axle via area 202.
The further details of one embodiment of microwire coil structures 300 are shown in Fig. 4 b.In general, one or more microwires
Circle 400 is coupling between the substrate of PTH 106 and BGA pads 108.The inductance of microwire coil structures is loop area and track width
Function, both of which can be controlled during manufacture.Inductance is also square directly proportional to loop quantity.By using ring
The combination of road surface product, track width and loop quantity can accurately control the amount of inductance.
Fig. 4 b show tool, and there are two the micro-coils of winding, generate the inductance higher than 1 picohenry (pH).Such as Fig. 4 b institutes
Show, due to cannot use gradually manufacturing process (for example, being manufactured for IC manufacturing and PCB and encapsulation) it is continuous to be formed
Coil loop, therefore the shape of each " loop " is as shown in the figure.This generates the similar effect (note as formed continuous coil loop
Corresponding inductance of anticipating is slightly less than with similarly sized continuous coil loop).
The additional exemplary configuration of microwire coil structures is shown in Fig. 5.As shown, pairs of in the presence of three groups be modeled
Configuration 500a and 500b, 502a and 502b and 504a and 504b.For each pairs of group, the difference in model is micro-coil
The arc length of structure 506,508 and 510.As shown, the arc length of microwire coil structures 506 is about 360 degree, and micro wire
The arc length of coil structures 508 is about 180 degree, and the arc length of microwire coil structures 510 is about 90 degree.
Curve graph 512 is shown on the left of Fig. 5, and different microwires are depicted using Ansys HFSS all-wave 3D Electromagnetic Modelings
The effective inductance of coil structures model is (with nanohenry (nH) to frequency (Hz × 1010)).As shown in curve graph 512, there is longer line
The model of circle is being up to about at 28GHz with larger effective inductance.However, at the frequency of 28GHz or more, effective inductance is deposited
In sizable variation.
All-wave 3D Electromagnetic Modelings show that the inductance of 50fH (millimicro microhenry) between 1000fH is feasible.It is expected that can lead to
It crosses and only increases or decreases more multi-coil (size as wound or solving roll and/or change coil) to realize the adjustment of several fH
Resolution ratio.Single loop between some application requirements 50fH to 300fH.
IEEE 802.3bj COM refer to packaging model and test result
IEEE 802.3bj-2014 standards limit the reflection of return loss specification.In IEEE 802.3bj-2014 also
Define channel operation nargin (COM) reference model and the program for calculating COM (it is the signal-to-noise ratio as unit of dB).
Fig. 6 shows that COM refers to packaging model 600, and Fig. 7 a and Fig. 7 b are to show following three kinds of difference for encapsulating selection
The curve graph of insertion loss (IL) and reflectance difference loss (RL).
1.COM is with reference to encapsulation
2. the encapsulation of the bent axle via with the prior art
3. the encapsulation with micro-coil
It is selected with following three kinds encapsulation in the s supplemental characteristics for the short backplane channel that the open region of IEEE 802.3bj is issued
In each cascade.Encapsulating 1 and 2 models has roughly the same return loss.Capacity ratio COM reference of the encapsulation 2 at BGA
The capacitance (180fF) assumed in encapsulation is more~50fF.Most deep trace indicates micro-coil encapsulation in Fig. 7 a and Fig. 7 b, and is directed to
25Gb/s NRZ (non-to revert to zero) passband shows smoother insertion loss and lower return loss.
COM results with short IEEE channel patterns are as follows：
The COM of 1.COM packaging models is 2.6dB
2. the COM of the encapsulation with Intel's prior art bent axle via is 2.0dB
3. the COM of the encapsulation with Intel's micro-coil is 3.6dB
It is required that the COM more than 3dB is to pass through IEEE 802.3bj-2014 standards.
Fig. 8 and Fig. 9 respectively illustrates circuit model 800 and describes the test knot of IEEE 100G BASE KR4 COM tests
The curve graph 900 of fruit.COM is added to reference to encapsulation connection, bent axle via BGA connections and micro-coil BGA connections using BGA
Connection, IEEE publications channel FCI_CC_Short_Link_Pair_2_to_Pair_10_Through.The channel has two
A connector, the connector have 5cm backboards and Line cards trace wires design.Back plate thickness is 6.4mm.Channel operation nargin
It is modeled with 25Gb/s data rates.With reference to encapsulation and encapsulation bent axle via sealing end is not compensated for COM, COM 2dB, and for
Micro-coil encapsulates BGA connections, COM 3.6dB.In addition, using micro-coil scheme, uncompensated ISI more preferably 16mV.
Figure 10 shows one embodiment of PCB assemblies 1000.PCB assemblies 1000 include PCB 1002, wherein with
Aforesaid way forms various microwire coil structures 400.The first COM including the semiconductor device 1106 for being coupled to BGA package 1108
Encapsulation 1104 is installed to via multiple soldered balls 1010 on PCB 1002.Similarly, including it is coupled to the semiconductor of BGA package 1116
The 2nd COM encapsulation 1112 of component 1114 is installed to via multiple soldered balls 1018 on PCB 1002.
Microwire coil structures 400 are coupled to the region 1020 and 1022 of the formation of the PTH in PCB 102.For simplicity, by
The various interconnection wirings and via that interconnection layer 1024 is shown jointly couple the signal of the PTH in region 1020 and 1022.Such as
It will appreciated by a person of ordinary skill in the art taht interconnection wiring and via can be formed with multilayer in PCB 1002.
The signal generated by semiconductor device 1106 and 1114 is transmitted along the transmitting path across microwire coil structures 400
Pass through PCB 1002.Therefore, because the capacitive coupling between BGA pads and the substrate of PTH, Signal Degrade that signal is subject to is small
It is more.
The other aspect of theme described herein is listed in the clause of following number：
1. one kind including the device of printed circuit board (PCB), including：
First conductive layer comprising ball grid array (BGA) pad；
Second conductive layer and third conductive layer, wherein the second conductive layer is disposed in the first conductive layer and third conductive layer
Between；
Sandwich layer is arranged between the second conductive layer and third conductive layer；
Across the electroplating ventilating hole (PTH) of sandwich layer, PTH has the substrate that is formed in the second conductive layer and by base conductive
The trace being connected in third conductive layer；And
Microwire coil structures are conductively connected the substrate and BGA pads of PTH.
2. the device of clause 1, wherein microwire coil structures are included in the first arc trace formed in the 4th conductive layer, the
Four conductive layers are arranged between the first conductive layer and the second conductive layer.
3. the device of clause 2, wherein microwire coil structures are included in the second arc trace formed in the 5th conductive layer, the
Five conductive layers are arranged between the 4th conductive layer and the second conductive layer.
4. the device of clause 3 further includes the buried via hole that the first arc trace is coupled to the second arc trace.
5. the device of clause 3, wherein the loop section of at least 270 degree of the first arc trace and the second arc trace formation.
6. the device of clause 3, wherein the first arc trace and the second arc trace form at least 630 degree of polycyclic section.
7. the device of any one of clause 2-6, wherein microwire coil structures are included in the second arc formed in the 5th conductive layer
Person's movements and expression line and the third arc trace formed in layer 6, the 5th conductive layer are arranged in the 4th conductive layer and the second conductive layer
Between, layer 6 is between layer 5 and the second conductive layer.
8. the device of any one of aforementioned clause, wherein the inductance compensation of microwire coil structures is by between PTH and BGA pads
Gap generate capacitance.
9. the device of any one of aforementioned clause, wherein microwire coil structures include the cener line for following distance with PTH
At least one trace of the axis radial offset amount of coincidence, and wherein, the cener line of PTH substantially with BGA pads
Center line is aligned.
10. the device of any one of aforementioned clause, wherein microwire coil structures have at least inductance of 1pH.
11. the device of any one of clause 1-9, wherein microwire coil structures have the inductance between 50fH and 300fH.
12. a kind of device including circuit board group piece installing, the device include：
Integrated circuit；
It is electrically coupled to the ball grid array of integrated circuit；And
Printed circuit board (PCB) comprising：
First conductive layer comprising be coupled to multiple BGA pads of ball grid array；
Second conductive layer and third conductive layer, wherein the second conductive layer is disposed in the first conductive layer and third conductive layer
Between；
Sandwich layer is arranged between the second conductive layer and third conductive layer；
Each PTH at least part in multiple electroplating ventilating holes (PTH) of sandwich layer, multiple PTH has the
The substrate that is formed in two conductive layers and base conductive is connected to the trace in third conductive layer；And
For each BGA pads at least part in multiple BGA pads, corresponding microwire coil structures are electrically coupled to
Between corresponding BGA pads PTH substrates corresponding in the second conductive layer.
13. the device of clause 12, wherein at least one microwire coil structures are included in the first arc formed in the 4th conductive layer
Person's movements and expression line, the 4th conductive layer are arranged between the first conductive layer and the second conductive layer.
14. the device of clause 13, wherein microwire coil structures are included in the second arc trace formed in the 5th conductive layer,
5th conductive layer is arranged between the 4th conductive layer and the first conductive layer.
15. the device of clause 13, wherein at least one microwire coil structures are included in the second arc formed in the 5th conductive layer
Person's movements and expression line and the third arc trace formed in layer 6, the 5th conductive layer are arranged in the 4th conductive layer and the first conductive layer
Between, layer 6 is between the 5th conductive layer and the first conductive layer.
16. the device of any one of clause 12-15, wherein the inductance compensation of at least one microwire coil structures is by micro-coil
The capacitance that gap between the structure PTH substrates being electrically coupled to and BGA pads generates.
17. the device of any one of clause 12-15, wherein at least one microwire coil structures include follow distance in PTH
A PTH at least one trace of axis radial offset amount that overlaps of cener line, and wherein, the center line of PTH
Axis is substantially aligned with the center line of a BGA pad in BGA pads.
18. the device of any one of clause 12-17, wherein integrated circuit is the communication core for having physics (PHY) layer interface
Piece, and wherein, at least one microwire coil structures are included in RX path or the transmitting path in high-speed communication channel, high speed
Communication port is coupled to the PHY layer interface at least transmission bandwidth of 25 Gigabits per seconds.
19. the device of any one of clause 12-18, wherein at least one microwire coil structures have at least inductance of 1pH.
20. the equipment of any one of clause 12-18, wherein at least one microwire coil structures have between 50fH and 300fH
Inductance.
21. a kind of device including circuit board group piece installing, the device include：
Printed circuit board (PCB)；
First ball grid array (BGA)；
First circuit block is installed to PCB via the first BGA；
2nd BGA；And
Second circuit component is installed to PCB via the 2nd BGA, wherein and PCB includes,
First conductive layer comprising be coupled to more than first a BGA pads of the first BGA and be coupled to the second of the 2nd BGA
Multiple BGA pads；
Second conductive layer and third conductive layer, wherein the second conductive layer is disposed in the first conductive layer and third conductive layer
Between；
A electroplating ventilating hole (PTH) and a PTH more than second more than first, more than first more than a PTH and second in a PTH at least one
Each PTH in part has the substrate formed in the second conductive layer and base conductive is connected in third conductive layer
Trace；
A microwire coil structures more than first and more than second a microwire coil structures, wherein every in a microwire coil structures more than first
It is corresponding among more than first a BGA pads that a microwire coil structures are electrically coupled to the substrate of the corresponding PTH among a PTH more than first
Between BGA pads, and wherein, each microwire coil structures more than second in a microwire coil structures are electrically coupled to a PTH more than second
Among corresponding PTH substrate and the corresponding BGA pads among more than second a BGA pads between；And
Signal path wires design couples in more than first a PTH and more than second a PTH and is coupled to corresponding microwire
Corresponding PTH pairs of coil structures.
22. the device of clause 21, wherein PCB includes sandwich layer, and wherein, and PTH passes through sandwich layer.
23. the device of clause 21 or 22, wherein at least one of microwire coil structures, which are included in the 4th conductive layer, to be formed
The first arc trace, the 4th conductive layer is arranged between the first conductive layer and the second conductive layer.
24. the device of any one of clause 21-23, wherein at least one of microwire coil structures microwire coil structures include
The the second arc trace formed in the 5th conductive layer, the 5th conductive layer are arranged between the 4th conductive layer and the first conductive layer.
25. the device of clause 24, wherein at least one of microwire coil structures microwire coil structures further include by the first arc
Trace is coupled to the buried via hole of the second arc trace.
26. the device of clause 24, wherein the loop section of at least 270 degree of the first arc trace and the second arc trace formation.
27. the device of clause 24, wherein the first arc trace and the second arc trace form at least 630 degree of polycyclic road
Section.
28. the device of any one of clause 21-27, wherein at least one of microwire coil structures have at least electricity of 1pH
Sense.
29. the device of clause 21-27, wherein at least one of microwire coil structures have the electricity between 50fH and 300fH
Sense.
30. the device of any one of clause 21-29, wherein signal path wires design includes in the interior layer in PCB
One in trace or wiring.
31. the device of any one of clause 21-30, wherein the first circuit block and second circuit component are communication chips.
32. the device of clause 31, wherein communication chip supports that it is at least one of at least 25 Gigabits per seconds to have bandwidth
The ethernet communication link of access, and wherein, the transmission path of each access at least one access is across corresponding micro-
Loop construction.
33. the device of clause 31, wherein communication chip supports tool, and there are four the ethernet communication link of access, Mei Getong
Road has the bandwidth of at least 25 Gigabits per seconds, and wherein, and the transmission path of each access passes through corresponding microwire coil structures.
34. the device of any one of clause 21-33, wherein the inductance compensation of at least one of microwire coil structures is by micro-
The capacitance that gap between substrate that loop construction is electrically coupled in-between, PTH and BGA pads generates.
35. the device of any one of clause 21-34, wherein at least one microwire coil structures include following distance and microwire
At least one trace of the axis radial offset amount that the cener line for the PTH that coil structures are coupled to overlaps, and wherein, PTH
The center line of BGA pads that is substantially electrically coupled to microwire coil structures of cener line be aligned.
Although describing some embodiments by reference to specific implementation, according to some embodiments, other realizations
Mode is possible.In addition, the arrangement and/or sequence of element shown in the accompanying drawings and/or described herein or other features are not
Centainly arranged with shown or described ad hoc fashion.According to some embodiments, many other arrangements are possible.
In each system shown in the figure, element in some cases can respective reference numeral having the same or not
Same reference numeral can be different and/or similar with the represented element of instruction.However, element can enough flexibly
To work with different realization methods and together with some or all of system shown or described herein system.Figure
Shown in various elements can be identical or different.Which element is referred to as first element and which element is referred to as
Two element is arbitrary.
In the specification and in the claims, term " coupling " and " connection " and their derivative can be used.It answers
The understanding, these terms are not intended as mutual synonym.But in a particular embodiment, " connection " can serve to indicate that
Two or more elements physically or electrically contact directly with one another." coupling " may mean that the direct physics of two or more elements
Or electrical contact.However, " coupling " may also mean that two or more elements are not directly contacted with each other, but still coordination with one another
Or interaction.
Embodiment is the realization method or example of the present invention.To " embodiment ", " one embodiment ", " some in specification
The reference of embodiment " or " other embodiment " mean a particular feature, structure, or characteristic described in conjunction with the embodiments be included in
In some few embodiments, but it is not necessarily all embodiments of the present invention." embodiment ", " one embodiment " or " some realities
Apply example " various occur being not necessarily all referring to identical embodiment.
All components, feature, structure, characteristic not described and illustrated herein etc. are required for being included in specific embodiment
Or in multiple embodiments.For example, if specification statement " can with ", " possibility ", " can " or "available" include component, feature,
Structure or characteristic is then not necessarily required including specific component, feature, the structure or characteristic.If specification or claim
Book mentions "a" or "an" element, then does not mean that there is only an elements.If specification or claims are mentioned " attached
Add " element, then do not exclude the presence of more than one add ons.
Algorithm be typically considered herein cause expected result from consistent action or the sequence of operation.These include pair
The physical manipulation of physical quantity.In general, but not necessarily, this tittle use can by storage, transmission, combine, compare and with its other party
The form of the electrical or magnetic signal that formula manipulates.The reason of primarily for Common usage, these signals are known as bit, value, members sometimes
Element, symbol, character, term, number etc. are proved to be convenient.It should be appreciated, however, that all these terms and term similar are all
It is associated with appropriate physical quantity, and is only the facility label suitable for this tittle.
It as discussed above, can be by corresponding software and/or fastener components and application (for example, by embedded
The software and/or firmware of the reason execution such as device) promote the various aspects of the embodiments herein.Therefore, the embodiment of the present invention can
For use as or support in some form of processor, processing core or embedded logic, the void run on processor or core
Execution or otherwise implementation or real on computer-readable or machine readable non-transitory storage medium or in it on quasi- machine
Existing software program, software module, firmware and/or distributed software.Computer-readable or machine readable non-transitory storage is situated between
Matter includes for any mechanism of machine (for example, computer) readable form storage or transmission information.For example, computer-readable
Or machine readable non-transitory storage medium includes with can be by computer or computing machine (for example, computing device, electronic system
Deng) form of access provides any mechanism of (that is, storage and/or transmission) information, for example, recordable/non-recordable medium (example
Such as, read-only memory (ROM), random access memory (RAM), magnetic disk storage medium, optical storage media, flash memory device
Deng).Content can be that directly executable (" object " or " executable " form), source code or variance codes (" increment " or " are mended
Fourth " code).Computer-readable or machine readable non-transitory storage medium can also include that can download the storage of content from it
Device or database.When computer-readable or machine readable non-transitory storage medium can also be included in sale or deliver thereon
Store substantial equipment or product.Therefore, substantial equipment will be stored and deliver or provide a mean for communication media download
Content be construed as provide include the computer-readable or machine readable nonvolatile with this content described herein
The product of property storage medium.
The above various assemblies for being referred to as process, server or tool described herein can be performed for being described herein
Function means.The operation executed by various assemblies described herein and function can be soft by what is run on processing element
Part is realized via any combinations of embedded hardware etc. or hardware and software.These components can be implemented as software module,
It is hardware module, the hardware (for example, specialized hardware, ASIC, DSP etc.) of specific purposes, embedded controller, hard-wired circuit, hard
Part logic etc..Software content (such as data, instruction, configuration information etc.) can be via including computer-readable or machine readable non-
The product of temporary storage medium provides, and provides the content for the instruction for indicating can be performed.Content can lead to computer
Execute various functions/operation described herein.
As used herein, the bulleted list connected by term "...... at least one" can indicate Listed Items
Any combinations.For example, phrase " at least one of A, B or C " can indicate A；B；C；A and B；A and C；B and C；Or A, B and C.
The above description (being included in the content described in abstract) of the illustrated embodiment of the present invention is not intended to exhaustive
Or limit the invention to disclosed precise forms.Although describing the specific implementation of the present invention for illustrative purposes herein
Example and example, but various equivalent modifications within the scope of the invention are possible, as those skilled in the relevant art will recognize
Know.
These modifications can be carried out to the present invention according to specific implementation mode above.It is used in the appended claims
Term is not necessarily to be construed as limiting the invention to specific embodiment disclosed in the description and the appended drawings.On the contrary, the model of the present invention
It encloses and is indicated in the appended claims completely, these claims are explained according to set claim canons of construction.
Claims (25)
1. one kind including the device of printed circuit board (PCB), including：
First conductive layer comprising ball grid array (BGA) pad；
Second conductive layer and third conductive layer, wherein second conductive layer is disposed in first conductive layer and described the
Between three conductive layers；
Sandwich layer is arranged between second conductive layer and the third conductive layer；
Across the electroplating ventilating hole (PTH) of the sandwich layer, the PTH has the substrate formed in second conductive layer and will
The base conductive is connected to the trace in the third conductive layer；And
Microwire coil structures are conductively connected the substrate of the PTH and the BGA pads.
2. the apparatus according to claim 1, wherein the microwire coil structures are included in first formed in the 4th conductive layer
Arc trace, the 4th conductive layer are arranged between first conductive layer and second conductive layer.
3. the apparatus of claim 2, wherein the microwire coil structures are included in second formed in the 5th conductive layer
Arc trace, the 5th conductive layer are arranged between the 4th conductive layer and second conductive layer.
4. device according to claim 3 further includes that the first arc trace is coupled to the second arc trace
Buried via hole.
5. device according to claim 3, wherein the first arc trace and the second arc trace are formed at least
270 degree of loop section.
6. device according to claim 3, wherein the first arc trace and the second arc trace are formed at least
630 degree of polycyclic section.
7. according to the device described in any one of claim 2-6, wherein it is conductive that the microwire coil structures are included in the described 5th
The the second arc trace formed and the third arc trace formed in layer 6, the 5th conductive layer are arranged in institute in layer
It states between the 4th conductive layer and second conductive layer, the layer 6 is between the layer 5 and second conductive layer.
8. device according to any one of the preceding claims, wherein the inductance compensation of the microwire coil structures is by described
The capacitance that gap between PTH and the BGA pads generates.
9. device according to any one of the preceding claims, wherein the microwire coil structures include following distance and institute
At least one trace of the axis radial offset amount of the cener line coincidence of PTH is stated, and wherein, the center line of the PTH
Axis is substantially aligned with the center line of BGA pads.
10. a kind of device including circuit board group piece installing, described device include：
Integrated circuit；
It is electrically coupled to the ball grid array of the integrated circuit；And
Printed circuit board (PCB) comprising：
First conductive layer comprising be coupled to multiple BGA pads of the ball grid array；
Second conductive layer and third conductive layer, wherein second conductive layer is disposed in first conductive layer and described the
Between three conductive layers；
Sandwich layer is arranged between second conductive layer and the third conductive layer；
Across multiple electroplating ventilating holes (PTH) of the sandwich layer, each PTH at least part in the multiple PTH has
The substrate that is formed in second conductive layer and the base conductive is connected to the trace in the third conductive layer；With
And
For each BGA pads at least part in the multiple BGA pads, corresponding microwire coil structures are electrically coupled to
Between corresponding BGA pads PTH substrates corresponding in second conductive layer.
11. device according to claim 10, wherein at least one microwire coil structures, which are included in the 4th conductive layer, to be formed
The first arc trace, the 4th conductive layer is arranged between first conductive layer and second conductive layer.
12. according to the devices described in claim 11, wherein the microwire coil structures are included in formed in the 5th conductive layer
Two arc traces, the 5th conductive layer are arranged between the 4th conductive layer and first conductive layer.
13. according to the devices described in claim 11, wherein at least one microwire coil structures, which are included in the 5th conductive layer, to be formed
The second arc trace and the third arc trace that is formed in layer 6, the 5th conductive layer be arranged in the described 4th and lead
Between electric layer and first conductive layer, the layer 6 is between the 5th conductive layer and first conductive layer.
14. according to the device described in any one of claim 10-13, wherein the inductance compensation of at least one microwire coil structures
The capacitance that gap between the PTH substrates be electrically coupled to by the microwire coil structures and the BGA pads generates.
15. according to the device described in any one of claim 10-13, wherein at least one microwire coil structures include follow away from
At least one trace from the axis radial offset amount overlapped with the cener line of a PTH in the PTH, and its
In, the cener line of the PTH is substantially aligned with the center line of a BGA pad in the BGA pads.
16. according to the device described in any one of claim 10-15, wherein the integrated circuit is with physics (PHY) layer
The communication chip of interface, and wherein, at least one microwire coil structures are included in the RX path or hair in high-speed communication channel
It send in path, the PHY layer interface at least transmission bandwidth of 25 Gigabits per seconds is coupled in the high-speed communication channel.
17. a kind of device including circuit board group piece installing, described device include：
Printed circuit board (PCB)；
First ball grid array (BGA)；
First circuit block is installed to the PCB via the first BGA；
2nd BGA；And
Second circuit component is installed to the PCB via the 2nd BGA, wherein and the PCB includes,
First conductive layer comprising be coupled to more than first a BGA pads of the first BGA and be coupled to the 2nd BGA's
A BGA pads more than second；
Second conductive layer and third conductive layer, wherein second conductive layer is disposed in first conductive layer and described the
Between three conductive layers；
In a electroplating ventilating hole (PTH) and a PTH more than second more than first, a PTH more than described first and more than second a PTH extremely
Each PTH in a few part has the substrate formed in second conductive layer and the base conductive is connected to institute
State the trace in third conductive layer；
A microwire coil structures more than first and more than second a microwire coil structures, wherein every in a microwire coil structures more than described first
A microwire coil structures are electrically coupled to the substrate of the corresponding PTH among a PTH more than described first and are welded with more than described first a BGA
Between corresponding BGA pads among disk, and wherein, each microwire coil structures thermocouple more than described second in a microwire coil structures
Close the substrate in the corresponding PTH among a PTH more than described second and the corresponding BGA among more than described second a BGA pads
Between pad；And
Signal path wires design couples being coupled to accordingly in a PTH more than described first and more than second a PTH
Corresponding PTH pairs of microwire coil structures.
18. device according to claim 17, wherein the PCB includes sandwich layer, and wherein, and the PTH passes through described
Sandwich layer.
19. the device according to claim 17 or 18, wherein at least one of described microwire coil structures are included in the 4th
The the first arc trace formed in conductive layer, the 4th conductive layer are arranged in first conductive layer and second conductive layer
Between.
20. according to the device described in any one of claim 17-19, wherein at least one of described microwire coil structures are micro-
Loop construction is included in the second arc trace formed in the 5th conductive layer, and it is conductive that the 5th conductive layer is arranged in the described 4th
Between layer and first conductive layer.
21. device according to claim 20, wherein at least one microwire coil structures in the microwire coil structures
It further include the buried via hole that the first arc trace is coupled to the second arc trace.
22. device according to claim 20, wherein the first arc trace and the second arc trace formed to
Few 270 degree of loop section.
23. device according to claim 20, wherein the first arc trace and the second arc trace formed to
Few 630 degree of polycyclic section.
24. according to the device described in any one of claim 17-23, wherein first circuit block and second electricity
Circuit unit is communication chip, wherein the communication chip supports that it is at least one logical of at least 25 Gigabits per seconds to have bandwidth
The ethernet communication link on road, and wherein, the transmission path of each access at least one access passes through accordingly
Microwire coil structures.
25. according to the device described in any one of claim 17-24, wherein at least one microwire coil structures include follow away from
From with the micro-coil structure Coupling to the PTH at least one mark of axis radial offset amount that overlaps of cener line
Line, and wherein, the BGA pads that the cener line of the PTH is substantially electrically coupled to the microwire coil structures
Center line is aligned.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562274136P | 2015-12-31 | 2015-12-31 | |
| US62/274,136 | 2015-12-31 | ||
| PCT/US2016/067697 WO2017116832A1 (en) | 2015-12-31 | 2016-12-20 | Micro coil apparatus for inductive compensation in packages and pcb for assemblies with blind and buried vias |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108293294A true CN108293294A (en) | 2018-07-17 |
Family
ID=59225213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680070022.2A Pending CN108293294A (en) | 2015-12-31 | 2016-12-20 | For encapsulating the microwire coil apparatus with the inductance compensation for being directed to the assembly with blind hole and buried via hole in PCB |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN108293294A (en) |
| DE (1) | DE112016006129T5 (en) |
| WO (1) | WO2017116832A1 (en) |
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| JP2011210596A (en) * | 2010-03-30 | 2011-10-20 | Murata Mfg Co Ltd | Ic socket and mounting structure thereof |
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| US20040032313A1 (en) * | 2002-08-15 | 2004-02-19 | Andrew Ferencz | Simplified transformer design for a switching power supply |
| CN101180924A (en) * | 2005-04-11 | 2008-05-14 | 英特尔公司 | Inductor |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2017116832A1 (en) | 2017-07-06 |
| DE112016006129T5 (en) | 2018-10-18 |
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Application publication date: 20180717 |