CN108287800A - A kind of bus arbitration system and method based on single bus communication protocol - Google Patents
A kind of bus arbitration system and method based on single bus communication protocol Download PDFInfo
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- CN108287800A CN108287800A CN201711429281.2A CN201711429281A CN108287800A CN 108287800 A CN108287800 A CN 108287800A CN 201711429281 A CN201711429281 A CN 201711429281A CN 108287800 A CN108287800 A CN 108287800A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
Abstract
The present invention provides a kind of bus arbitration system and method based on single bus communication protocol is used for Monobus network, including:Multiple main frames are transmitted control to the bus of the Monobus network;It is arbitrated according to timesharing section arbitration mechanism between the multiple host, by analyzing the transaction sequence of the bus, is judged using bus free, distributed arbitration program is carried out on the arbitration domain of the transaction sequence, and limited competition is carried out using bus contention order.In the present invention, need not make any modification as slave can be directly accessed the unibus system built according to the present invention, and since the control of built bus is only sent by initialization sequence and command word, ROM codes and main equipment, the data of reception determine, there is no central host, so bus does not have any scheduled priority.In special circumstances, if you need to support iButton, a default host is may specify when building bus system.
Description
Technical field
The present invention relates to communication protocol techniques field, more particularly between IC chip or distributed data acquisition section
The arbitration mechanism that monobus communicates between point.
Background technology
Monobus (1-wire buses) is a proprietary technology of Maxim wholly-owned subsidiaries Dallas, can be in single line item
Data communication and electric current transfer function between slave are completed under part, are had and are saved I/O mouth lines resource, simple in structure, at low cost
It is honest and clean, convenient for bus extension and many advantages, such as safeguard.But 1-Wire bus data transfer rates are relatively low, and there are two types of rates:Standard
Pattern 16kbps, high speed (super driving) pattern is 142kbps.Communication use host-guest architecture, be a host to one or more slaves.1-
Wire equipment is gathered around can be simultaneously in same bus using this unique trait there are one 64 exclusive identification codes (ROM codes)
Mount multiple 1-Wire equipment.
It is the reliable primary condition of safeguards system that equipment carries out work according to 1-Wire communication protocols.1-Wire bus systems
With single duplex mode, timesharing exchanges data on same data/address bus between slave, passes through the high low setting to level in bus
To transmit data bit 1 and 0.Ensure the reliability service of 1-Wire bus systems, 1-Wire must be strictly observed between slave
Communications transaction sequence carries out the data communication for meeting timing requirements.And 1- Wire transaction sequences are all by a series of activities sequential
Composition, most basic work schedule includes equipment initialization, host writes sequential, host reads sequential.It is all in 1-Wire buses
Transaction sequence (being made of aforementioned 3 kinds of sequential) is started with initialization, and the reset pulse and slave that initialization is sent out by host are rung
The transponder pulse composition answered.Transponder pulse makes host know in bus there is slave and ready.After initialization slave it
Between transmitted by read-write sequence initiation command and data exchange, write sequential and be divided into and write 0 and write 1, write after sequential starts, 1-Wire is set
It is standby data/address bus to be detected in sampling window to obtain the position data of host transmission.Sequential is read equally to be divided into reading 0 and read
1, after reading sequential starts, host is detected data/address bus in sampling window to obtain the position data of equipment transmission.
Therefore, existing monobus arbitration mechanism can lead to additional timings expense, to increase system burden, reduce system
Reaction speed.
Invention content
In order to solve the above problem, the present invention is to inherit to propose a kind of bus arbitration mechanism under former monobus characteristic, using point
When section arbitration law, and use it for building the more host multinodes for following monobus (1-wire) communication protocol interconnection monobus
Network, and compatible original 1-wire devices.
Specifically, according to an aspect of the invention, there is provided a kind of bus arbitration system based on single bus communication protocol
System is used for Monobus network, including:
Multiple main frames are transmitted control to the bus of the Monobus network;According to timesharing between the multiple host
Section arbitration mechanism is arbitrated, and by analyzing the transaction sequence of the bus, is judged using bus free, in the affairs sequence
Distributed arbitration program is carried out on the arbitration domain of row, and carries out limited competition using bus contention order.
Preferably, the arbitration domain refers to bus signals on the bus:In initialization sequence, read/write time slot by
And the period that bus is only driven by host side and drags down bus.
It is furthermore preferred that described drive bus by host side and include by the period that bus drags down:Answering in initialization sequence
The digit pulse period is write to be pulled down to since bus time slot in time slot and is finally released as the high period, reads in time slot from time slot
Start to drag down bus and is kept for period until 1 microsecond.
Preferably, the specific method of the bus free judgement is:If the bus uses unified power supply power supply and nothing
When other independent current source nodes, after the node device electrification reset of the Monobus network or complete a bus transaction sequence
It monitors to assert bus free when bus is high after row;If the bus has multiple independent current source nodes, work as node
Equipment is on it after reset, when monitoring that bus is high, then assert that bus is empty after continuous monitoring one delay time section of bus
It is not busy.
It is furthermore preferred that the delay time section is longest waiting time delay in bus operation sequence, i.e., its value is following
The maximum value of Shi Yanzhong:Detect online recovery latency between high time delay, bus operation time slot, the time delay in 1 time slot of read-write and
Waiting time delay in feature operation.
Preferably, the full 0 that the ROM command codes of the bus contention order are 8 is followed by the host for starting transaction sequence
64 ROM codes.
Preferably, the limited competition refers to, when the continuous competition frequency of failure of a host is more than or equal to its internal preset
When value, which can preengage bus using bus contention order in subsequent bus contention.
Preferably, the host selects search command having to explicitly to indicate last in a string of continuous transaction sequences using sky
It is a, the end of a string of continuous transaction sequences is indicated with this.
It is furthermore preferred that the sky selects the F0 that the ROM command codes of search command are 8,64 read-reads-of heel to write the 0th
To the 63rd ROM code period;In the period, the return value for reading time slot twice since certain is 1, i.e., having to explicitly indicates
This search does not select the node device in any one bus.
According to another aspect of the present invention, a kind of bus arbitration method based on single bus communication protocol is additionally provided,
For Monobus network, above-mentioned system is used.
Advantage of the invention is that:As slave, it any modification need not be made can be directly accessed and build according to the present invention
Unibus system, and since the control of built bus is only set by initialization sequence and command word, ROM codes and leading
The data decision that preparation is sent, received, without central host, so bus does not have any scheduled priority.In special circumstances, such as
It need to support iButton, a default host is may specify when building bus system.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit are common for this field
Technical staff will become clear.Attached drawing only for the purpose of illustrating preferred embodiments, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 is that the initialization sequence of the present invention arbitrates domain figure;
Fig. 2 writes time-slot arbitration domain figure for the present invention's;
Fig. 3 is the reading time-slot arbitration domain figure of the present invention;
Fig. 4 is the arbitrated procedure schematic diagram of the host of the present invention.
Specific implementation mode
Exemplary embodiments of the present invention are more fully described below with reference to accompanying drawings.Although showing this hair in attached drawing
Bright illustrative embodiments, it being understood, however, that may be realized in various forms the reality of the invention without that should be illustrated here
The mode of applying is limited.It is to be able to be best understood from the present invention on the contrary, providing these embodiments, and this can be sent out
Bright range is completely communicated to those skilled in the art.
The present invention is a kind of bus arbitration mechanism proposed in the case where inheriting former monobus characteristic, is arbitrated using timesharing section
Method, and use it for building the more host multinodes for following monobus (1-wire) communication protocol interconnection Monobus network, and it is simultaneous
Hold original 1-wire devices:I.e. it is as a slave, need not make any modification and can be directly accessed and be built according to present mechanism
Unibus system.By analyzing former monobus transaction sequence, using peculiar bus free determination method, in exclusive arbitration domain
Upper carry out distributed arbitration program, and limited competition is carried out using special command, and the competition expense of bus is zero.It is total by building
The control of line is only sent by initialization sequence and command word, ROM codes and main equipment, the data of reception determine, without center
Host, so bus does not have any scheduled priority.It in special circumstances, can when building bus system if you need to support iButton
Specify a default host.
The arbitration mechanism of monobus proposed by the present invention arbitrates machine using distributed timesharing section without additional timings expense
System.Different then its arbitration of more power supplys (distribution) power supply mode whether are used to calculate for 1-wire bus multinodes interference networks
Method is slightly different.It is accessed in more host multinodes interconnection Monobus network that the arbitration mechanism proposed according to the present invention is built
Node device can functionally be divided into slave or host.Host is the promoter of bus transaction sequence and executes arbitration and (while also ringing
It should transaction sequence);Slave only in response to and feed back corresponding data.And the arbitration primitive rule of monobus is in the present invention:
It is whether identical as the driving value of this host that bus value is monitored during arbitrating time domain, means that bus competes if different, this
Host stops operation while abandoning the control to bus at once;Since 1-wire buses are connect using " line with ", then when its driving
To find that bus is " 0 " when " 1 ", that is, representing the competition of this host unsuccessfully should abort operation at once.
Consider there is node device to power using parasitic in 1-wire networks, then host is monitoring bus free and full simultaneously
It could start transmission when all node device (predominantly using the node device of parasitic power supply) Power Supplies Conditions in sufficient network.And such as
At leisure whether what judge bus current timeIn the present invention, whether multiple feed side is used for current 1-wire networks
Its judgment mechanism of formula is different, and bus arbitration mechanism proposed by the present invention is discussed in detail below.
The present invention proposes a kind of bus arbitration system based on single bus communication protocol, is used for Monobus network, including:
Multiple main frames are transmitted control to the bus of the Monobus network;According to timesharing between the multiple host
Section arbitration mechanism is arbitrated, by analyzing the transaction sequence of the bus, using bus free judgement, in the affairs sequence
Distributed arbitration program is carried out on the arbitration domain of row, and carries out limited competition using bus contention order.Elaboration in detail below is above-mentioned
The each process of arbitration mechanism that host uses:
(1) judge bus free method
If the bus system set up is using unified power supply power supply and when without other independent current source nodes, when in this system
It monitors to assert bus free when bus is high after node device electrification reset or after completing a bus transaction sequence.
Otherwise, node device should also continuously monitor one delay t of bus after reset when monitoring that a bus is high on itDELAYWhen
Between after section (bus is height always around here) could assert bus free.Be delayed tDELAYInvolved bus when to set up bus system
Longest waiting time delay in the sequence of operation, i.e. its value are to detect recovery latency between high time delay, bus operation time slot online, read
Write the time delay in 1 time slot and the waiting time delay in feature operation these when Yanzhong maximum value.And complete a transaction sequence
Method is identical both when judging bus free afterwards.
Host should also judge that all node devices using parasitic power supply are full in 1-wire networks after judging bus free
Sufficient Power Supplies Condition, or while meeting automatically when judging bus free, could start transmission.It refers to that these are adopted to meet Power Supplies Condition
Normal operating conditions has been charged to the node device of parasitism power supply (capacitance is charged to full value).And their charging time is (total
At this moment line is height) with it is specific set up bus system when using pull-up voltage in the parasitic number of node equipment powered, bus, communicate speed
Rate, operating temperature, cable length and node device driving type are related.Its value is mainly by using parasitic power supply in system
Number of node equipment determine that the recovery latency between value and bus operation time slot is identical (see " recovery between bus operation time slot
Time delay " part).
Bus is monitored during arbitration time domain (see " the arbitration domain of monobus " part) in 1-Wire communications transaction sequences
Whether whether value with this host drive value identical, means that competition occurs for bus and this host loses arbitration if different, i.e.,
Competition failure, this host stop operation while abandoning the control to bus at once.It should be noted that sound of this host to bus operation
It should be also possible to continue until finding that this bus operation sequence is unrelated with oneself.
(2) limited competition rule
Host observe bus free and also meet connected equipments in current system Power Supplies Condition and initiate one
Transaction sequence is denoted as primary competition failure if the host loses arbitration during this (before completing the moment to the transaction sequence),
Its unit for built system bus transaction sequence.A random number is set inside each host, value range is minimum to be taken
The host number in system is built, the total node number being up in system.When the continuous frequency of failure of a host is more than or equal to this at random
When number, host uses competition command sequence in subsequent bus contention (see " bus contention order " part).Here special Shen
Bright is to treat the metering of bus searching class order to be different.It (is ordered using same search for continuously searching for transaction sequence
Enable), if in first search transaction sequence competition failure that the continuous search transaction sequence starts, in the continuous search affairs
It must not be at war with to bus in the subsequent searches transaction sequence of sequence and (must not initiate bus operation) and be denoted as primary
Failure.Search command sequence mark (identical as preceding transaction sequence command code to see " sky selects search command " part) is selected used here as sky
This time search transaction sequence is the last one search transaction sequence in this continuous search transaction sequence (while potentially to master
More stringent requirements are proposed for the searching algorithm of machine).Arbitration domain, bus different delay and special command are done specifically separately below
It is bright.
(3) the arbitration domain of monobus
It is by host driven bus (1-wire bus) in the transaction sequence of monobus and by the period that bus drags down
Bus arbitration domain.Distinguish analytic explanation bus arbitration below for several bus signals sequential defined in 1-wire communication protocols
Domain.Some that be used time sequence parameters (see 1. monobus temporal characteristics parameter of table below) are first provided before explanation, below will
Directly explained using the symbol of these parameters.
1 monobus temporal characteristics parameter of table
Note 1:Δ indicates the host sampling time
(4) the arbitration domain in initialization sequence
With reset pulse, (host drags down monobus t to one initialization sequenceRSTLMicrosecond is until bus state returns to height) it rises
Begin, and waiting delay tPDHIGHMonobus t (is dragged down with online transponder pulse after microsecondPDLOWMicrosecond) terminate.Only have among these
Reset pulse region is arbitration domain (Fig. 1 middle twills shadow region), and initialization sequence arbitrates domain as shown in Figure 1.
(5) the arbitration domain in time slot is write
It writes there are two types of time slots, that is, write 0 time slot and writes 1 time slot.Their arbitration domain is pulled down to finally from monobus
Until release bus makes it be raised (close twill shadow region in Fig. 2).Write time-slot arbitration domain figure as shown in Figure 2.
(6) the arbitration domain in time slot is read
Host reads 0 time slot and reads the arbitration domain of 1 time slot to be all to drag down bus from host and discharge after keeping at least 1 microsecond
Bus this period (close twill shadow region in Fig. 3).Due to joining to reading time slot initialization drop-down sequential in former 1-wire agreements
Number tRILIt is defined as>1 μ s, then it is that (host is total since time slot to take 1 microsecond of greatest common divisor to read the arbitration domain of time slot here
Line drags down) 1 microsecond period.Time-slot arbitration domain is read to see shown in Fig. 3.
(7) the waiting time delay in monobus transaction sequence
According to 1-wire agreements, all node devices must comply with bus transaction sequence shown below, any step
Missing out of order can all cause node device not respond host.Its sequence of operation is as follows:
Step 1, initial reset/online response detection cycle
Step 2, ROM command operation periods
Step 3, command function operation cycle
Then to waiting for time delay (bus state is high level at this time) to be analyzed as follows in monobus transaction sequence:
(8) high time delay is detected online
High time delay t is detected onlinePDHIGHBe being terminated to online transponder pulse by reset pulse in initialization step
Waiting time delay (the slave stand-by period in Fig. 1), its value is the microsecond of 15 microseconds~60 in 1-wire agreements, is initialization
Bus is the high latency of high level in step.
(9) recovery latency between bus operation time slot
Recovery latency t between bus operation time slotRECIncluding online transponder pulse and write between time slot, read-write time slot
Bus recovery time, its value range is 1 microseconds of > in 1-wire agreements;And read and write its meaning of bus recovery time between time slot
It is to make to charge to normal operating conditions using the node device of parasitic power supply in 1-wire networks (capacitance is charged to full value).Online
After transponder pulse and the recovery latency for writing between time slot start from online transponder pulse, and next time slot (write order code
Lowest order) failing edge terminate.Under normal conditions, selected tRSTLAnd tRSTHDuration is identical.Under standard speed, at this time
tRECValue is the microsecond of 180 microseconds~405.Under high-speed mode, then above-mentioned time value is shorter, typically under standard speed very
One of, tRECIt is reduced to the microsecond of 18 microseconds~40.And write the bus recovery latency between time slot and section when specific establishment bus system
Pull-up voltage, traffic rate, operating temperature, cable length and node device on point device (it is powered using parasitic) number, bus
Drive type related.Its value mainly by being determined using the number of node equipment of parasitic power supply in system, complies with following equation:
tREC=F × N+S
F- is according to coefficient selected by voltage, temperature etc.;Recommendation is as follows, standard speed:1.54~3.52, high-speed mode:
1.18~1.8
The number of node equipment of parasitic power supply is used in N- systems
S- system velocity base values;Recommendation is as follows, standard speed:1 microsecond, high-speed mode:0.5 microsecond.
(10) time delay in 1 time slot is read and write
The time delay read and write in 1 time slot refers to that bus is the time of high level (1 time slot to be write in see Fig. 2 in 1 time slot of read/write
With 1 time slot is read in Fig. 3), i.e. tSLOT-tRILValue is the microsecond of 1 microsecond of 45+ Δs~119.Here Δ refers to the host sampling time, by specific
Host selected when bus system is set up to determine.
(11) the waiting time delay in feature operation
Waiting time delay in feature operation refers to that the host in certain feature operations waits for slave devices to complete function behaviour
Make the spent stand-by period (bus state is high level at this time), the thermometric order such as in DS18B20 micro LANs waits for
Time is 93.75 milliseconds~750 milliseconds.
(12) bus contention order
Bus contention order follows transaction sequence shown below, and the sequence of operation is as follows:
Step 1, initial reset/online response detection cycle
Step 2, ROM command operation periods
Step 2 is completed to indicate this bus transaction the sequence ends.After host sends out bus contention command code (H'00),
Followed by 64 ROM codes (being shown in Table 2) of this host (host for starting this transaction sequence).Bus contention order is used for sound
Bright host ROM codes, while showing that can start back to back next bus transaction sequence preengages the bus right to use.
(13) sky selects search command
Sky selects search command to follow transaction sequence shown below, and the sequence of operation is as follows:
Step 1, initial reset/online response detection cycle
Step 2,64 read-reads-write the position (the 0th to the 63rd) the ROM code operation cycles
Step 2 is completed to indicate this bus transaction the sequence ends.After host sends out search command code (H'F0), and then
It is that 64 read-reads-write position (the 0th to the 63rd) ROM code period (being shown in Table 2);(selection) is write in the period in these read-reads-,
It is ' 1 ' that must read the return value of time slot twice since certain, i.e., having to explicitly indicates this search and do not select any one bus
On node device.Sky selects search command to be used to state that this search affairs to be that the secondary bus is continuously searched in transaction sequence most
Transaction sequence is once searched for afterwards.
2 special ROM command tables of table
Embodiment 1
It is the course of work example according to the bus arbitration system based on single bus communication protocol of the present invention below:
As shown in figure 4, host can start bus transaction sequence when monitoring bus free and meeting Power Supplies Condition simultaneously
Row.Two or more hosts may initiate a reset pulse simultaneously in its respective clock cycle errors, as a result in bus
One defined reset pulse sequential of upper generation.Here the host that clock cycle errors E refers to startup bus transaction sequence is produced
The clock cycle that the time difference of raw reset pulse failing edge and the reset pulse failing edge in final bus is less than the host, (this took
Certainly in the monitoring bus mode of host).
When bus is that lower drags down (arbitration time domain) under reset pulse or other hosts, the master by initiating operation is arbitrated
Machine respectively carries out;Whether arbitration rules with this host are driven value identical by monitoring bus value, mean bus hair if difference
Raw competition, then this host stops operation while abandoning the control to bus at once;Since 1-wire buses are connect using " line with ",
Then found when it is driven to " 1 " bus be " 0 " represent that this host competes unsuccessfully should abort operation at once.Due to monobus
Data line state is determined by the host for winning arbitration, and any transmission information will not be lost in arbitrated procedure.Due to each host
The function of host and slave is combined, so any one host should all respond the operation of bus until finding this secondary bus behaviour
Make sequence it is unrelated with oneself until.
Fig. 4 shows the arbitrated procedure of three hosts.Certainly, arbitrated procedure may relate to more contents, this is by connecting
It is determined to the operation that the host of bus is initiated in advance.During reset pulse (twill shadow region in left in Fig. 4), generate
The internal drive data level and the actual level of 1-wire buses of the host of DQ1 are inconsistent, then the host is answered in the online of it
It answers the stand-by period and closes data-driven (i.e. it loses arbitration).During write order (twill shadow region in right in Fig. 4), generate
The internal drive data level and the actual level of 1-wire buses of the host of DQ2 are inconsistent, then the host is when at it, this is write
Data-driven is closed after gap (i.e. it loses arbitration).It can see that arbitrated procedure can't be influenced by winning arbitration by Fig. 4
The data transmission that carries out of the bus transaction sequence initiated of host.
Since the data that the control of monobus is only sent by initialization sequence and command word, ROM codes and host determine do not have
There is central host, so bus is also without any scheduled priority.It althoughs note that by random set by limited competition rule
Number can bring a potential priority.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (10)
1. a kind of bus arbitration system based on single bus communication protocol is used for Monobus network, which is characterized in that including:
Multiple main frames are transmitted control to the bus of the Monobus network;
It is arbitrated according to timesharing section arbitration mechanism between the multiple host, by analyzing the transaction sequence of the bus,
Judged using bus free, carry out distributed arbitration program on the arbitration domain of the transaction sequence, and using bus contention order into
Row limited competition.
2. the bus arbitration system according to claim 1 based on single bus communication protocol, it is characterised in that:
The arbitration domain refers to only by the host driven bus and being dragged down bus in bus signals on the bus
Period.
3. the bus arbitration system according to claim 2 based on single bus communication protocol, it is characterised in that:
The period dragged down by host driven bus and by bus includes:Reset pulse period, the when of writing in initialization sequence
It is pulled down to since bus time slot in gap and is finally released as the high period, read to drag down bus holding in time slot since time slot
Period until 1 microsecond.
4. the bus arbitration system according to claim 1 based on single bus communication protocol, it is characterised in that:
The specific method of bus free judgement is:
If the bus is set using unified power supply power supply and without other independent current source nodes in the node of the Monobus network
It monitors to assert bus free when bus is high after standby electrification reset or after completing a bus transaction sequence;If described
Bus has multiple independent current source nodes, then after node device on it reset, when monitoring that bus is high, then continuous prison
Assert bus free after surveying one delay time section of bus.
5. the bus arbitration system according to claim 4 based on single bus communication protocol, it is characterised in that:
The delay time section is longest waiting time delay in bus operation sequence, i.e., the maximum of Yanzhong when its value is following
Value:Detect online in recovery latency between high time delay, bus operation time slot, the time delay in 1 time slot of read-write and feature operation etc.
Wait for time delay.
6. the bus arbitration system according to claim 1 based on single bus communication protocol, it is characterised in that:
The full 0 that the ROM command codes of the bus contention order are 8 is followed by 64 ROM of the host for starting transaction sequence
Code.
7. the bus arbitration system according to claim 1 based on single bus communication protocol, it is characterised in that:
The limited competition refers to, when the continuous competition frequency of failure of a host is more than or equal to its internal preset value, the host
Bus can be preengage using bus contention order in subsequent bus contention.
8. the bus arbitration system according to claim 1 based on single bus communication protocol, it is characterised in that:
The host selects search command having to explicitly to indicate the last one in a string of continuous transaction sequences using sky, and one is indicated with this
Series winding continues the end of transaction sequence.
9. the bus arbitration system according to claim 8 based on single bus communication protocol, it is characterised in that:
The sky selects the F0 that the ROM command codes of search command are 8,64 read-reads-of heel to write the 0th to the 63rd ROM code
Period;In the period, the return value for reading time slot twice since certain is 1, i.e., having to explicitly indicates this search and do not select
Node device in any one bus.
10. a kind of bus arbitration method based on single bus communication protocol is used for Monobus network, it is characterised in that use basis
System described in any one of claim 1-9.
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CN109992534A (en) * | 2019-03-22 | 2019-07-09 | 华北电力大学 | A kind of method and system of online fast search single wire device sequence number |
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CN114416622A (en) * | 2021-12-30 | 2022-04-29 | 深圳华芯集成电路设计有限公司 | Single bus communication system and method |
CN115361345A (en) * | 2022-10-24 | 2022-11-18 | 北京智芯微电子科技有限公司 | Data flow control method and device based on single bus information transmission and communication system |
CN116566761A (en) * | 2023-03-28 | 2023-08-08 | 成都电科星拓科技有限公司 | SPI dual-host sharing arbitration system and method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1801823A (en) * | 2006-01-10 | 2006-07-12 | 山西大学 | Single bus communication protocol with multi node equipment interconnection |
CN101499043A (en) * | 2009-03-12 | 2009-08-05 | 杭州士兰微电子股份有限公司 | Single-wire bus system and communication method |
CN101739372A (en) * | 2008-11-05 | 2010-06-16 | 联发科技股份有限公司 | Shared resource arbitration method and device thereof |
CN103201728A (en) * | 2010-10-08 | 2013-07-10 | 高通股份有限公司 | Arbitrating stream transactions based on information related to the stream transaction(s) |
CN104504888A (en) * | 2014-12-08 | 2015-04-08 | 国家电网公司 | Full-insulating bus multipoint temperature measuring single conductor communication system |
CN105955905A (en) * | 2016-04-18 | 2016-09-21 | 合肥工业大学 | Interface circuit based on serial bus structure and communication protocol |
CN107332746A (en) * | 2017-06-02 | 2017-11-07 | 上海申矽凌微电子科技有限公司 | A kind of unibus system based on Data Transport Protocol |
-
2017
- 2017-12-26 CN CN201711429281.2A patent/CN108287800B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1801823A (en) * | 2006-01-10 | 2006-07-12 | 山西大学 | Single bus communication protocol with multi node equipment interconnection |
CN101739372A (en) * | 2008-11-05 | 2010-06-16 | 联发科技股份有限公司 | Shared resource arbitration method and device thereof |
CN101499043A (en) * | 2009-03-12 | 2009-08-05 | 杭州士兰微电子股份有限公司 | Single-wire bus system and communication method |
CN103201728A (en) * | 2010-10-08 | 2013-07-10 | 高通股份有限公司 | Arbitrating stream transactions based on information related to the stream transaction(s) |
CN104504888A (en) * | 2014-12-08 | 2015-04-08 | 国家电网公司 | Full-insulating bus multipoint temperature measuring single conductor communication system |
CN105955905A (en) * | 2016-04-18 | 2016-09-21 | 合肥工业大学 | Interface circuit based on serial bus structure and communication protocol |
CN107332746A (en) * | 2017-06-02 | 2017-11-07 | 上海申矽凌微电子科技有限公司 | A kind of unibus system based on Data Transport Protocol |
Cited By (8)
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CN109992534A (en) * | 2019-03-22 | 2019-07-09 | 华北电力大学 | A kind of method and system of online fast search single wire device sequence number |
CN109992534B (en) * | 2019-03-22 | 2020-10-20 | 华北电力大学 | Method and system for rapidly searching serial number of single-wire device on line |
CN111510219A (en) * | 2020-04-15 | 2020-08-07 | 联合华芯电子有限公司 | Bidirectional optical fiber communication method in bus type network |
CN114416622A (en) * | 2021-12-30 | 2022-04-29 | 深圳华芯集成电路设计有限公司 | Single bus communication system and method |
CN115361345A (en) * | 2022-10-24 | 2022-11-18 | 北京智芯微电子科技有限公司 | Data flow control method and device based on single bus information transmission and communication system |
CN115361345B (en) * | 2022-10-24 | 2023-01-24 | 北京智芯微电子科技有限公司 | Data flow control method and device based on single bus information transmission and communication system |
CN116566761A (en) * | 2023-03-28 | 2023-08-08 | 成都电科星拓科技有限公司 | SPI dual-host sharing arbitration system and method |
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