CN108282079B - Multi-ring wide hysteresis current control method and circuit of grid-connected inverter - Google Patents

Multi-ring wide hysteresis current control method and circuit of grid-connected inverter Download PDF

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CN108282079B
CN108282079B CN201810083721.1A CN201810083721A CN108282079B CN 108282079 B CN108282079 B CN 108282079B CN 201810083721 A CN201810083721 A CN 201810083721A CN 108282079 B CN108282079 B CN 108282079B
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冯磊
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Yunnan Power Grid Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention relates to a grid-connected inverter control method, in particular to a multi-ring wide hysteresis current control method and a corresponding hardware circuit for realizing the method. The PWM driving circuit comprises a sampling conditioning circuit, wherein the output end of the sampling conditioning circuit is respectively connected with an effective value signal output circuit and a subtracter, the output end of the subtracter is connected with a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL is less than hH, and the current effective value signal output circuit, the double hysteresis comparator X1 and the double hysteresis comparator X2 are jointly connected with a CPLD for outputting PWM driving signals. The invention has the advantages that: the advantages of the traditional fixed loop width current control are reserved. This means that the multi-ring wide hysteresis current control inverter keeps the advantages of high stability and rapid dynamic performance; according to the practical application occasions, the specific ring width is determined by judging the effective value of the output current of the inverter, so that the switching loss of the power switching tube can be greatly reduced.

Description

Multi-ring wide hysteresis current control method and circuit of grid-connected inverter
Technical Field
The invention relates to a grid-connected inverter control method, in particular to a multi-ring wide hysteresis current control method and a corresponding hardware circuit for realizing the method.
Background
The fixed switching frequency PWM current control of the grid-connected inverter is sensitive to system parameters and load fluctuation, and when the voltage peak value Vm on the alternating current side of the three-phase inverter fluctuates, if the PWM switching frequency is fixed, the magnitude of a current tracking error also changes, so that the fixed switching frequency cannot meet the control system with high tracking accuracy requirements, and the problem can be solved through hysteresis control. When the current error exceeds the width of the hysteresis loop, the power switch tube of the main circuit is switched to force the current error to be reduced, so that the current error is controlled within a certain loop width range, and the tracking accuracy and the dynamic response speed are extremely high.
In practical engineering, the switching of the power switching tube is accompanied by conduction loss and cut-off loss, and the higher the switching frequency of the switching tube is, the larger the current flowing through the switching tube is, the larger the additional loss is. Therefore, it is necessary to reduce the switching frequency of the switching tube as much as possible according to the specific application, especially when working under high current. When the hysteresis control is adopted, the amplitude of the ripple current is in positive correlation with the hysteresis width, and the current waveform distortion rate is in positive correlation with the ratio of the amplitude of the ripple current to the effective value of the current. According to the rule, under the requirement of the same current waveform distortion rate, when the effective value of the current is smaller, the smaller width of the hysteresis loop is adopted to reduce the amplitude of the ripple current; when the effective value of the current is larger, the larger hysteresis width is adopted, and the limitation of the amplitude of the ripple current is sacrificed to reduce the switching frequency and further reduce the switching loss.
Disclosure of Invention
The invention aims to overcome the defects of the existing fixed-loop wide hysteresis current control technology, and provides a control circuit which not only retains the advantages of the traditional hysteresis current control, but also can reduce the switching loss of an inverter when outputting large current, and a control method which retains the advantages of the traditional hysteresis current control and can also reduce the switching loss of the inverter when outputting large current.
In order to solve the technical problems, the invention is realized by the following technical scheme: the output end of the sampling conditioning circuit is respectively connected with an effective value signal output circuit and a subtracter for generating an error current signal, the output end of the subtracter is connected with a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL < hH, and the current effective value signal output circuit, the double hysteresis comparator X1 and the double hysteresis comparator X2 are commonly connected with a CPLD for outputting PWM driving signals.
Furthermore, the effective value signal output circuit comprises an effective value conversion circuit for receiving the sampling current analog signal output by the sampling conditioning circuit, and the output end of the effective value conversion circuit is connected with an A/D chip for converting the current effective value analog signal output by the receiving effective value conversion circuit into a current digital effective value signal and outputting the current digital effective value signal to the CPLD.
A multi-ring wide hysteresis current control method of a grid-connected inverter comprises the following steps:
firstly, simultaneously inputting an inverter current error signal to a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL is less than hH, obtaining two original driving signals under different ring widths, namely hysteresis comparison output pulse signals, and inputting the signals to a CPLD;
and secondly, selecting an original driving signal with a corresponding ring width by the CPLD through judging the size relation between the actual measurement output current effective value of the inverter and a set threshold value, and forming a pair of complementary PWM driving signals with a dead zone to drive the switching tube of the main circuit of the inverter to act.
Further, the current error signal is obtained by inputting the sampling current analog signal converted by the sampling conditioning circuit and the reference current value into the subtractor, and is simultaneously input into the double hysteresis comparator X1 with the loop width of hL and the double hysteresis comparator X2 with the loop width of hH through calculation of the subtractor.
The generating step of the current effective value comprises the following steps:
firstly, converting an output value of an inverter current sensor into a sampling current analog signal through a sampling conditioning circuit;
secondly, converting the sampling current analog signal into a current effective value analog signal through an effective value conversion circuit;
and thirdly, converting the current effective value + -analog signal into a current effective value digital signal through an A/D chip and transmitting the current effective value digital signal to the CPLD.
Further, the judging step of the original driving signal is;
firstly, respectively setting an upper threshold value and a lower threshold value of a current effective value, comparing the current effective value with the lower threshold value, if the current effective value is smaller than the lower threshold value, taking the output value of a double hysteresis comparator X1 with a smaller ring width as the output value of an original driving signal, otherwise, entering the next step;
comparing the current effective value with an upper threshold value, if the current effective value is lower than the upper threshold value, taking the value of the original driving signal output in the last judgment as the output value of the original driving signal of the current time, and otherwise, entering the next step;
and thirdly, if the effective value of the current is larger than the upper threshold value, taking the output value of the double hysteresis comparator X2 with larger loop width as the output value of the original driving signal.
In the hysteresis current control of the inverter, when the upper bridge arm of the inverter bridge is conducted (delta t)1A time period) of time,
Figure BDA0001561773270000031
Δt1current i in time intervalLFrom iLrefH rises to iLref+ h, so that formula (1) is approximately
Figure BDA0001561773270000032
When the lower bridge arm of the inverter is conducted (delta t)2A time period) of time,
Figure BDA0001561773270000033
Δt2current i in time intervalLFrom iLref+ h down to iLrefH, so that formula (3) is approximately
Figure BDA0001561773270000041
The hysteresis PWM switching period obtained by the formula (2) and the formula (4) is
Figure BDA0001561773270000042
E is to bes＝Esmsin (ω t) is substituted in formula (5) and is simplified as:
Figure BDA0001561773270000043
PWM switching frequency
Figure BDA0001561773270000044
The main symbol names in the above equation: l-inverter filter inductance value. i.e. iL-inverter output current value. v. ofdc-the value of the dc side voltage of the inverter. e.g. of the types-grid connection point voltage value. Δ t1-time of current rise. Δ t2-time of current drop. T issThe hysteresis loop controls the PWM switching period. f. ofsThe hysteresis loop controls the PWM switching frequency. i.e. iLref-an inverter reference current value. h is the value of the hysteresis loop width. Esm-grid-connected point voltage magnitude.
As can be seen from equation (7), when the dc-side capacitor voltage, the filter inductance, and the grid voltage amplitude are fixed, the switching frequency at the same phase is inversely proportional to the hysteresis loop width.
Based on the inverse relation between the switching frequency and the width of the hysteresis loop, the multi-loop width hysteresis current control method provided by the invention adjusts the switching frequency by selecting the width of the hysteresis loop, and indirectly controls the switching loss of the power switching tube. The method specifically comprises the following two steps: the first step is that the inverter current error signal is simultaneously input into a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL is less than hH, the original driving signals under two different ring widths, namely hysteresis comparison output pulse signals, are obtained and input into CPLD, and the double hysteresis comparator is in an operation logic formula (8). And the second step is that the CPLD selects an original driving signal with a corresponding ring width by judging the size relation between the actual measurement output current effective value of the inverter and a set threshold value, the selection method is as the formula (9), and a pair of complementary PWM driving signals with a dead zone are formed to drive the switching tube of the main circuit of the inverter to act.
Figure BDA0001561773270000051
Figure BDA0001561773270000052
The main symbol names in the above equation: d (k +1) -hysteresis comparison output pulse signal. d (k) -the last hysteresis comparison outputs the pulse signal. Δ i — output current error signal. U shapeH-a logic high level. U shapeL-a logic low level. h is the loop width of the double hysteresis comparator, and h is hL for double hysteresis comparator X1 and hH for double hysteresis comparator X2. h (k +1) -the current ring width value. h (k) -the previous cycle width value. I isL-an effective value of the inverter output current. I issetL-lower threshold value of the effective value of the inverter output current. I issetH-an upper threshold value for the effective value of the output current. h isH-larger value of the ring width. h isL-smaller value of the ring width.
The generation of the error current and the calculation of the effective value of the current are implemented by a hardware circuit, which is specifically described as follows:
the sensor signal from the output current of the inverter passes through a sampling conditioning circuit, the signal is divided into two paths, one path is input to the positive end of the subtracter, and the other path is input to an effective value conversion circuit(ii) a Reference current iLrefThe analog signal is input to the negative end of the subtracter, and the error current signal of the inverter is obtained after the processing of the subtracter. And the current effective value analog signal output by the effective value conversion circuit is input to an A/D chip to obtain a current effective value digital signal. And the CPLD receives the output signal from the A/D chip to acquire the effective value of the output current of the inverter.
The invention is characterized in that the hysteresis loop comparator with the corresponding loop width is selected according to the effective value of the actual output current of the inverter, and the switching loss of the power switching tube is reduced by selecting the size of the hysteresis loop width while the change of the reference value of the filter inductance current tracking current of the inverter is realized.
Compared with the prior art, the invention has the advantages that: the advantages of the traditional fixed loop width current control are reserved. This means that the multi-ring wide hysteresis current control inverter keeps the advantages of high stability and rapid dynamic performance; according to the practical application occasions, the specific ring width is determined by judging the effective value of the output current of the inverter, so that the switching loss of the power switching tube can be greatly reduced.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a hardware architecture diagram of multi-loop wide hysteretic current control;
fig. 2 is a flowchart of a process for selecting a loop width for a CPLD.
In the figure; 1, a sampling conditioning circuit; 2, a current effective value signal output circuit; 3, a subtracter; 4, an effective value conversion circuit; 5, A/D chip.
Detailed Description
The invention is described in detail below with reference to the following figures and embodiments:
the output end of the sampling conditioning circuit 1 is respectively connected with an effective value signal output circuit 2 and a subtracter 3 for generating an error current signal, the output end of the subtracter 3 is connected with a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL < hH, and the current effective value signal output circuit 2, the double hysteresis comparator X1 and the double hysteresis comparator X2 are jointly connected with a CPLD for outputting PWM driving signals.
Furthermore, the effective value signal output circuit comprises an effective value conversion circuit 4 for receiving the sampling current analog signal output by the sampling conditioning circuit, and an A/D chip 5 for converting the current effective value analog signal output by the receiving effective value conversion circuit 4 into a current digital effective value signal and outputting the current digital effective value signal to the CPLD is connected to the output end of the effective value conversion circuit 4.
A multi-ring wide hysteresis current control method of a grid-connected inverter specifically comprises the following two steps:
the first step is that the inverter current error signal is simultaneously input into a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL is less than hH, the original driving signals under two different ring widths, namely hysteresis comparison output pulse signals, are obtained and input into CPLD, and the double hysteresis comparator is in an operation logic formula (1).
And the second step is that the CPLD selects an original driving signal with a corresponding ring width by judging the size relation between the actual measurement output current effective value of the inverter and a set threshold value, the selection method is as the formula (2), and a pair of complementary PWM driving signals with a dead zone are formed to drive the switching tube of the main circuit of the inverter to act. A program flow diagram for a CPLD is shown in fig. 2.
Figure BDA0001561773270000071
Figure BDA0001561773270000072
The main symbol names in the above equation: d (k +1) -hysteresis comparison output pulse signal. d (k) -the last hysteresis comparison outputs the pulse signal. Δ i — output current error signal. U shapeH-a logic high level. U shapeL-a logic low level. h is the loop width of the double hysteresis comparator, and h is hL for double hysteresis comparator X1 and hH for double hysteresis comparator X2. h (k +1) -Current RingAnd a wide value. h (k) -the previous cycle width value. I isL-an effective value of the inverter output current. I issetL-lower threshold value of the effective value of the inverter output current. I issetH-an upper threshold value for the effective value of the output current. h isH-larger value of the ring width. h isL-smaller value of the ring width.
The generation of the error current and the calculation of the effective value of the current are implemented by a hardware circuit, which is specifically described as follows:
a sensor signal from the output current of the inverter passes through the sampling conditioning circuit 1, the signal is divided into two paths, one path is input to the positive end of the subtracter 3, and the other path is input to the effective value conversion circuit 4; reference current iLrefThe analog signal is input to the negative terminal of the subtracter 3, and the error current signal of the inverter is obtained after the processing of the subtracter 3. The analog signal of the effective value of the current output by the effective value conversion circuit 4 is input to the a/D chip 5 to obtain the digital signal of the effective value of the current. And the CPLD receives the output signal from the A/D chip to acquire the effective value of the output current of the inverter.
It is to be emphasized that: the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention in any way, and all simple modifications, equivalent changes and modifications made to the above embodiments according to the technical spirit of the present invention are within the scope of the technical solution of the present invention.

Claims (4)

1. The multi-ring wide hysteresis current control method of the grid-connected inverter is characterized in that a multi-ring wide hysteresis current control circuit of the grid-connected inverter comprises a sampling conditioning circuit used for receiving a sensor signal of the inverter, the output end of the sampling conditioning circuit is respectively connected with an effective value signal output circuit and a subtracter used for generating a current error signal, the output end of the subtracter is connected with a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL is less than hH, and the effective value signal output circuit, the double hysteresis comparator X1 and the double hysteresis comparator X2 are commonly connected with a CPLD used for outputting a PWM driving signal;
the method comprises the following steps:
firstly, simultaneously inputting an inverter current error signal to a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH, wherein hL is less than hH, obtaining two original driving signals under different ring widths, namely hysteresis comparison output pulse signals, and inputting the signals to a CPLD;
secondly, selecting an original driving signal with a corresponding ring width by the CPLD through judging the magnitude relation between an actual current effective value output by the inverter and an upper threshold value and a lower threshold value of a preset current effective value, and forming a pair of complementary PWM driving signals with a dead zone to drive a main circuit switching tube of the inverter to act;
the judging step of the original driving signal is as follows;
firstly, respectively setting an upper threshold value and a lower threshold value of a current effective value, comparing the current effective value with the lower threshold value, if the current effective value is smaller than the lower threshold value, taking the output value of a double hysteresis comparator X1 with a smaller ring width as the output value of an original driving signal, otherwise, entering the next step;
comparing the current effective value with an upper threshold value, if the current effective value is lower than the upper threshold value, taking the value of the original driving signal output in the last judgment as the output value of the original driving signal of the current time, and otherwise, entering the next step;
and thirdly, if the effective value of the current is larger than the upper threshold, taking the output value of the double hysteresis comparator X2 with larger loop width as the output value of the original driving signal.
2. The method for controlling the multi-ring wide hysteresis current of the grid-connected inverter according to claim 1, characterized in that: the effective value signal output circuit comprises an effective value conversion circuit used for receiving a sampling current analog signal output by the sampling conditioning circuit, and the output end of the effective value conversion circuit is connected with an A/D chip used for converting the current effective value analog signal output by the effective value conversion circuit into a current effective value digital signal and outputting the current effective value digital signal to the CPLD.
3. The method for controlling the multi-ring wide hysteresis current of the grid-connected inverter according to claim 1, characterized in that: the current error signal is obtained by inputting a sampling current analog signal converted by the sampling conditioning circuit and a reference current value into a subtracter, and is simultaneously input into a double hysteresis comparator X1 with the ring width of hL and a double hysteresis comparator X2 with the ring width of hH through calculation of the subtracter.
4. The method for controlling the multi-ring wide hysteresis current of the grid-connected inverter according to claim 1, characterized in that: the generating step of the current effective value comprises the following steps:
firstly, converting an output value of an inverter current sensor into a sampling current analog signal through a sampling conditioning circuit;
secondly, converting the sampling current analog signal into a current effective value analog signal through an effective value conversion circuit;
and thirdly, converting the current effective value analog signal into a current effective value digital signal through an A/D chip and transmitting the current effective value digital signal to the CPLD.
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