CN108259344B

CN108259344B - Telemeasuring method and device

Info

Publication number: CN108259344B
Application number: CN201711225464.2A
Authority: CN
Inventors: 宋高; 敖襄桥; 乔剡; 李佳; 高瑞昌
Original assignee: Hangzhou H3C Technologies Co Ltd
Current assignee: Hangzhou H3C Technologies Co Ltd
Priority date: 2017-11-29
Filing date: 2017-11-29
Publication date: 2020-12-29
Anticipated expiration: 2037-11-29
Also published as: CN108259344A

Abstract

Telemetry methods and apparatus are provided. In the application, the switching device serving as the INT starting point device constructs a message on the basis of the original message through the ASIC chip, and executes INT based on the constructed message, which has no influence on the forwarding of the original message; furthermore, the switching device serving as the INT starting point device adds INT head and INT Metadata information on the constructed message through the mutual cooperation of the ASIC chip and the FPGA to realize INT, and the INT head and INT Metadata information are not added by the ASIC chip independently to realize INT, so that the defect that the INT cannot be supported by the ASIC chip due to limited data plane processing capacity is prevented; the INT is implemented between switching devices in a data center network.

Description

Telemeasuring method and device

Technical Field

The present application relates to network communication technologies, and in particular, to a Telemetry (telemetrology) method and apparatus.

Background

The remote measurement is a technology for transmitting a short-distance measurement value of a target object to a long-distance measurement station to realize long-distance measurement, and the remote measurement technology is a novel technology with good integration performance, good tracking performance and good remote control performance and is widely applied.

In networking applications, telemetry provides great convenience for network maintenance and diagnostics. At present, there are some drafts for telemetry functions, which define metadata (Meatadata) of telemetry messages and bearer modes.

Telemetry is subdivided into In-band Telemetry (INT). INT is a framework designed to collect and report network status. INT is implemented by the data plane and does not require interference by the control plane.

However, for the switching devices in the data center network, the data plane processing capability of an Application Specific Integrated Circuit (ASIC) chip for data plane processing is limited, so that the ASIC chip cannot support INT and cannot implement INT between the switching devices in the data center network.

Disclosure of Invention

Telemetry methods and apparatus are provided to implement INT between switching devices in a data center network.

The technical scheme provided by the application comprises the following steps:

a telemetry method applied in a data centre network, the method being applied to a switching device, when said switching device is designated as an in-band telemetry INT start device, the method comprising:

an ASIC forwarding chip of the switching equipment receives a first message, determines that the first message is matched with an INT condition, constructs a second message according to the first message and sends the second message to a Field Programmable Gate Array (FPGA) of the switching equipment; the message characteristic information of the second message is the same as the message characteristic information of the first message;

the FPGA receives a second message, an INT (INT) head is added to the second message, and the second message added with the INT head is sent back to the ASIC forwarding chip;

and the ASIC forwarding chip receives the second message added with the INT header, adds INT Metadata information on the received second message and forwards the second message.

A telemetry method applied to a data center network is applied to a switching device and comprises the following steps:

receiving a second message;

checking that the second packet carries an in-band telemetry INT header, if so,

when the switching equipment is designated as INT intermediate equipment, adding INT Metadata information on the second message and forwarding;

and when the switching equipment is designated as INT end point equipment, redirecting the second message to designated INT collection equipment for collecting INT information.

A telemetry apparatus for use in a data center network, the apparatus for use in a switching device, comprising: more than two interfaces, an ASIC forwarding chip and a field programmable gate array FPGA;

the ASIC forwarding chip is used for determining that a first message received by one of the more than two interfaces matches an INT condition when the switching equipment is designated as an in-band remote INT starting point equipment, constructing a second message according to the first message and sending the second message to the FPGA; the message characteristic information of the second message is the same as the message characteristic information of the first message;

the FPGA is used for receiving a second message, adding an INT (INT) header to the second message and sending the second message added with the INT header back to the ASIC forwarding chip;

the ASIC forwarding chip is further used for receiving a second message added with an INT header, adding INT Metadata information on the received second message, and selecting an interface from the more than two interfaces to forward the second message added with the INT Metadata information.

A telemetry apparatus for use in a data center network, the apparatus for use in a switching device, comprising: more than two interfaces and an application specific integrated circuit ASIC forwarding chip,

one interface of the more than two interfaces receives a second message;

the ASIC forwarding chip is used for checking that the second message carries an in-band telemetry INT head, and adding INT Metadata information on the second message and selecting one interface from the more than two interfaces for forwarding when the switching equipment is designated as INT intermediate equipment; and when the switching equipment is designated as INT end equipment, redirecting the second message to the INT collection equipment through an interface of INT collection equipment which is connected and designated in the two or more interfaces and used for collecting INT information.

According to the technical scheme, in the application, the switching equipment serving as the INT starting point equipment constructs a message on the basis of the original message through the ASIC chip, and the INT is executed based on the constructed message, so that the forwarding of the original message is not influenced;

furthermore, the switching device serving as the INT starting point device adds INT head and INT Metadata information on the constructed message through the mutual cooperation of the ASIC chip and the FPGA to realize INT, and the INT head and INT Metadata information are not added by the ASIC chip independently to realize INT, so that the defect that the INT cannot be supported by the ASIC chip due to limited data plane processing capacity is prevented;

furthermore, the switching device serving as the INT intermediate device directly adds INT Metadata information to the message and forwards the message when the message carries an INT header, other operations for INT are not required to be executed additionally, the operation is simple, and the INT is sufficiently ensured to be realized within the capability of a data forwarding plane of the ASIC chip;

finally, the switching device serving as the INT end point device directly redirects the message to the INT collection device when the message carries the INT head, the INT head does not need to be stripped, the method is simple, and the INT implementation is guaranteed within the data forwarding plane capacity of the ASIC chip.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a flow chart of a first method provided herein;

FIG. 2 is a flow chart of a second method provided herein;

FIG. 3 is a flow chart of a third method provided herein;

fig. 4 is a schematic diagram of application networking provided by the present application;

FIG. 5 is a schematic diagram of an application of an embodiment provided in the present application;

FIG. 6 is a schematic diagram of an INT header format provided herein;

fig. 7 is a schematic diagram of an INT Metadata information 1 format provided in the present application;

FIG. 8 is a block diagram of the apparatus provided in the present application;

fig. 9 is a diagram of another apparatus structure provided in the present application.

Detailed Description

In a data center network, if it is required to know the network status, such as delay, between two switching devices, it is a common way to perform INT between the two switching devices to obtain the network status, such as delay, between the two switching devices.

However, as described in the background, the ASIC chip for data plane processing on the switching device has limited data plane processing capability and cannot support INT.

Based on this, in the present application, an improvement is made to INT, which is mainly reflected in:

1. in the switching device serving as the INT starting point device, the INT is not executed by an ASIC chip of the switching device alone, but is executed by the ASIC chip of the switching device and a Field Programmable Gate Array (FPGA) of the switching device in cooperation with each other, and when the INT is executed by the ASIC chip and the FPGA in cooperation, an originally received message is not used, but a message is reconstructed to ensure that a normally forwarded message is not affected by the INT, which is specifically shown in the flow illustrated in fig. 1.

2. In the switching device as an INT intermediate device, when an ASIC chip receives a message carrying an INT header, INT Metadata (Metadata) information is directly added in the message. See in particular the flow shown in figure 2.

3. In the switching device as the INT end point device, when the ASIC chip receives the message carrying the INT head, the INT head of the message does not need to be stripped, and the message is directly redirected to the appointed INT collecting device for collecting INT information. See in particular the flow shown in figure 3.

It should be noted that, in the present application, the INT start point device, the INT intermediate device, and the INT end point device described above are pre-specified by a network management device such as a network controller according to requirements. For example, in the networking shown in fig. 4, if INT is executed between the switching device 401 and the switching device 405 according to a service requirement to obtain a network state, such as a delay, between the switching device 401 and the switching device 405, the network management device may designate the switching device 401 as an INT starting point device, the switching device 402 and the switching device 403 from the switching device 401 to the switching device 405 are INT intermediate devices, and the switching device 405 is an INT ending point device.

Based on the above description, the flow shown in fig. 1 provided by the present application is described below:

referring to fig. 1, fig. 1 is a flow chart of a first method provided in the present application. The procedure applies to a switching device, wherein the switching device is designated as an INT origin device.

As shown in fig. 1, the process may include the following steps:

step 101, an ASIC forwarding chip of the switching device receives a first message.

In this step 101, the first message generally refers to any message, and the naming is only for convenience of description and is not limited in this application.

And 102, the ASIC forwarding chip determines that the first message is matched with the INT condition, constructs a second message according to the first message and sends the second message to the FPGA of the switching equipment.

In order to ensure that the normal forwarding of the first packet is not affected, in this step 102, the ASIC forwarding chip further needs to forward the first packet. The mode of forwarding the first message is similar to the existing message forwarding mode and is not limited any more.

As an embodiment, in this step 102, constructing the second message according to the first message may specifically include: and copying one copy of the first message to obtain a second message. Here the second message obtained by copying a copy of the first message is identical to the first message.

As another embodiment, in this step 102, constructing the second message according to the first message may specifically include: constructing a new second message, wherein the second message is different from the first message in that: the second message does not carry the load (Payload) of the first message; or copying a copy of the first packet and deleting the Payload (Payload) carried by the copied first packet. The second packet obtained here is different from the first packet in that it does not carry the payload of the first packet. Here, the second packet does not carry the load of the first packet, and the purpose is to save the bandwidth occupied by the transmission of the subsequent second packet.

As can be seen from the above description, regardless of whether the second packet constructed by the ASIC forwarding chip carries the load of the first packet, the packet feature information carried by the second packet constructed by the ASIC forwarding chip is the same as the packet feature information of the first packet. As an embodiment, the message feature information may be: message five tuple information and/or an encapsulation header such as a VXLAN header, etc.

It should be noted that, in the present application, the ASIC forwards the second message to the FPGA through the chip, so that the FPGA adds the INT header to the second message. Based on this, as an embodiment, in the present application, the ASIC forwarding chip may carry a specified flag in the second message sent to the FPGA. The designated mark is used for indicating to add an INT head so as to indicate the FPGA to add the INT head for the second message.

And 103, receiving the second message by the FPGA, adding an INT (INT) head to the second message, and sending the second message added with the INT head back to the ASIC (application specific integrated circuit) forwarding chip.

As described above, the second message sent by the ASIC forwarding chip to the FPGA carries a designation flag indicating that an INT header is added. Thus, in this step 103, when the FPGA receives the second message, it checks that the second message carries the specified flag, and adds the INT header to the second message.

It should be noted that, as described above, the designation mark is used to indicate that the INT header is added, that is, after the INT header is added to the second packet by the FPGA, the designation mark has no any significance, and based on this, as an embodiment, in this application, after the INT header is added to the second packet by the FPGA, the designation mark carried by the second packet may be further deleted.

And 104, the ASIC forwarding chip receives the second message added with the INT header, adds INT Metadata information on the received second message and forwards the second message.

In the second message, the INT Metadata information is adjacent to and following the INT header. The INT Metadata information here mainly includes INT related information.

As described above, the second packet, regardless of whether it carries the load of the first packet, ultimately definitely carries the packet characteristic information of the first packet, where the packet characteristic information at least includes the destination address (destination IP address or destination MAC address) of the packet, and based on this, in this step 104, the ASIC forwarding chip may forward the second packet according to the destination address (destination IP address or destination MAC address) of the second packet.

So far, the description shown in fig. 1 is completed.

When the switching device designated as the INT start device forwards the second packet according to the flow shown in fig. 1, the switching device designated as the INT intermediate device receives the second packet. The following describes, with reference to fig. 2, a process executed when the switching device serving as an INT intermediate device receives the second packet:

referring to fig. 2, fig. 2 is a flow chart of a second method provided by the present application. The procedure applies to the switching device as an INT intermediate device.

As shown in fig. 2, the process may include the following steps:

step 201, receiving a second message; if the second packet is checked to carry the INT header, step 202 is executed.

And 202, adding INT Metadata information to the second message and forwarding the INT Metadata information.

In this step 202, INT Metadata information is added to the second packet, where the added INT Metadata information is the last INT Metadata information of the second packet.

As described above, the second packet, regardless of whether it carries the payload of the first packet, will eventually and certainly carry the packet characteristic information of the first packet, where the packet characteristic information at least includes the destination address (destination IP address or destination MAC address) of the packet, and based on this, in this step 202, when the second packet to which the INT Metadata information is added is forwarded, the second packet can be forwarded according to the destination address (destination IP address or destination MAC address) of the second packet. This is similar to existing packet forwarding procedures.

Thus, the flow shown in fig. 2 is completed.

It should be noted that, the above steps 201 to 202 may be performed by an ASIC forwarding chip of the switching device as the INT intermediate device.

When the switching device designated as the INT intermediate device forwards the second packet according to the flow shown in fig. 2, the switching device designated as the INT destination device receives the second packet. The following describes, with reference to fig. 3, the process executed when the switching device, which is an INT endpoint device, receives the second packet:

referring to fig. 3, fig. 3 is a flow chart of a third method provided in the present application. The procedure applies to a switching device that is an INT endpoint device.

As shown in fig. 3, the process may include the following steps:

step 301, receiving a second message; if the second packet is checked to carry the INT header, step 302 is executed.

Step 302, redirecting the second message to an INT collection device for collecting INT information.

In this application, the INT collection device is a specially designated device responsible for collecting INT information, and can realize network monitoring between the INT start point device and the INT end point device through interaction with a network management device in a data center network.

The flow shown in fig. 3 is completed.

It should be noted that, the above steps 301 to 302 can be executed by an ASIC forwarding chip of the switching device as the INT endpoint device.

The flow shown in fig. 1 to 3 is described below based on an embodiment:

referring to fig. 5, fig. 5 is a diagram of an application networking of an embodiment provided in the present application. In fig. 5, if the service requirements are: determining the network delay of the message sent from the switching device 501 to the switching device 503, the network management device 500 determines to execute INT between the switching device 501 and the switching device 503, wherein the network management device 500 designates the switching device 501 as an INT starting device and notifies the switching device 501, designates the switching device 502, via which the message is sent from the switching device 501 to the switching device 503, as an INT intermediate device and notifies the switching device 502, and designates the switching device 503 as an INT destination device and notifies the switching device 503.

In fig. 5, the network management device 500 further needs to issue an ACL for INT (denoted as a first ACL) to the switching device 501 designated as an INT starting point device, where a matching item in the first ACL is an INT condition, where the INT condition specifically includes: INT parameter information, such as message feature information, such as quintuple information, and/or a messaging port; the actions in the first ACL are: and constructing another message according to the message matched with the INT condition, carrying a designated mark for indicating the addition of the INT head on the constructed message and uploading the designated mark to the FPGA.

In fig. 5, the network management device 500 further needs to issue an ACL (denoted as a second ACL) for INT to the switching device 502 designated as an INT intermediate device, where a matching item of the second ACL is: the INT header is carried, and the actions of the second ACL are: and adding INT Metadata information to the message carrying the INT header.

In fig. 5, the network management device 500 further needs to issue an ACL for INT (denoted as a third ACL) to the switching device 503 designated as an INT endpoint device, where a matching item of the third ACL is: the action of carrying the INT header, the third ACL is: redirected to a designated INT collection device for collecting INT information.

As shown in fig. 5, the ASIC forwarding chip (denoted as chip 5_1) of the switching device 501 receives a message (denoted as message a1) through the local Port 1.

The chip 5_1 finds that the switch device 501 is designated as an INT start device, and determines INT parameter information according to the message a1, where the INT parameter information is exemplified by the message quintuple information of the message a 1.

If the INT parameter information determined by the chip 5_1 is matched with the INT condition as the matching item in the local first ACL, a message is constructed according to the action of the first ACL, in this embodiment, the construction message of the chip 5_1 is, for example: chip 5_1 copies a copy of message a 1. For the sake of distinguishing from the message a1, the message a1 obtained by copying is referred to as a message a 2.

The chip 5_1 carries a specified tag for indicating that the INT header is added on the message a2 according to the action of the first ACL, and sends the specified tag to the FPGA of the switching device 501. It should be noted that, in order not to affect the forwarding of the message a1, here, the chip 5_1 further needs to forward the message a1 according to the destination address of the message a1, such as the destination IP address or the destination MAC address, so as to ensure the normal forwarding of the message a 1.

And the FPGA receives the message a2, and if the message a2 is found to carry a designated mark for indicating adding of an INT (integrated circuit) header, the INT header is added to the message a 2. In one embodiment, the INT header added by the FPGA at the message a2 is adjacent to and after the specified header, such as the UDP header, of the message a2 (this is equivalent to an INT header prepending). In another embodiment, the INT header added by the FPGA at message a2 is after the entire message (including the payload) of message a2 (this is equivalent to INT header backpatching). Fig. 6 illustrates a format diagram of the INT. In FIG. 6, Probe marker (1), Probe marker (2): indicates an INT head; message Type: indicates the type of INT header; flag: flag indicating INT header, Request Vector: indicates the type of telemetric, multiple types each indicated with 1 bit, HOP Limit: represents the maximum HOP Count, HOP Count: representing the number of hops passed; maximum length: the maximum length of the following INT Metadata (Metadata) information is shown, and the Current length is the length of the INT Metadata information which needs to be added currently.

And after the FPGA adds the INT header in the message a2, deleting the specified mark which is carried in the message a2 and used for indicating the addition of the INT header. For convenience of description, the packet a2 with the INT header added and the designated tag deleted is referred to as packet a 3.

The FPGA sends a message a3 back to the chip 5_ 1.

The chip 5_1 receives the message a3, adds INT Metadata information to the message a3 and forwards the INT Metadata information. For convenience of description, the message a3 to which the INT Metadata information is added is referred to as a message a 4. Here, the INT Metadata information (denoted as INT Metadata information 1) added by the message a4 is adjacent to and subsequent to the INT header. Fig. 7 illustrates INT Metadata information 1. In fig. 7, Device ID: an ID indicating the switching device 501; receive Seconds: a message reception timestamp is represented; ingress Port: representing a message input port; transmit Seconds: representing a message transmission timestamp; egress Port: an output port for representing a transmission message; queue ID: an egress port queue representing a message; CongetionCongestion flag, Drop count: indicating the packet loss count. Here, the chip 5_1 may forward the message a4 according to a destination address of the message a4, such as a destination IP address or a destination MAC address.

The ASIC forwarding chip (denoted chip 5_2) of the switching device 502 receives the message a4 through the local Port 2.

And the chip 5_2 finds that the switching equipment 502 is designated as an INT intermediate equipment, checks that the message a4 carries an INT header and is just matched with the matching item of the second ACL, adds INT Metadata information on the message a4 according to the action of the second ACL and sends the INT Metadata information. For convenience of description, the message a4 to which the INT Metadata information is added is referred to as a message a 5. Here, the INT Metadata information (denoted as INT Metadata information 2) added by the message a5 is the last INT Metadata information in the message a 5. Here, the chip 5_2 may forward the message a5 according to a destination address of the message a5, such as a destination IP address or a destination MAC address.

The ASIC forwarding chip (denoted chip 5_3) of the switching device 503 receives the message a5 through the local Port 3.

And the chip 5_3 finds that the switching device 503 is designated as an INT end point device, detects that the message a5 carries an INT header and is just matched with a matching item of the third ACL, redirects the message a5 to an INT collection device according to the action of the third ACL, and realizes network monitoring between the INT start point device and the INT end point device through interaction with gateway devices in the data center network by the INT collection device.

Thus, the description of the embodiments is completed.

As can be seen from the description of the above embodiments, in the present application, the switching device serving as an INT starting point device constructs a packet based on an original packet through the ASIC chip, and executes INT based on the constructed packet, which has no influence on the forwarding of the original packet;

The methods provided herein are described above. The following describes the apparatus provided in the present application:

referring to fig. 8, fig. 8 is a diagram illustrating the structure of the apparatus according to the present invention. The device is applied to the switching equipment and comprises: more than two interfaces 801, an ASIC forwarding chip 802 and an FPGA 803.

The ASIC forwarding chip 802 is configured to, when the switching device is designated as an in-band telemetry INT starting point device, determine that a first message received by one of the two or more interfaces matches an INT condition, construct a second message according to the first message, and send the second message to the FPGA 803; the message characteristic information of the second message is the same as the message characteristic information of the first message;

the FPGA803 is configured to receive a second packet, add an INT header to the second packet, and send the second packet with the INT header added back to the ASIC forwarding chip 802;

the ASIC forwarding chip 802 is further configured to receive a second message to which an INT header is added, add INT Metadata information to the received second message, and select one interface from the two or more interfaces to forward the second message to which the INT Metadata information is added. The interface selected here is not the interface on which the message is received, but is selected in dependence on the destination address of the second message, such as the destination IP address or the destination MAC address.

As an embodiment, the constructing, by the ASIC forwarding chip 802, the second packet according to the first packet includes:

and copying one copy of the first message to obtain a second message.

As an embodiment, a second message sent by the ASIC forwarding chip 802 to the FPGA803 carries a specific flag, where the specific flag is used to indicate that an INT header is added;

after the FPGA803 adds the INT header to the second packet, the method further includes: and deleting the designated mark carried by the second message.

As an embodiment, the INT header is adjacent to and behind a specified header of the second packet; or, the INT header is located after the entire packet of the second packet;

the INT Metadata information is adjacent to and subsequent to the INT header.

Thus, the description of the device structure shown in fig. 8 is completed.

It should be noted that the apparatus shown in fig. 8 is only for listing the interface, the ASIC forwarding chip 801, and the FPGA802 related to the method of the present application, and is not intended to limit the apparatus.

Referring to fig. 9, fig. 9 is a block diagram of another apparatus provided in the present application. The device is applied to the switching equipment and comprises: more than two interfaces 901, an ASIC forwarding chip 902.

One interface of the more than two interfaces receives a second message;

an ASIC forwarding chip 902, configured to check that the second packet carries an in-band telemetry INT header, and add INT Metadata information to the second packet and select one interface from the two or more interfaces for forwarding when the switching device is designated as an INT intermediate device; and when the switching equipment is designated as INT end equipment, redirecting the second message to the INT collection equipment through an interface of INT collection equipment which is connected and designated in the two or more interfaces and used for collecting INT information.

Thus, the apparatus shown in fig. 9 is completed.

It should be noted that the apparatus shown in fig. 9 is only for listing the interface, ASIC forwarding chip 902 related to the method of the present application, and is not used to limit the apparatus.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A telemetry method applied in a data centre network, characterized in that it is applied to a switching device, when said switching device is designated as an in-band telemetry INT start device, the method comprising:

2. The method of claim 1, wherein constructing the second packet from the first packet comprises:

and copying one copy of the first message to obtain a second message.

3. The method according to claim 1, wherein a second message sent by the ASIC forwarding chip to the FPGA carries a specific flag, and the specific flag is used to indicate addition of an INT header;

after the FPGA adds the INT header to the second packet, the method further includes: and deleting the designated mark carried by the second message.

4. The method of claim 1, wherein the INT header is adjacent to and after a designated header of the second packet; or, the INT header is located after the entire packet of the second packet;

the INT Metadata information is adjacent to and subsequent to the INT header.

5. A telemetry method applied to a data center network is characterized in that the method is applied to a switching device and comprises the following steps:

receiving a second message;

checking that the second message carries an in-band telemetry INT head, wherein the INT head is added by an FPGA of the switching equipment after constructing a message with the same message characteristic information as that of the first message according to the received first message by an ASIC forwarding chip of the switching equipment which is designated as an in-band telemetry INT starting point device under the condition that the first message is matched with INT; then the process of the first step is carried out,

6. A telemetry apparatus for use in a data center network, the apparatus for use in a switching device, comprising: more than two interfaces, an ASIC forwarding chip and a field programmable gate array FPGA;

7. The apparatus of claim 6, wherein constructing the second packet from the first packet by the ASIC forwarding chip comprises:

and copying one copy of the first message to obtain a second message.

8. The device according to claim 6, wherein a second packet sent by the ASIC forwarding chip to the FPGA carries a specific flag, and the specific flag is used to indicate addition of an INT header;

9. The apparatus of claim 6, wherein the INT header is adjacent to and after a designated header of the second packet; or, the INT header is located after the entire packet of the second packet;

the INT Metadata information is adjacent to and subsequent to the INT header.

10. A telemetry apparatus for use in a data center network, the apparatus for use in a switching device, comprising: more than two interfaces and an application specific integrated circuit ASIC forwarding chip,

one interface of the more than two interfaces receives a second message;

the ASIC forwarding chip is used for checking that the second message carries an in-band telemetry INT head, and the INT head is added by an FPGA of the switching equipment after constructing a message with the same message characteristic information as that of the first message according to the received first message by an ASIC forwarding chip of the switching equipment which is designated as an in-band telemetry INT starting point device under the condition that the first message is matched with INT; then, when the switching device is designated as an INT intermediate device, adding INT Metadata information on the second message and selecting one interface from the more than two interfaces for forwarding; and when the switching equipment is designated as INT end equipment, redirecting the second message to the INT collection equipment through an interface of INT collection equipment which is connected and designated in the two or more interfaces and used for collecting INT information.