CN108257994A - The manufacturing method of semiconductor device - Google Patents
The manufacturing method of semiconductor device Download PDFInfo
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- CN108257994A CN108257994A CN201810034789.0A CN201810034789A CN108257994A CN 108257994 A CN108257994 A CN 108257994A CN 201810034789 A CN201810034789 A CN 201810034789A CN 108257994 A CN108257994 A CN 108257994A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 85
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000013078 crystal Substances 0.000 claims abstract description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 38
- 238000013138 pruning Methods 0.000 claims abstract description 33
- 230000004888 barrier function Effects 0.000 claims abstract description 29
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- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
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- 238000012545 processing Methods 0.000 claims description 21
- 238000005286 illumination Methods 0.000 claims description 10
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- 238000009966 trimming Methods 0.000 claims description 9
- 238000003384 imaging method Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 149
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- 239000000463 material Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
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- 239000011229 interlayer Substances 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
Abstract
This disclosure relates to manufacturing method for semiconductor device.Embodiment provides a kind of method for manufacturing semiconductor device, including：The first metal interconnecting layer in the first interlevel dielectric layer is formed on the front of the first wafer, does not have any metalwork in first edge area；Crystal round fringes pruning modes just are carried out in face of second edge area from the first wafer, second edge area is less than or equal to the width in first edge area in the width of wafer radially；The process for forming the first metal interconnecting layer includes：Photoresist pattern is formed on the first interlevel dielectric layer；Using lip coater in first edge area barrier-coating, to cover photoresist pattern therein；Using photoresist pattern and barrier layer be the first interlevel dielectric layer of mask etching to form groove, barrier layer blocking first edge area in order to avoid form groove wherein；Photoresist pattern and barrier layer are removed, metalwork is formed in a groove, to form the first metal interconnecting layer.
Description
Technical field
This disclosure relates to semiconductor applications, it particularly relates to the manufacturing method of semiconductor device.
Background technology
In current back side illumination image sensor, it usually needs by two wafers (wafer) bonding (bond) together.
And since in back-end process (back end of line, BEOL), requirement of each processing step for crystal round fringes is different, because
This causes the surface flatness at crystal round fringes poor, so as to cause film stripping is easily generated at crystal round fringes after bonding
(peeling) the defects of, these defects can influence subsequent reduction processing etc. and reduce wafer yields.
Therefore there is the demand for new technology.
Invention content
One purpose of the disclosure is to provide a kind of novel manufacturing method for semiconductor device.
According to the disclosure in a first aspect, provide a kind of method for manufacturing semiconductor device, including：First
The first metal interconnecting layer in the first interlevel dielectric layer is formed on the front of wafer, wherein the first metal interconnecting layer is the
There is no any metalwork on the first edge region of one wafer；And from the front of the first wafer, to the second side of the first wafer
Edge region carries out crystal round fringes pruning modes, so as at least remove portion of first interlevel dielectric layer in second edge region
Point, wherein second edge region wafer width radially be less than or equal to first edge region in wafer radially
Width；Wherein, the process for forming the first metal interconnecting layer includes：Photoresist figure is formed on the first interlevel dielectric layer
Case；Using lip coater on the first edge region of the first wafer barrier-coating, to cover in first edge region
Photoresist pattern；Using photoresist pattern and the barrier layer being coated with as mask, the first interlevel dielectric layer is carried out
Etching processing, so as to form groove, wherein the barrier layer stops first edge region in order to avoid being formed in first edge region
Groove；And photoresist pattern and barrier layer are removed, and form metalwork in a groove, it is mutual so as to form the first metal
Even layer.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become more apparent from.
Description of the drawings
The attached drawing of a part for constitution instruction describes embodiment of the disclosure, and is used to solve together with the description
Release the principle of the disclosure.
With reference to attached drawing, according to following detailed description, the disclosure can be more clearly understood, wherein：
Figure 1A and 1B shows the flow of the manufacturing method of the semiconductor device according to one exemplary embodiment of the disclosure
Figure.
Fig. 2 shows the floor map of the first wafer according to the disclosure one exemplary embodiment.
Fig. 3 A-3H are respectively illustrated is manufacturing semiconductor device side according to one exemplary embodiment of the disclosure
Device schematic cross-section at the exemplary each step of method.
Note that in embodiments described below, same reference numeral is used in conjunction between different attached drawings sometimes
Come the part for representing same section or there is identical function, and omit its repeated explanation.In the present specification, using similar mark
Number and letter represent similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. does not indicate that reality sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should be noted that：Unless in addition have
Body illustrates that the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
It is illustrative to the description only actually of at least one exemplary embodiment below, is never used as to the disclosure
And its application or any restrictions that use.That is, semiconductor device and its manufacturing method herein is with illustrative
Mode is shown, to illustrate the different embodiments of the structures and methods in the disclosure.It will be understood by those skilled in the art, however, that
They are merely illustrative the exemplary approach of the present invention that can be used for implementing rather than the mode of limit.In addition, attached drawing need not be by
Ratio is drawn, some features may be amplified the details to show specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
In shown here and discussion all examples, any occurrence should be construed as merely illustrative, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
For foregoing problems, present inventor employs crystal round fringes pruning modes (wafer edge trim),
Bonding before just by the fringe region of uneven surface remove, so as to avoid be bonded after stripping the problems such as.But the application
Inventor also found, when trimming crystal round fringes, can remove the metalwork of edge formation, may expose metalwork, so as to
Cause metallic pollution, lead to white pixel.By further investigation, present inventor proposes a kind of method, i.e., sharp
It avoids forming metalwork at crystal round fringes with lip coater (edge coater), so as to solve the problems, such as crystal round fringes
While be avoided that metallic pollution.As described above, the present invention is especially suitable for need to be bonded the back side illumination image sensor handled.
But those skilled in the art are understood that, the present invention is not limited to back side illumination image sensor, but can be identical used in having
In the manufacturing method of any semiconductor device of demand (that is, avoiding metallic pollution while solving the problems, such as crystal round fringes).
In order to more comprehensively, the present invention is expressly understood, illustrate the technology according to the disclosure below in conjunction with attached drawing.
Figure 1A shows the flow chart of the manufacturing method for semiconductor device 100 according to one exemplary embodiment of the disclosure,
And Figure 1B shows the specific example process of the step 110 in Figure 1A.
As shown in the method flow of Figure 1A, at step 110, formed on the front of the first wafer embedded in the first interlayer electricity
The first metal interconnecting layer in dielectric layer, wherein the first metal interconnecting layer is not any on the first edge region of the first wafer
Metalwork.
" fringe region of wafer " herein refers to an annular region of wafer most peripheral, range usually by
The width (distance away from wafer most outer) of wafer radially determines, such as shown by FIG. 2 below.Fig. 2 shows bases
The floor map of first wafer 201 of one exemplary embodiment of the disclosure.Horizontal arrow R in figure represents the first wafer
Radially.First edge region is innermost dotted line to the region between 201 outer of wafer represented by solid line, radially
Width be W1.Second and third fringe region in figure represent its boundary by the circle of dotted line of outside two respectively, are respectively two
The region of secondary trimming, will be discussed in detail below.
Figure 1B shows step 110, the detailed process for forming the first metal interconnecting layer.
As shown in Figure 1B, first, at step 101, photoresist pattern is formed on the first interlevel dielectric layer.
Then, at step 102, using lip coater on the first edge region of the first wafer barrier-coating,
To cover the photoresist pattern in first edge region.In some embodiments, the material on the barrier layer can be
Photoresist.Preferably, the material identical of the material on the barrier layer and the photoresist pattern, so as to convenient follow-up
It is removed together.In some embodiments, the material on the barrier layer also can be different from the photoresist pattern.
Then, at step 103, using photoresist pattern and the barrier layer being coated with as mask, to the first interlayer electricity
Dielectric layer performs etching processing, so as to form groove, wherein barrier layer blocking first edge region is in order to avoid in first edge
Groove is formed in region.
Then, at step 104, photoresist pattern and barrier layer are removed, and form metalwork in a groove, from
And form the first metal interconnecting layer.
In some embodiments, the first metal interconnecting layer can be copper metal layer, using technology well known in the art come
It is formed.For example, the first metal interconnecting layer can be formed by single Damascus technics well known in the art, at this point, first
The metalwork of metal interconnecting layer is metal connecting line or metal throuth hole.Alternatively, the first metal interconnecting layer can pass through ability
Various dual damascene process well known to domain are formed, and so as to be formed simultaneously metal connecting line and through-hole, therefore the first metal interconnects
The metalwork of layer includes metal connecting line and metal throuth hole.Although being only referred to a lithography and etching processing in Figure 1B, this
Field technology personnel are understood that, in the case of using certain dual damascene process, the photoetching in abovementioned steps 101-103
It may be carried out twice with etching processing, therefore, etching forms any groove in first edge region in order to prevent, each
Lip coater barrier-coating at first edge region is employed to before etching.
In general, in practice, multiple metal interconnecting layers can be formed on the first wafer.In some embodiments, the first gold medal
It can be the top metal interconnecting layer on the front of the first wafer to belong to interconnection layer.For each gold below the first metal interconnecting layer
The forming process for belonging to interconnection layer is unrestricted.
In other embodiments, on the front of the first wafer, on the first metal interconnecting layer and/or under,
One or more metal interconnecting layers in the respective interlevel dielectric layer respectively can be also formed, wherein one or more
Multiple metal interconnecting layers are on the first edge region of the first wafer all without any metalwork.With forming the first metal interconnecting layer
It is similar, during all metal interconnecting layers are formed, all using lip coater photic on first edge region
Barrier-coating on Resist patterns, to cover the photoresist pattern in first edge region, to stop respective interlayer
Dielectric layer forms any groove in first edge region.For example, it is coated on first edge region using lip coater
Barrier layer, so that all metal layers on the first wafer do not form any metalwork in first edge region.
Then, return to Figure 1A, at step 120, from the front of the first wafer, to the second edge region of the first wafer into
Row crystal round fringes pruning modes, so as at least remove part of first interlevel dielectric layer in second edge region, wherein the
The width in wafer radially for being less than or equal to first edge region in the width of wafer radially of two fringe regions.Such as figure
Shown in 2, the boundary in second edge region is outermost circle of dotted line, width W2, less than the width W1 in first edge region.
But Fig. 2 is an example, W2 can also be equal to W1, and second edge region is identical with first edge region at this time.This field
Technical staff is understood that, the part or all of layer being located on the second edge region of wafer can be carried out as needed brilliant
The edge of the circle pruning modes, it might even be possible to which part of the wafer (such as Silicon Wafer) in second edge region is trimmed into part thickness
Degree is whole.
As described above, according to the method for the present invention, the uneven surface of edge is eliminated by crystal round fringes pruning modes
Smooth problem, and avoided using lip coater and form metalwork in edge, it is made during crystal round fringes so as to avoid trimming
Into metallic pollution.
It is bonding in the semiconductor device of manufacture in addition, as shown in the optional step 130 and 140 that dotted line represents in Figure 1A
In the case of device, for example, back side illumination image sensor, this method can also include：The second wafer is provided, and in step 130
The front of the first wafer after trimming and the front of the second wafer are bonded together by place.Then, optionally, in order to further keep away
Exempt from edge and generate defect, at step 140, from the back side of the first wafer, the third fringe region of the first wafer is carried out another
One crystal round fringes pruning modes, wherein third fringe region wafer width radially be more than second edge region in crystalline substance
The upward width of diameter, and less than or equal to the width in wafer radially in first edge region.As shown in Fig. 2, third
The boundary of fringe region is intermediate circle of dotted line, width W3, less than first edge region width W1 and be more than the second side
The width W2 in edge region.But Fig. 2 is an example, W3 can also be equal to W1, at this time third fringe region and first edge
Region is identical.In this way, third fringe region is without departing from first edge region, so as to ensure that second of trimming when will not repair
Metalwork is cut, metallic pollution will not be caused.
In the case where the semiconductor device of manufacture is back side illumination image sensor, in some embodiments, first is brilliant
Wafer of the circle to form all devices (such as pixel unit) needed for imaging sensor, and the second wafer is carrying wafer,
Only play the role of carrying.
And in other embodiments, which can be stack imaging sensor, that is, will scheme
As the part of devices of sensor be transferred to carrying wafer on make, wherein two be bonded wafer may be generally referred to as pixel wafer and
Logic wafer, therefore, the first wafer are one in pixel wafer and logic wafer, and the second wafer for pixel wafer and is patrolled
Collect another in wafer.
It in some embodiments, before bonding will also be in two wafers when using medium with medium bonding method
Top all form dielectric layer, in order to be bonded.
Either manufacture which kind of back side illumination image sensor, usually after bonding will also to be formed with pixel unit that
The back side of wafer (the first wafer or the second wafer) carries out reduction processing, and the reduction processing can carry out above-mentioned another wafer
It is carried out before or after edge pruning processing.Preferably, carried out before above-mentioned another crystal round fringes pruning modes are carried out to
Few a part of reduction processing, to facilitate carry out pruning modes.
In addition, in some embodiments, metal layer can be also formed on the front of the second wafer, therefore before bonding
Corresponding crystal round fringes pruning modes can also be carried out to the second wafer.At this point, it is similar with the first wafer, in order to avoid trimming is made
Into metallic pollution, lip coater may be used to avoid forming metalwork in the edge of the second wafer.Specifically, can be with
The second metal interconnecting layer in the second interlevel dielectric layer is formed on the front of the second wafer, wherein the second metal interconnects
Layer does not have any metalwork on the 4th fringe region of the second wafer, wherein during the second metal interconnecting layer is formed,
The second barrier layer is coated on the photoresist pattern on the 4th fringe region using lip coater, to stop second
Interlevel dielectric layer forms any groove in the 4th fringe region.Then, from the front of the second wafer, to the of the second wafer
Five fringe regions carry out crystal round fringes pruning modes, wherein the 5th fringe region is less than or equal in the width of wafer radially
The width in wafer radially of 4th fringe region.
It note that herein, the numbers such as " first ", " second ", " third ", " the 4th ", " the 5th " are intended merely to tool
The each different components or region for having same names are distinguished and are used, and are not meant to sequence or position relationship etc..It is in addition, right
In each different components with same names and region, such as " the first wafer " and " the second wafer ", " the first metal interconnection
Layer " and " the second metal interconnecting layer " etc. are not meant to that they all have identical structure or component.For example, although attached drawing
In be not shown, but in most cases, the component formed in " the first wafer " and " the second wafer " is all different, wafer
Structure may also be different.
In order to more complete and comprehensive understand the present invention, will be described in detail by taking Fig. 3 A-3H as an example according to the disclosure one below
One specific example of the manufacturing method of a exemplary embodiment.It note that this example is not intended to form to the present invention's
Limitation.For example, the present invention is not limited in the concrete structure of the semiconductor device shown by Fig. 3 A-3H, but there is phase to all
Semiconductor device with demand or design consideration is all suitable for.It can also be applied above in conjunction with the described contents of Figure 1A -1B and Fig. 2
In corresponding feature.
Exemplary each step of the manufacturing method is shown in detail in Fig. 3 A-3H by taking back side illumination image sensor as an example
The device schematic cross-section at place.
At Fig. 3 A, first is formed on the front of the first wafer 201 by known ways such as chemical vapor depositions (CVD)
Then interlevel dielectric layer 202 forms photoresist figure by conventional photoetching treatment on the first interlevel dielectric layer 202
Case 203.
In some embodiments, the first wafer 201 can be semiconductor crystal wafer, by being suitable for any of semiconductor device
Semi-conducting material (Si, SiC, SiGe etc.) is made.In other embodiments, the first wafer 201 or insulation
The various composite wafers such as silicon (SOI), silicon germanium on insulator on body.Those skilled in the art understand the first wafer 201 not by
Any restrictions, but can be selected according to practical application.It could be formed with various semiconductor device structures in first wafer 201
Part, for example, trap, source region, drain region, photodiode etc..Although it is not shown in the figure, forming the first interlevel dielectric layer
Before 202, other layers or component, such as the interconnection of grid, contact, other metals may be already formed on the first wafer 201
Layer etc..
It note that for the sake of simple and convenient, the section of whole wafer be not shown in Fig. 3 A-3H, but merely illustrate
The section of the neighbouring part of crystal round fringes, wherein the trapezoidal shape on figure the right falling of represent that wafer most edge would generally be formed
Angle but it is not intended that the wafer of the present invention is limited to trapezoidal chamfering, but can include various known
Edge configuration.
Then, at Fig. 3 B, using lip coater on the first edge region of the first wafer 201 barrier-coating
204, to cover the photoresist pattern 203 in first edge region.The barrier layer 204 is photo anti-corrosion agent material, excellent
Selection of land, can be with the material identical of photoresist pattern 203.Preferably, the fringe region that lip coater is coated with can be with
Apart from wafer edge about 3.7 ± 0.5mm.
Then, at Fig. 3 C, with photoresist pattern 203 and the barrier layer 204 being coated with for mask, to the first interlayer
Dielectric layer 202 performs etching processing.Therefore groove 205 is ultimately formed.After groove is formed, photoresist pattern is eliminated
203 and barrier layer 204.It, can not in first edge region since barrier layer 204 blocks the etching in first edge region
Form groove 205.It note that the groove 205 for being illustrated that in Fig. 3 C and being formed by dual damascene process, and in some cases
Under, which formed by two step lithography and etching processing, and attached drawing is omitted at another step lithography and etching at this time
Reason, but those skilled in the art are understood that, can all use edge-coating in the processing of two step lithography and etchings as needed
Machine forms barrier layer in first edge region, to prevent to form any groove in first edge region.
Then, at Fig. 3 D, metalwork 206 is formed in groove 205, so as to form the first metal interconnecting layer.It moreover, can
To form silicon nitride layer 207 on the first metal interconnecting layer, to prevent metal from spreading.In some embodiments, the first metal
Interconnection layer can be layers of copper, and known any copper wire technique may be used to be formed.For example, it can be sequentially depositing lining in a groove
Then bed course and copper seed layer fill up groove using electro-coppering, it is extra finally to be chemically-mechanicapolish polished (CMP) processing removal
Copper.
Then, at Fig. 3 E, in a manner of identical with the first aforementioned metal interconnecting layer, the shape on the first metal interconnecting layer
Into other two metal interconnecting layer.Although illustrating only three metal interconnecting layers in figure, but it is clear that the present invention is not limited thereto, and
It is that any number of metal interconnecting layers may be used.
Then, at Fig. 3 F, from the front of the first wafer 201, to the second edge region of the first wafer 201 (by most right
The dotted line on side represents its boundary) crystal round fringes pruning modes are carried out, so as to eliminate the institute of the second edge overlying regions of wafer
There is layer.The width in wafer radially for being less than first edge region in the width W2 of wafer radially in second edge region
W1, as shown in prior figures 2.In some embodiments, as needed, crystal round fringes pruning modes can also remove wafer 201
The part in second edge region.Crystal round fringes pruning modes are unrestricted, but can carry out as needed
Selection or design.Preferably, the width W2 in second edge region is about 1mm to 2mm, more preferably 1.5mm or so.
Therefore, it with reference to shown in Fig. 3 E and 3F, according to the method for the present invention, is avoided using lip coater in crystal round fringes
Place forms metalwork, and metallic pollution is caused during crystal round fringes so as to avoid trimming.In addition, due to there is no shape at crystal round fringes
Into the groove for metalwork and corresponding filling metal, therefore after the formation process of metal layer, at crystal round fringes
Uneven surface degree also has improvement.
Then, at Fig. 3 G, the front of the first wafer 201 after trimming and the front of the second wafer 208 are bonded in one
It rises.As shown in the figure, the first wafer 201 is tipped upside down on 208 top of the second wafer.But the present invention when not being limited to bonding with
And which wafer has to be placed over/lower section after bonding, but the position of upper and lower wafer can be interchanged.In some embodiments
In, the first wafer 201 and the second wafer 208 are bonded together in a manner that medium is bonded with medium, at this point, layer 209 is
Second wafer, 208 outermost bonding dielectric layer.Although it is not shown in the figure, the outermost of the first wafer 201 also should
It is formed with bonding dielectric layer.In addition, though be not shown in figure, but the second wafer 208 can be stack back side illumination image
Logic wafer in sensor, is formed with various semiconductor devices, and is formed with multiple metal connecting line layers thereon.Also may be used
With in a manner of identical with the first aforementioned metal interconnecting layer, multiple metal interconnecting layers are formed on the second wafer 208.Later,
Similarly, before bonding, crystal round fringes pruning modes are also carried out to the fringe region of the second wafer 208.
Due to having carried out crystal round fringes pruning modes before bonding, crystal round fringes after being bonded are reduced or even avoided
The problems such as stripping.
Then, at Fig. 3 H, from the back side of the first wafer 201, to the third fringe region of the first wafer 201 (by figure
Rightmost its boundary shown in phantom) carry out another crystal round fringes pruning modes, wherein third fringe region in wafer radially
Width W3 be more than the width W2 in wafer radially in second edge region, and less than first edge region in wafer diameter
Upward width W1, as shown in prior figures 2.Preferably, the width W3 of third fringe region is about 2mm to 3mm, more preferably
For 2.5mm or so.Although it is not shown in the figure, before above-mentioned another crystal round fringes pruning modes are carried out, it is preferable that can be with
Reduction processing is carried out to the back side of the first wafer 201.In some cases, this time crystal round fringes pruning modes can also be trimmed to
Part or all of layer or even the second wafer 208 on second wafer 208.
It will be understood by those skilled in the art that other than the process and structure as shown in Fig. 3 A-3H, the disclosure further includes shape
Other any process and structures necessary into semiconductor device.
Word "front", "rear", " top ", " bottom " in specification and claim, " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language is interchangeable in appropriate circumstances so that embodiment of the disclosure described herein, for example, can in this institute
Those of description show or other are orientated in other different orientations and operate.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other realization methods in the arbitrary realization method of this exemplary description
Preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technology, invention content or specific embodiment
Given in the theory that is any stated or being implied that goes out limited.
As used in this, word " substantially " mean comprising by design or manufacture the defects of, device or element appearance
Arbitrary small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in practical realization method with perfect or ideal situation
Between difference.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And it thus is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or combination thereof.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering obtain object all modes
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembling ", and/or " order " object etc..
Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As used herein
, unless explicitly stated otherwise, " connection " means an element/node/feature with another element/node/feature in electricity
Above, it is directly connected mechanically, in logic or in other ways (or direct communication).Similarly, unless explicitly stated otherwise,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection indirectly of element or other feature, including profit
With the connection of one or more intermediary elements.
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
Single operation can be combined into, single operation can be distributed in additional operation, and operate can at least portion in time
Divide and overlappingly perform.Moreover, alternative embodiment can include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are changed, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
In addition, embodiment of the present disclosure can also include the example below：
1st, a kind of method for manufacturing semiconductor device, which is characterized in that including：
The first metal interconnecting layer in the first interlevel dielectric layer is formed on the front of the first wafer, wherein first
Metal interconnecting layer does not have any metalwork on the first edge region of the first wafer；And
From the front of the first wafer, crystal round fringes pruning modes are carried out to the second edge region of the first wafer, so as to extremely
Remove part of first interlevel dielectric layer in second edge region less, wherein second edge region in wafer radially
Width is less than or equal to the width in wafer radially in first edge region；
Wherein, the process for forming the first metal interconnecting layer includes：
Photoresist pattern is formed on the first interlevel dielectric layer；
Using lip coater on the first edge region of the first wafer barrier-coating, to cover first edge region
In photoresist pattern；
Using photoresist pattern and the barrier layer being coated with as mask, place is performed etching to the first interlevel dielectric layer
Reason, so as to form groove, wherein the barrier layer stops first edge region in order to avoid forming groove in first edge region；With
And
Photoresist pattern and barrier layer are removed, and forms metalwork in a groove, it is mutual so as to form the first metal
Even layer.
2nd, the method according to 1, which is characterized in that further include：
Second wafer is provided；And
To the second edge region of the first wafer carry out crystal round fringes pruning modes after, by the first wafer front with
The front of second wafer is bonded together.
3rd, the method according to 2, which is characterized in that further include：
After bonding, from the back side of the first wafer, another crystal round fringes are carried out to the third fringe region of the first wafer
Pruning modes, wherein third fringe region wafer width radially be more than second edge region in wafer radially
Width, and less than or equal to the width in wafer radially in first edge region.
4th, the method according to 3, which is characterized in that after the bonding step, further include：From the back side of the first wafer,
Reduction processing is carried out to the first wafer,
Wherein described reduction processing carries out before or after another crystal round fringes pruning modes are carried out.
5th, the method according to 2, which is characterized in that further included before bonding steps：
The second metal interconnecting layer in the second interlevel dielectric layer is formed on the front of the second wafer, wherein second
Metal interconnecting layer does not have any metalwork on the 4th fringe region of the second wafer, wherein forming the second metal interconnecting layer
In the process, the second barrier layer is coated on the photoresist pattern on the 4th fringe region using lip coater, with
Stop that the second interlevel dielectric layer forms any groove in the 4th fringe region；
From the front of the second wafer, crystal round fringes pruning modes are carried out to the 5th fringe region of the second wafer, wherein the
The width in wafer radially for being less than or equal to the 4th fringe region in the width of wafer radially of five fringe regions.
6th, the method according to 2, which is characterized in that the first crystalline substance is additionally included in before crystal round fringes pruning modes are carried out
Bonding dielectric layer is formed on round top.
7th, the method according to 2, which is characterized in that the semiconductor device is back side illumination image sensor, and the
Two wafers are carrying wafer.
8th, the method according to 2, which is characterized in that the semiconductor device is stack imaging sensor, and first is brilliant
Circle is one in pixel wafer and logic wafer, and the second wafer is another in pixel wafer and logic wafer.
9th, the method according to 1, which is characterized in that first metal interconnecting layer for the first wafer front on most
Top-level metallic interconnection layer.
10th, the method according to 1, which is characterized in that before crystal round fringes pruning modes are carried out, further include：
On the front of the first wafer, on first metal interconnecting layer and/or under, formed it is one or more
Metal interconnecting layer in respective interlevel dielectric layer respectively, wherein one or more metal interconnecting layer is first
All without any metalwork on the first edge region of wafer,
Wherein, during one or more metal interconnecting layer is formed, all using lip coater positioned at
Barrier-coating on photoresist pattern on first edge region, to cover the photoresist figure in first edge region
Case, to stop that respective interlevel dielectric layer forms any groove in first edge region.
11st, the method according to 1, which is characterized in that first metal interconnecting layer is by single Damascus technics
It is formed, and the metalwork of first metal interconnecting layer is metal connecting line or metal throuth hole.
12nd, the method according to 1, which is characterized in that first metal interconnecting layer is to pass through dual damascene process
It is formed, and the metalwork of first metal interconnecting layer includes metal connecting line and metal throuth hole.
13rd, the method according to 1, which is characterized in that the material on the barrier layer and the photoresist pattern
Material identical.
14th, the method according to 1, which is characterized in that the barrier layer is by different from the photoresist pattern
Photo anti-corrosion agent material is formed.
Although some specific embodiments of the disclosure are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to illustrating rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out to embodiment without departing from the scope and spirit of the disclosure.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
- A kind of 1. method for manufacturing semiconductor device, which is characterized in that including：The first metal interconnecting layer in the first interlevel dielectric layer is formed on the front of the first wafer, wherein the first metal Interconnection layer does not have any metalwork on the first edge region of the first wafer；AndFrom the front of the first wafer, crystal round fringes pruning modes are carried out to the second edge region of the first wafer, so as at least go Except the width in wafer radially of part of first interlevel dielectric layer in second edge region, wherein second edge region Less than or equal to the width in wafer radially in first edge region；Wherein, the process for forming the first metal interconnecting layer includes：Photoresist pattern is formed on the first interlevel dielectric layer；Using lip coater on the first edge region of the first wafer barrier-coating, to cover in first edge region Photoresist pattern；Using photoresist pattern and the barrier layer being coated with as mask, processing is performed etching to the first interlevel dielectric layer, from And groove is formed, wherein the barrier layer stops first edge region in order to avoid forming groove in first edge region；AndPhotoresist pattern and barrier layer are removed, and forms metalwork in a groove, so as to form the first metal interconnecting layer.
- 2. it according to the method described in claim 1, it is characterized in that, further includes：Second wafer is provided；AndAfter crystal round fringes pruning modes are carried out to the second edge region of the first wafer, by the front and second of the first wafer The front of wafer is bonded together.
- 3. it according to the method described in claim 2, it is characterized in that, further includes：After bonding, from the back side of the first wafer, another crystal round fringes trimming is carried out to the third fringe region of the first wafer The width in wafer radially for being more than second edge region in the width of wafer radially of processing, wherein third fringe region Degree, and less than or equal to the width in wafer radially in first edge region.
- 4. it according to the method described in claim 3, it is characterized in that, after the bonding step, further includes：From the back of the body of the first wafer Face carries out reduction processing to the first wafer,Wherein described reduction processing carries out before or after another crystal round fringes pruning modes are carried out.
- 5. it according to the method described in claim 2, it is characterized in that, is further included before bonding steps：The second metal interconnecting layer in the second interlevel dielectric layer is formed on the front of the second wafer, wherein the second metal Interconnection layer does not have any metalwork on the 4th fringe region of the second wafer, wherein in the process for forming the second metal interconnecting layer In, the second barrier layer is coated on the photoresist pattern on the 4th fringe region using lip coater, with blocking Second interlevel dielectric layer forms any groove in the 4th fringe region；From the front of the second wafer, crystal round fringes pruning modes are carried out to the 5th fringe region of the second wafer, wherein the 5th side The width in wafer radially for being less than or equal to the 4th fringe region in the width of wafer radially in edge region.
- 6. according to the method described in claim 2, it is characterized in that, is additionally included in before crystal round fringes pruning modes are carried out Bonding dielectric layer is formed on the top of one wafer.
- 7. according to the method described in claim 2, it is characterized in that, the semiconductor device be back side illumination image sensor, and And second wafer for carrying wafer.
- 8. according to the method described in claim 2, it is characterized in that, the semiconductor device is stack imaging sensor, the One wafer is one in pixel wafer and logic wafer, and the second wafer is another in pixel wafer and logic wafer It is a.
- 9. according to the method described in claim 1, it is characterized in that, first metal interconnecting layer is on the front of the first wafer Top metal interconnecting layer.
- 10. according to the method described in claim 1, it is characterized in that, before crystal round fringes pruning modes are carried out, further include：On the front of the first wafer, on first metal interconnecting layer and/or under, form one or more difference Metal interconnecting layer in respective interlevel dielectric layer, wherein one or more metal interconnecting layer is in the first wafer First edge region on all without any metalwork,Wherein, during one or more metal interconnecting layer is formed, all using lip coater positioned at first Barrier-coating on photoresist pattern on fringe region, to cover the photoresist pattern in first edge region, To stop that respective interlevel dielectric layer forms any groove in first edge region.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037036A (en) * | 2018-08-02 | 2018-12-18 | 德淮半导体有限公司 | Crystal round fringes pruning method |
| CN109830445A (en) * | 2019-01-02 | 2019-05-31 | 长江存储科技有限责任公司 | A kind of chip preparation method and chip structure |
| WO2021082337A1 (en) * | 2019-10-30 | 2021-05-06 | 武汉新芯集成电路制造有限公司 | Method for improving tip discharge defect and manufacturing method for semiconductor device |
| CN115579374A (en) * | 2022-12-12 | 2023-01-06 | 合肥新晶集成电路有限公司 | Method for manufacturing back cover type image sensor and back cover type image sensor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127311A (en) * | 2006-08-16 | 2008-02-20 | 台湾积体电路制造股份有限公司 | Methods of manufacturing semiconductor device |
| US20100197071A1 (en) * | 2009-01-30 | 2010-08-05 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device |
| CN101853864A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Method of wafer bonding |
| US20160276310A1 (en) * | 2015-03-18 | 2016-09-22 | Globalfoundries Singapore Pte. Ltd. | Edge structure for backgrinding asymmetrical bonded wafer |
-
2018
- 2018-01-15 CN CN201810034789.0A patent/CN108257994A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127311A (en) * | 2006-08-16 | 2008-02-20 | 台湾积体电路制造股份有限公司 | Methods of manufacturing semiconductor device |
| US20100197071A1 (en) * | 2009-01-30 | 2010-08-05 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device |
| CN101853864A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Method of wafer bonding |
| US20160276310A1 (en) * | 2015-03-18 | 2016-09-22 | Globalfoundries Singapore Pte. Ltd. | Edge structure for backgrinding asymmetrical bonded wafer |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037036A (en) * | 2018-08-02 | 2018-12-18 | 德淮半导体有限公司 | Crystal round fringes pruning method |
| CN109830445A (en) * | 2019-01-02 | 2019-05-31 | 长江存储科技有限责任公司 | A kind of chip preparation method and chip structure |
| CN109830445B (en) * | 2019-01-02 | 2021-04-13 | 长江存储科技有限责任公司 | Chip preparation method and chip structure |
| WO2021082337A1 (en) * | 2019-10-30 | 2021-05-06 | 武汉新芯集成电路制造有限公司 | Method for improving tip discharge defect and manufacturing method for semiconductor device |
| CN115579374A (en) * | 2022-12-12 | 2023-01-06 | 合肥新晶集成电路有限公司 | Method for manufacturing back cover type image sensor and back cover type image sensor |
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