CN108256356A - A kind of method for resisting chip register direct fault location - Google Patents
A kind of method for resisting chip register direct fault location Download PDFInfo
- Publication number
- CN108256356A CN108256356A CN201611241559.9A CN201611241559A CN108256356A CN 108256356 A CN108256356 A CN 108256356A CN 201611241559 A CN201611241559 A CN 201611241559A CN 108256356 A CN108256356 A CN 108256356A
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- CN
- China
- Prior art keywords
- register
- chip
- fault location
- direct fault
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The present invention proposes a kind of method for resisting chip register direct fault location.It applies in the various safety chips for having safety requirements; such as electronic ID card, fiscard, social security card, mass transit card chip; the present invention can coordinate other chip reset mechanism that chip is protected illegally not influenced or invaded, so as to improve the security protection strength to chip interior resource.
Description
Technical field
Present invention is mainly applied to field of information security technology, are a kind of anti-attacking technologies suitable for safety chip.
Background technology
Chip during the work time, has the risk potentially attacked.Common attack method, which has, implements chip
Illumination, electromagnetism or burr injection, change environment temperature, voltage, working frequency of chip etc., make to deposit in chip by these attacks
Device and its reseting logic generate malfunction, and the data and security setting for leading to chip memory storage are tampered, such as safety sensor
Enabled switch, the switch of Prevention-Security mechanism etc. is distorted by opening to be in off state so that the internal security of chip is set
Decrease or failure are put, so as to which chip be made to be in a kind of unsafe working condition, attacker is allow further to be attacked.
Therefore the exception for finding registers state is detected in time, so as to reach defence purpose.
Invention content
The present invention discloses a kind of method for resisting chip register direct fault location, and one group of register is placed in portion in the chip,
And corresponding initializing circuit and CL Compare Logic circuit are set, and using the warning output of CL Compare Logic circuit as the reset of chip
Source.In the chip initiation stage, initializing circuit initializes one group of register.Chip is by different after the completion of initialization
Normal condition interference, when leading to register by exceptional reset, detects alarming value by CL Compare Logic circuit, thus therefore chip
Reset.When being not affected by exceptional condition interference, the data of one group of register are the presence of complementary data form, as " 01 " or
" 10 " represent logical value " 0 " and " 1 " respectively, and chip is normally carried out work.
As shown in Figure 1, the present invention uses a kind of circuit of the register group structure with exceptional reset alarm mechanism, by posting
Storage A, register B, initialization control circuit C and multilevel iudge logic circuit D compositions；Wherein, register A and register B is used
To preserve numerical value in the form of complementary logic, initialization circuit C be used for the chip initiation stage to register A and
Register B is initialized, and by its reset values " 00 " or " 11 ", i.e. alarming value, is initialized as " 01 " or " 10 ", that is, is worked normally
Value, and the output of decision logic circuit D is compared in shielding before initialization is completed, and is avoided in initial phase false alarm；Compare and sentence
Disconnected logic circuit D is in real time detected the value of register A and register B, when its value is " 00 " or " 11 ", exports alarm signal
Number, when being not in initial phase, which will cause chip reset.
The present invention needs that chip reset mechanism is coordinated to use, and is protect effective to one kind of external operating condition abnormal aggression
Handguard section when external operating condition is normal, does not interfere with the course of normal operation of chip.
The present invention using output signal as chip reset source for be illustrated, but the present invention is not limited to will export
Reset source of the signal as chip can be interrupt source or other abnormality processings control signal.The present invention can pass through repeatedly multiple
System, for protecting multiple (group) registers from the threat of fault injection attacks.
Description of the drawings
Fig. 1 chip register direct fault location circuits using the present invention of resisting realize schematic diagram
Specific embodiment
In the following, for using one to resist chip register direct fault location circuit, to illustrate the specific implementation of the present invention
Mode.
The hardware realization of the resistance chip register direct fault location circuit of the present invention is as shown in Figure 1.
The present invention (register A and is posted using register data input and its inverted value are connected respectively to one group of register
Storage B) input terminal, i.e., the data terminal of two registers, by the output terminal of CL Compare Logic circuit D, i.e. register group data ratio
Relatively result output connection chip system resets.In the chip initiation stage, by initializing circuit C by register group (register A and
Register B) value be initialized as " 01 " or " 10 " by reset values " 00 " or " 11 ", while initialization complete before, shielding is compared
The warning output of logic circuit D.After the completion of chip initiation, in course of normal operation, when external operating condition causes to post extremely
When storage group generates exceptional reset, the value of register group will be reset " 00 " or " 11 ", be detected by comparing logic circuit D
The numerical value of register group is alarm condition, and output alarm signal is caused chip reset by circuit D.When external operating condition is normal
When, the value of register group (register A and register B) represents logical value " 0 " when being " 01 ", when " 10 " represents logical value " 1 ", from
And work normally chip.
The present invention includes but not limited to this specific embodiment.The present invention is illustrated so that one group of register is realized as an example
, but the present invention is not limited solely to the situation of one group of register, can be multiple, multigroup register.The value of register group is not limited to
Represent logical value " 0 " when " 01 ", when " 10 " represents logical value " 1 ", may be reversed use or takes other coding modes.It is defeated
Go out signal and be also not necessarily limited to reset source as chip, can be interrupt source or other abnormality processings control signal.
Claims (7)
- A kind of 1. method for resisting chip register direct fault location, it is characterised in that one group of register and just is placed in portion in the chip Beginningization unit and comparing unit, using the outputs level signals of comparing unit as the reset source of chip, when chip is by abnormal item When part interferes, register is caused to reset, CL Compare Logic circuit will will detect that this abnormality, cause the reset of chip.
- 2. a kind of method for resisting chip register direct fault location as described in claim 1, it is characterised in that using initialization Mode one group of register is initialized as normal operating conditions by alarm condition during chip initiation, initialization tie Alarm condition is persistently detected after beam, carries out Realtime Alerts.
- 3. a kind of method for resisting chip register direct fault location as described in claim 1, it is characterised in that when due to resetting During by anomalous effects, register can enter alarm condition, so as to which situation about being attacked reset can be effectively detected And it alarms.
- 4. a kind of method for resisting chip register direct fault location as described in claim 1, it is characterised in that by one group of deposit The value of device is defined as normal operating conditions and alarm condition, and normal operating conditions includes two kinds of " 01 " and " 10 "；Alarm condition packet Include two kinds of " 00 " or " 11 ", wherein " 00 " or " 11 " form alarm condition not only can by causing to the interference of register, by In structure proposed by the invention, can also be caused by reset anomalous effects.
- 5. a kind of method for resisting chip register direct fault location as described in claim 1, it is characterised in that without in synthesis And the structure and logic of the present invention are fully relied on for being carried out additional special designing by protection register during placement-and-routing Principle can protect one group of register.
- A kind of 6. method for resisting chip register direct fault location, it is characterised in that the circuit structure can pass through multiple copies, For protecting multiple (group) registers from the threat of fault injection attacks.
- A kind of 7. method for resisting chip register direct fault location, it is characterised in that by register A, register B, initialization control Circuit C and multilevel iudge logic circuit D compositions；Wherein, register A and register B is used for preserving number in the form of complementary logic Value, initialization circuit C are used for initializing register A and register B in the chip initiation stage, be answered by it Place value " 00 " or " 11 ", i.e. alarming value are initialized as " 01 " or " 10 ", i.e. normal operating value, and are shielded before initialization is completed The output of multilevel iudge logic circuit D, avoids in initial phase false alarm；Multilevel iudge logic circuit D is in real time to register A It is detected with the value of register B, when its value is " 00 " or " 11 ", output alarm signal, when being not in initial phase, The alarm signal will cause chip reset.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611241559.9A CN108256356B (en) | 2016-12-29 | 2016-12-29 | Method for resisting fault injection of chip register |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611241559.9A CN108256356B (en) | 2016-12-29 | 2016-12-29 | Method for resisting fault injection of chip register |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108256356A true CN108256356A (en) | 2018-07-06 |
| CN108256356B CN108256356B (en) | 2021-05-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611241559.9A Active CN108256356B (en) | 2016-12-29 | 2016-12-29 | Method for resisting fault injection of chip register |
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| Country | Link |
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| CN (1) | CN108256356B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866160A (en) * | 2005-05-19 | 2006-11-22 | 美国博通公司 | Digital power-on reset circuit and power-on reset method |
| CN103714018A (en) * | 2013-12-11 | 2014-04-09 | 中国电子科技集团公司第三十研究所 | Security access control method for chip storage circuit |
| US20140359383A1 (en) * | 2013-05-28 | 2014-12-04 | International Business Machines Corporation | Address windowing for at-speed bitmapping with memory built-in self-test |
-
2016
- 2016-12-29 CN CN201611241559.9A patent/CN108256356B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866160A (en) * | 2005-05-19 | 2006-11-22 | 美国博通公司 | Digital power-on reset circuit and power-on reset method |
| US20140359383A1 (en) * | 2013-05-28 | 2014-12-04 | International Business Machines Corporation | Address windowing for at-speed bitmapping with memory built-in self-test |
| CN103714018A (en) * | 2013-12-11 | 2014-04-09 | 中国电子科技集团公司第三十研究所 | Security access control method for chip storage circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108256356B (en) | 2021-05-25 |
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