CN108255777A - For the embedded floating type DSP stone structures of FPGA - Google Patents
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Abstract
Present disclose provides a kind of embedded floating type DSP stone structures for FPGA, including：First input unit is made of the special preceding plus device of input register group and floating number multiplication, by corresponding configuration bit, input deposit is carried out to input data or bypass selects；Multiplier unit is connected to first input unit, receives the input data that prime passes through register；Second input unit including the second input register group, is connected to the output terminal of multiplier unit；Multiple selector group unit, input terminal are connected to the output terminal of the output terminal of second input unit, the first input unit；ALU units including adder and logical unit, provide plus-minus by floating number and fixed-point number and multiplying use, logical operation is provided for fixed-point number；Output unit.Since the processing to data and operation are all completed in the inside configuration, operation efficiency significantly will realize floating point arithmetic with the mode of soft core.
Description
Technical field
This disclosure relates to FPGA fields more particularly to a kind of embedded floating type DSP stone structures for FPGA.
Background technology
The advantages such as FPGA may be programmed by itself, degree of parallelism is high, flexibility is good obtain in fields such as communication, space flight, military affairs
It is widely applied.Digital Signal Processing is exactly an important application field, at present base in the FPGA products of industrial quarters mainstream
This is all integrated with programmable digital signal processing module.For example, contain 3600 DSP48E1 in the Virtex-7 of Xilinx companies
Unit supports multiply-add/multiply and subtract/operations such as to multiply accumulating, and the Stratix-V of altera corp contains 532 DSP units, single
DSP IP kernels can be split according to the demand of application realizes most functions with minimum resource, support it is multiply-add, multiply subtract, multiply it is tired
The operations such as add, but do not support addition, accumulating operation.FPGA generally requires to call numerous during Digital Signal Processing is carried out
DSP module to carry out signal various mathematical operations, but being continuously increased with data volume, required signal to be processed
The floating number for becoming numberical range bigger from original fixed-point number expression represents, such as radar signal, navigation etc. are all using floating
The representation of points.
In real life, floating number has a wide range of applications space, for example, radar signal is exactly the table using floating number
Show method, the radar signal being collected into can by be sent in the form of floating number in computer carry out signal processing, exactly by
In such application demand, the FPGA products of Altera to Xilinx companies both provide the soft cores of related IP of floating point arithmetic.
By taking Xilinx companies as an example, the said firm develops the soft cores of relevant floating point arithmetic module I P, passes through the IP in Vivado
Catalog functions carry out IP calling, can support to include a variety of floating point arithmetics, in addition to the basic operation of floating number, also carry
For operations such as index, logarithm, evolutions, the concrete function provided is as shown in table 1 below.Algorithm is carried out using hardware description language to build
Mould, the method for generating stone circuit structure is feasible, but excessively cumbersome, and the development cycle is long, so FPGA manufacturers are mostly all
It is to employ a kind of traditional floating point arithmetic realization method, i.e., by the way of the soft cores of IP, passes through the side of logical resource or DSP
Formula realizes relevant operation.
The operation that 1 Xilinx floating-points IP of table is supported
DSP module in current FPGA products is all the DSP architecture using fixed-point type, in the eda software of Altera
The logic control part mapping in floating point arithmetic is arrived FPGA's in the eda software Vivado of Quartus II and Xilinx
In the logical resources such as LUT tables, the operations such as the multiplication for carrying out floating point arithmetic, addition are mapped to fixed-point multiplication device, the addition of DSP
In device.Although this method is convenient, the resource occupied is excessive, and the operation efficiency of the soft cores of IP is not high.Due to floating number
The application demand of high-speed computation, Intel Company are embedded in floating type stone DSP module to improve FPGA in its newest product
To the support that floating number calculates, but there is not chip offer so far.
In view of the above-mentioned problems, the present disclosure proposes a kind of floating type DSP architecture of stone, to improve the operation of floating number effect
Rate, while reduce the use of logical resource in FPGA.
Disclosure
(1) technical problems to be solved
Present disclose provides a kind of embedded floating type DSP stone structures for FPGA, more than at least partly solving
The technical issues of proposed.
(2) technical solution
According to one aspect of the disclosure, a kind of embedded floating type DSP stone structures for FPGA are provided, are wrapped
It includes：First input unit, by input register group and floating number multiplication it is special before plus device form, by corresponding configuration bit,
Input deposit or bypass selection are carried out to input data；Multiplier unit is connected to first input unit, receives prime
By the input data of register；Second input unit including the second input register group, is connected to the output of multiplier unit
End；Multiple selector group unit, is made of multiple selectors, and input terminal is connected to the output terminal of second input unit,
The output terminal of one input unit；ALU units, including adder and logical unit, the adder is floating number and fixed point
Number provides plus-minus and multiplying is used, while also provide logical operation for fixed-point number；And output unit, for exporting
Operation result.
In the disclosure some embodiments, wherein, ALU units further include adjustment circuit, rounding-off unit, coding module, spy
Assize module, preliminary shift module, shift-corrected module, wherein the adjustment circuit includes leading zero detection circuit and a mistake
Poor adjustment circuit.
In the disclosure some embodiments, when carrying out floating number multiplying, the preceding plus device unit of the first input unit
Exponential part for the floating number to input is summed, and multiplier unit is used to carry out multiplication operation, ALU to mantissa part
Unit is used to complete the adjustment of floating number, normalization and rounding-off operation.
In the disclosure some embodiments, when carrying out floating number signed magnitude arithmetic(al), in ALU units, two of input
Floating number can be respectively fed to two paths, and signal carries out plus-minus operation using adder to two floating numbers all the way, obtained knot
Fruit detects in mantissa part result 0 number by leading zero probe unit, carries out a preliminary displacement and the adjustment of index,
Another way signal is sent into after being encoded in detection tree construction, is finally generated signal, is indicated whether to need the signal to tentatively shifting
It is further adjusted, finally obtains the result of floating number signed magnitude arithmetic(al).
In the disclosure some embodiments, the output unit includes：Output register group, output register group are prime
Adder unit in ALU units provides deposit unit, and the result after calculating is registered in adder, and result is used to tire out
In the operation added；Pattern detector, the pattern detector are configurable module, and user passes through the mould in configuration mode detector
Formula is to detect whether output result is consistent with pattern, so as to make the specific data of DSP output user's needs.
In the disclosure some embodiments, multiplier unit carries out multiplication behaviour by way of booth codings to operand
Make, and the number of compression section product, further partial product is compressed in combination with the tree-like adder of multiplier unit, and
The result of gained is further corrected with reference to the leading zero detection circuit in ALU units.
In the disclosure some embodiments, the multiplier unit introduces the structure of assembly line during design.
In the disclosure some embodiments, the second input unit be also connected to including：Multiple selector group selection signal
OPMODE, carry signal CARRYIN, the data input pin of port C and ALU operation modes configuration signal ALUMODE.
In the disclosure some embodiments, the input terminal of multiple selector group unit is also connected to the grade for including DSP results
Join signal PCIN, for the CARRYINSEL signals in option value input source and output feedback signal PCOUT, and by phase
The gating signal OPMODE answered selects the selector in multiple selector group unit, switches different function and/or change
The data source being input in next stage adder.
In the disclosure some embodiments, the first input unit and/or output unit reserve used during DSP cascades
Port.
(3) advantageous effect
It can be seen from the above technical proposal that the disclosure at least has for the embedded floating type DSP stone structures of FPGA
There is one of following advantageous effect：
(1) it since the processing to data and operation are all completed in the inside configuration, is provided compared to using the logic in FPGA
Operation is more efficient for the circuit structures such as source mapping floating number adjustment, and it is serial with soft that operation efficiency will be substantially better than xilinx 7
The mode of core realizes floating point arithmetic；
(2) floating point arithmetic is carried out by using dedicated floating type stone DSP architecture, it is possible to reduce logic provides in FPGA
The consumption in source.
(3) compared to the soft core realization method of floating point arithmetic, under the premise of identical floating point number operations, floating type
DSP stones structure has lower power consumption.
Description of the drawings
Fig. 1 is schematic diagram of the embodiment of the present disclosure for the embedded floating type DSP stone structures of FPGA.
Fig. 2 is the original that the embodiment of the present disclosure realizes floating number multiplying for the embedded floating type DSP stones of FPGA
Reason figure.
Fig. 3 is that the DSP architecture of embodiment of the present disclosure floating number multiplication realizes structure chart.
Fig. 4 is the padding operation schematic diagram of embodiment of the present disclosure mantissa multiplication.
Fig. 5 is that the embodiment of the present disclosure realizes floating number signed magnitude arithmetic(al) for the embedded floating type DSP stones of FPGA
Schematic diagram.
The DSP architecture of Fig. 6 embodiment of the present disclosure floating-point adders realizes structure chart.
Specific embodiment
Present disclose provides a kind of embedded floating type DSP stone structures for FPGA.To make purpose, the skill of the disclosure
Art scheme and advantage are more clearly understood, below in conjunction with specific embodiment, and with reference to attached drawing, to the disclosure further specifically
It is bright.
Disclosure some embodiments will be done with reference to appended attached drawing in rear and more comprehensively describe to property, some of but not complete
The embodiment in portion will be shown.In fact, the various embodiments of the disclosure can be realized in many different forms, and should not be construed
To be limited to this several illustrated embodiment；Relatively, these embodiments are provided so that the disclosure meets applicable legal requirement.
In first exemplary embodiment of the disclosure, it is hard to provide a kind of embedded floating type DSP for FPGA
Nuclear structure.Fig. 1 is structure diagram of the first embodiment of the present disclosure for the embedded floating type DSP stone structures of FPGA.Such as
Shown in Fig. 1, the disclosure includes for the embedded floating type DSP stone structures of FPGA：First input unit, multiplier unit,
Second input unit, multiple selector group unit, ALU units, output unit.
The present embodiment is carried out for each component part of the embedded floating type DSP stone structures of FPGA individually below
Detailed description.
First input unit is mainly made of the special preceding plus device of input register group and floating number multiplication, by corresponding
Configuration bit, carries out input data A, B input deposit or bypass selects；Before when floating number multiplication is performed plus device can be right
The index of floating number is added, and obtained result is sent to rear stage and carries out further operating.Multi-stage pipeline is introduced in the unit, it is right
Critical path is split, and is shortened critical path, be ensure that the working frequency of DSP.Meanwhile it is used when reserving DSP cascades
Port, can complete more to operate by cascade mode, improve the flexibility of DSP.
Multiplier unit is connected to first input unit, for receive prime by register input data A and
B.Multiplier unit is the multiplier unit (A*B) of one two input in the present embodiment, to operation by way of booth codings
Number carries out multiplication operation, and the number of compression section product, and further partial product is compressed in combination with tree-like adder,
Area overhead is reduced through the above way, improves calculating speed, which is simultaneously floating number and the multiplication provider of fixed-point number
Part is supported, and the leading zero detection circuit (LZD) combined in ALU units further corrects the result of gained.It is preferred that
Ground, the multiplier unit can introduce the structure of assembly line during design, improve working frequency.
Second input unit includes the second input register group, is connected to the output terminal of multiplier unit, further includes multichannel
Selector group selection signal OPMODE, carry signal CARRYIN, the data input pin of port C and ALU operation modes match confidence
Number ALUMODE, which is used to carry out input deposit to input, with time division multiplier to the key between ALU units
Working frequency is improved in path.
The input terminal of multiple selector group unit is connected to the output terminal of second input unit, the first input unit
Output terminal, while the cascade signal PCIN including DSP results input the CARRYINSEL signals in source for option value, with
And the output feedback signal PCOUT of this DSP module, multiple selector group unit is made of multiple selectors, by gating accordingly
Signal OPMODE selects selector, so as to complete the switching between different function, can also change and be input to next stage and add
Data source in musical instruments used in a Buddhist or Taoist mass.
The formant of ALU units is to provide addition used in plus-minus and multiplying for floating number and fixed-point number
Device, while also logical operation is provided for fixed-point number.Wherein, the ALU units are in order to the operation of supporting floating number, to its structure
Improved, other than operating structure, be also added into leading zero detection circuit (LZD), an error transfer factor circuit and
Unit is rounded, it is so as to make it while the operation for completing floating number, output result normalization is standard compliant so as to generate
Floating number exports.
Output unit includes output register group and pattern detector, and the output unit is introduced by output register group
Pipeline organization, so as to improve the working frequency of DSP, while register provides deposit unit for prime adder unit, meter
Result after calculation can be registered in adder, in this way can be by result in cumulative operation.Meanwhile output unit is pre-
Cascade port has been stayed, thus can complete more operations by cascading DSP.Pattern detector is the mould that user can configure
Block, user exports whether result is consistent with pattern by the pattern in configuration mode detector to detect, so as to export DSP
The specific data that user needs.
During realizing floating number multiplication, operation is as shown in Figure 2.In order to realize above-mentioned calculating process, this structure exists
Add device unit before being added in first input unit, sum to the exponential part of the floating number A and B of input, multiplier unit
Multiplication operation is carried out to mantissa part, adjustment, normalization and the rounding-off operation of floating number then transfer to ALU units to complete.Algorithm
DSP architecture realize block diagram as shown in figure 3, wherein, preceding plus device in the first input unit, adder behind multiplier and
Adjustment circuit is all in ALU units.Preceding plus device can be in the 32bit data of input data as a dedicated index adder
Exponential part, i.e., add operation before the exponential part of 24 to 31 carries out, index of the obtained result as floating number multiplication
Part.
According to the regulation of IEEE-754 agreements, the mantissa part of any denormal floating-point number is 23bit, before this 23bit
There are one the hidden bits that numerical value is 1 not to show in floating number, but this position when floating point arithmetic is participated in
Hidden bit needs, which are mended out, to be participated in operation, in order to balance the multiplication operation of fixed-point number 25*25bit, it is also necessary in hidden bit
It is preceding to mend 0, as the sign bit of mantissa, it is made to meet bit wide demand, as shown in Figure 4.The operation for carrying out mending 0 to mantissa is by floating-point
Number all regards that positive number carries out operation as, but this is not the real sign bit of result, therefore real symbol in order to obtain
Position, it is necessary to the symbol of two floating-point multipliers of input is taken out, individually carries out logic XOR operation, it is real so as to obtain result
Sign bit.Then it is that can obtain the multiplication result of mantissa part mantissa bit to be carried out multiplying.
After the value of exponential part and mantissa part is obtained, need to be adjusted exponential part and mantissa part, it is right
Relevant floating number carries out normalization processing.It needs to use leading zero detection circuit during normalization processing is carried out
(LZD) in mantissa part result 0 number is detected, so as to carry out shifting function to mantissa part.Obtaining leading 0
After numerical value, corresponding shifting function is carried out to mantissa result, while the value of index is cut to leading 0 a numerical value, then will most
The mantissa part of whole sign bit, 8bit exponential parts and 23bit combines as the result of final floating number multiplication.
The embodiment of the present disclosure realizes the principle of floating number signed magnitude arithmetic(al) such as the embedded floating type DSP stones of FPGA
Shown in Fig. 5, therefore the disclosure employs structure shown in fig. 6 and operation is carried out to floating number so as to obtain the knot of floating number addition and subtraction
Fruit.Two floating numbers are input in ALU units, can be respectively fed to two paths, and signal utilizes adder to two floating-points all the way
Number carries out plus-minus operation, and obtained result carries out a preliminary displacement and the adjustment of index, another way signal by LZD units
It is sent into after being encoded in detection tree construction, finally generates signal, indicate whether to need to carry out the signal tentatively shifted further
Adjustment, finally obtain the result of floating number signed magnitude arithmetic(al).Above-mentioned operation is all completed in ALU units.
When carrying out practical operation, the addition with symbolic number is not needed to by encoding and detecting tree unit, because this
Result will not generate error under kind calculation condition, but the subtraction of the addition of contrary sign or jack per line is the adjustment for needing to carry out result
's.There are 1bit errors during contrary sign addition or jack per line subtraction is carried out.It is compiled by two data to input
After code, tree-like detection is carried out, so as to finally determine the need for carrying out the adjustment of an error.
The floating type stone DSP architecture proposed in the disclosure has the function of floating-point adder, multiplication and adds up, and adopts
With standard SMIC 28nm CMOS technologies library, voltage 0.945V, 125 degrees Celsius of temperature completes floating type using DC tools
The circuit of stone DSP is realized, is 11091 μm by the entire area that placement-and-routing obtains2。
Compare 7 Series FPGAs of xilinx of same process node, model xc7v585tffg1157-3, identical
(using 6 stage pipeline structures in the disclosure) in the case of latency, floating number addition and subtraction unit is called, selects speed
Preferential structure optimization, the unit are mapped on 1 DSP48E1 and logical resource, set performance and resource respectively as excellent
The structure for changing target and the disclosure is compared, while have invoked floating number multiplication unit, and comparison result is as shown in the table, is floated
Addition, the comparison situation of multiplication of counting are as shown in the table：
2 synthesis result contrast table of table
It can be seen that during floating-point adder is performed by comparing, the floating type stone DSP that the disclosure is proposed
The floating-point adder operational performance of structure is 1.8 times of the soft cores of IP under the conditions of performance priority；Floating number performance of multiplication operation is property
1.43 times of the soft cores of IP under energy priority condition.This is because the participation of on piece logical resource is needed during the soft verifications of IP are existing,
Data pass out on piece logical resource again again by the result after DSP operation and DSP operation are sent into after the processing of on piece logical resource
Managing the two processes needs to spend longer time, and processing of the floating type stone DSP architecture that the disclosure is proposed to data
It all completes in the inside configuration with operation, is secondly not so good as using circuit structures such as the logical resource mapping floating number adjustment in FPGA
Dedicated circuit design is efficient.The floating point arithmetic efficiency of floating type stone DSP architecture that the disclosure is proposed will be substantially better than
7 series of xilinx realizes floating point arithmetic with the mode of soft core.
Certainly, above-mentioned hardware configuration should also include the function modules such as power module (not shown), these are in the art
Those skilled in the art it should be understood that those skilled in the art in the art can also add corresponding according to the needs of function
Function module, therefore not to repeat here.
So far, first embodiment of the present disclosure floating type stone DSP architecture introduction finishes.
So far, attached drawing is had been combined the embodiment of the present disclosure is described in detail.It should be noted that it in attached drawing or says
In bright book text, the realization method that is not painted or describes is form known to a person of ordinary skill in the art in technical field, and
It is not described in detail.In addition, the above-mentioned definition to each element and method be not limited in mentioning in embodiment it is various specific
Structure, shape or mode, those of ordinary skill in the art simply can be changed or replaced to it.
Unless there are known entitled phase otherwise meaning, the numerical parameter in this specification and appended claims are approximations, energy
Enough required characteristic changings according to as obtained by content of this disclosure.Specifically, all be used in specification and claim
The number of the middle content for representing composition, reaction condition etc., it is thus understood that repaiied by the term of " about " in all situations
Decorations.Under normal circumstances, the meaning of expression refers to include by specific quantity ± 10% variation in some embodiments, at some
± 5% variation in embodiment, ± 1% variation in some embodiments, in some embodiments ± 0.5% variation.
Furthermore word "comprising" does not exclude the presence of element or step not listed in the claims.Before element
Word "a" or "an" does not exclude the presence of multiple such elements.
Specification and the word of ordinal number such as " first ", " second ", " third " etc. used in claim, with modification
Corresponding element, itself is not meant to that the element has any ordinal number, does not also represent the suitable of a certain element and another element
Sequence in sequence or manufacturing method, the use of those ordinal numbers are only used for enabling the element with certain name and another tool
The element for having identical name can make clear differentiation.
In addition, unless specifically described or the step of must sequentially occur, there is no restriction in more than institute for the sequence of above-mentioned steps
Row, and can change or rearrange according to required design.And above-described embodiment can be based on the considerations of design and reliability, that
This mix and match is used using or with other embodiment mix and match, i.e., the technical characteristic in different embodiments can be freely combined
Form more embodiments.
Those skilled in the art, which are appreciated that, to carry out adaptively the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.It can be the module or list in embodiment
Member or component be combined into a module or unit or component and can be divided into addition multiple submodule or subelement or
Sub-component.Other than such feature and/or at least some of process or unit exclude each other, it may be used any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification is (including adjoint power
Profit requirement, abstract and attached drawing) disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation
It replaces.If also, in the unit claim for listing equipment for drying, several in these devices can be by same hard
Part item embodies.
Similarly, it should be understood that in order to simplify the disclosure and help to understand one or more of each open aspect,
Above in the description of the exemplary embodiment of the disclosure, each feature of the disclosure is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：I.e. required guarantor
The disclosure of shield requires features more more than the feature being expressly recited in each claim.More precisely, as following
Claims reflect as, open aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following specific embodiment are expressly incorporated in the specific embodiment, wherein each claim is in itself
All as the separate embodiments of the disclosure.
Particular embodiments described above has carried out the purpose, technical solution and advantageous effect of the disclosure further in detail
It describes in detail bright, it should be understood that the foregoing is merely the specific embodiment of the disclosure, is not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of embedded floating type DSP stone structures for FPGA, including：
First input unit, by input register group and floating number multiplication it is special before plus device form, by corresponding configuration bit,
Input deposit or bypass selection are carried out to input data；
Multiplier unit is connected to first input unit, receives the input data that prime passes through register；
Second input unit including the second input register group, is connected to the output terminal of multiplier unit；
Multiple selector group unit, is made of multiple selectors, and input terminal is connected to the output terminal of second input unit,
The output terminal of one input unit；
ALU units, including adder and logical unit, the adder provides for floating number and fixed-point number and adds and subtracts and multiply
Method operation is used, while also provides logical operation for fixed-point number；And
Output unit, for exporting operation result.
2. embedded floating type DSP stone structures according to claim 1, wherein, ALU units further include adjustment circuit,
Unit, coding module, detection tree module, preliminary shift module, shift-corrected module are rounded, wherein before the adjustment circuit includes
Lead zero detection circuit and an error transfer factor circuit.
3. embedded floating type DSP stone structures according to claim 2, when carrying out floating number multiplying, first
The preceding plus device unit of input unit is used to sum to the exponential part of the floating number of input, and multiplier unit is used for mantissa
Part carries out multiplication operation, and ALU units are used to complete the adjustment of floating number, normalization and rounding-off operation.
4. embedded floating type DSP stone structures according to claim 2, when carrying out floating number signed magnitude arithmetic(al),
In ALU units, two floating numbers of input can be respectively fed to two paths, all the way signal using adder to two floating numbers into
Row plus-minus operation, obtained result detect in mantissa part result 0 number by leading zero probe unit, and progress one is preliminary
Displacement and index adjustment, another way signal be encoded after be sent into detection tree construction in, finally generate signal, indicate whether need
The signal tentatively shifted is further adjusted, finally obtain the result of floating number signed magnitude arithmetic(al).
5. embedded floating type DSP stone structures according to claim 2, the output unit include：
Output register group, output register group provides deposit unit for the adder unit in prime ALU units, after calculating
Result be registered in adder, by result in cumulative operation；
Pattern detector, the pattern detector be configurable module, user by the pattern in configuration mode detector to
Whether detection output result is consistent with pattern, so as to make the specific data of DSP output user's needs.
6. embedded floating type DSP stone structures according to claim 2,
Multiplier unit carries out operand by way of booth codings multiplication operation, and the number of compression section product, simultaneously
Further partial product is compressed with reference to the tree-like adder of multiplier unit, and combines the leading zero detection in ALU units
Circuit further corrects the result of gained.
7. embedded floating type DSP stone structures according to claim 2,
The multiplier unit introduces the structure of assembly line during design.
8. embedded floating type DSP stone structures according to claim 2,
Second input unit be also connected to including：Multiple selector group selection signal OPMODE, carry signal CARRYIN, port C
Data input pin and ALU operation modes configuration signal ALUMODE.
9. embedded floating type DSP stone structures according to claim 2,
The input terminal of multiple selector group unit is also connected to the cascade signal PCIN including DSP results, defeated for option value
Enter the CARRYINSEL signals in source and output feedback signal PCOUT, and multichannel is selected by corresponding gating signal OPMODE
The selector selected in device group unit is selected, and is switched different function and/or is changed the data being input in next stage adder
Source.
10. embedded floating type DSP stone structures according to claim 2,
Used port when first input unit and/or output unit reserve DSP cascades.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113746471B (en) * | 2021-09-10 | 2024-05-07 | 中科寒武纪科技股份有限公司 | Arithmetic circuit, chip and board card |
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| CN117891430A (en) * | 2024-03-18 | 2024-04-16 | 中科亿海微电子科技（苏州）有限公司 | Floating point multiplication and addition structure applied to FPGA embedded DSP |
| CN117891430B (en) * | 2024-03-18 | 2024-05-14 | 中科亿海微电子科技（苏州）有限公司 | Floating point multiplication and addition structure applied to FPGA embedded DSP |
| CN117931123A (en) * | 2024-03-25 | 2024-04-26 | 中科亿海微电子科技（苏州）有限公司 | Low-power-consumption variable-precision embedded DSP hard core structure applied to FPGA |
| CN117931123B (en) * | 2024-03-25 | 2024-06-14 | 中科亿海微电子科技（苏州）有限公司 | Low-power-consumption variable-precision embedded DSP hard core structure applied to FPGA |
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