CN108255690A - A kind of server performance measure - Google Patents
A kind of server performance measure Download PDFInfo
- Publication number
- CN108255690A CN108255690A CN201810039311.7A CN201810039311A CN108255690A CN 108255690 A CN108255690 A CN 108255690A CN 201810039311 A CN201810039311 A CN 201810039311A CN 108255690 A CN108255690 A CN 108255690A
- Authority
- CN
- China
- Prior art keywords
- miss
- hit
- mshr
- cache
- concurrent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
- G06F11/3423—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time where the assessed time is active or idle time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
- G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3476—Data logging
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a kind of server performance measures, are related to processor performance measurement field.The present invention includes CPU, Cache, MSHR and concurrent monitoring device, Cache are connect respectively with CPU and MSHR；Concurrent monitoring device is connect respectively with Cache and MSHR；Wherein, concurrent monitoring device concurrently accesses monitor including Hit Hit, Hit miss concurrently access monitor and miss miss concurrently access monitor, and three kinds concurrently access monitor and measure corresponding lap substitution formula：Time HT+ (tri- kinds of concurrent laps of miss rate MR) * miss penalties MP is hit to calculate real server performance.The present invention concurrently accesses monitor by the three kinds of cachings added in the buffer, concurrent phenomenon when hit and missing is measured out, accurate dissect caches concurrent situation, shoot off concurrent overlapping phenomenon, the physical storage dead time is obtained in real time, and accurately server performance is measured.
Description
Technical field
The invention belongs to processor performances to measure field, more particularly to a kind of server performance measure.
Background technology
The evaluation of processor operational performance is to calculate the time as standard using processor.And processor calculates the time by run time
It is formed with the memory stalls time.The memory stalls time postpones tens times to thousands of times compared with processor run time, decides
Processor calculates time, that is, the calculated performance of processor.The calculating of current memory stalls time is dependent on program
Miss rate MR, average memory access time AMAT=hit time HT+ miss rate MR* miss penalties MP.It is held in present procedure
Row develops into Out-of-order execution and is equipped under the conditions of non-block type caching, and Out-of-order execution is equipped with non-the a large amount of of obstruction caching generation and concurrently visits
It asks.And in practice, it is not that each missing data access corresponds to memory stalls due to caching the presence concurrently accessed,
Existing foundation miss rate is as the evaluation criterion of processor performance, it is difficult to reflect processor actual performance.
The problem of present invention is difficult to measure according to above-mentioned processor performance, it is concurrent by the three kinds of cachings added in the buffer
Monitor is accessed, measures out concurrent phenomenon when hit and missing, accurate dissect caches concurrent situation, on the basis of MR, plane
Concurrent overlapping phenomenon is removed, in the calculating of memory stalls stand-by period, takes into account that caching is concurrent, obtains practical storage in real time
The device dead time.
Invention content
The purpose of the present invention is to provide a kind of server performance measures, pass through the three kinds of cachings added in the buffer
Monitor is concurrently accessed, measures out concurrent phenomenon when hit and missing, accurate dissect caches concurrent situation, shoot off and be concurrently overlapped
Phenomenon obtains the physical storage dead time in real time, solve existing processor performance be difficult to measure, can not Accurate Determining
The problem of.
In order to solve the above technical problems, the present invention is achieved by the following technical solutions：
The present invention is a kind of server performance measure, described including CPU, Cache, MSHR and concurrent monitoring device
Cache is connect respectively with CPU and MSHR；The concurrent monitoring device is connect respectively with Cache and MSHR；The CPU has been used for
Paired data is stored, handled and is controlled；The Cache is that a kind of cache memory subsystem frequently makes for replicating
Data are in favor of quickly accessing；The MSHR is that a kind of Computer Architecture is used to record the thing that each single item does not complete
Business；The concurrent monitoring device is including Hit-Hit concurrently accesses monitor, Hit-miss concurrently accesses monitor and miss-
Miss concurrently accesses monitor；The Hit-Hit concurrently accesses monitor and is connect with Cache, and Hit-Hit concurrently accesses monitor
For measuring the lap of Hit-Hit；The Hit-miss concurrently accesses monitor and is connect respectively with Cache and MSHR, Hit-
Miss concurrently accesses monitor for measuring the lap of Hit-miss；The miss-miss concurrently accesses monitoring and connects with MSHR
It connects, miss-miss concurrently accesses monitor for measuring the lap of miss-miss.
Preferably, the MSHR records transaction information includes fail address, keyword message and renaming register letter
Breath.
Preferably, the concurrent monitoring device includes signal monitoring device and counter register.
Preferably, the server performance calculation formula is：Server mean access time ATMA=hits time HT+
(tri- kinds of concurrent laps of miss rate MR-) * miss penalties MP.
The invention has the advantages that：
Three kinds of cachings adding in the buffer of the present invention concurrently access monitor, when measuring out hit and lacking and find
As accurate dissect caches concurrent situation, shoots off concurrent overlapping phenomenon, obtains the physical storage dead time in real time, accurately
Server performance is measured.
Certainly, it implements any of the products of the present invention and does not necessarily require achieving all the advantages described above at the same time.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, embodiment will be described below required
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is a kind of server performance measure structure diagram of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained all other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
Refering to Figure 1, the present invention is a kind of server performance measure, including CPU, Cache, MSHR and concurrently
Monitoring device, Cache are connect respectively with CPU and MSHR；Concurrent monitoring device is connect respectively with Cache and MSHR；CPU has been used for
Paired data is stored, handled and is controlled；Cache is that a kind of cache memory subsystem frequently uses for replicating
Data are in favor of quickly accessing；MSHR is that a kind of Computer Architecture is used to record the affairs that each single item does not complete；Concurrently supervise
It surveys device and including Hit-Hit concurrently accesses monitor, Hit-miss and concurrently access monitor and miss-miss and concurrently access monitoring
Device；Hit-Hit concurrently accesses monitor and is connect with Cache, and Hit-Hit concurrently accesses monitor for measuring the weight of Hit-Hit
Folded amount, Hit-Hit access overlapping for calculating-calculating, can increase processor availability data；Hit-miss concurrently accesses monitoring
Device is connect respectively with Cache and MSHR, and Hit-miss concurrently accesses monitor for measuring the lap of Hit-miss, Hit-
Miss accesses overlapping for calculating-storage；Miss-miss concurrently accesses monitoring and is connect with MSHR, and miss-miss concurrently accesses monitoring
Device is used to measure the lap of miss-miss, and miss-miss accesses overlapping for storage access-storage.
Wherein, MSHR records transaction information includes fail address, keyword message and renaming register information, once
Storage control returns to the failure required data of memory access, these data are just used to re-execute；MSHR is additionally operable to merge to same
Multiple requests of a line prevent from sending same request multiple.
Wherein, concurrent monitoring device is including the signal monitoring device for being monitored to signal and for calculating information time
Several counter registers.
Wherein, server performance calculation formula is：Server mean access time ATMA=hits time HT+ (miss rate
Tri- kinds of concurrent laps of MR-) * miss penalties MP.
It is worth noting that, in above system embodiment, included each unit is only drawn according to function logic
Point, but above-mentioned division is not limited to, as long as corresponding function can be realized；In addition, each functional unit is specific
Title is also only to facilitate mutually distinguish, the protection domain being not intended to restrict the invention.
In addition, one of ordinary skill in the art will appreciate that realize all or part of step in the various embodiments described above method
It is that relevant hardware can be instructed to complete by program, corresponding program can be stored in a computer-readable storage and be situated between
In matter, the storage medium, such as ROM/RAM, disk or CD.
Present invention disclosed above preferred embodiment is only intended to help to illustrate the present invention.There is no detailed for preferred embodiment
All details are described, are not limited the invention to the specific embodiments described.Obviously, according to the content of this specification,
It can make many modifications and variations.This specification is chosen and specifically describes these embodiments, is in order to preferably explain the present invention
Principle and practical application, so as to which skilled artisan be enable to be best understood by and utilize the present invention.The present invention is only
It is limited by claims and its four corner and equivalent.
Claims (5)
1. a kind of server performance measure, including CPU, Cache, MSHR and concurrent monitoring device, it is characterised in that：
The Cache is connect respectively with CPU and MSHR；The concurrent monitoring device is connect respectively with Cache and MSHR；
The CPU has been used for paired data and has been stored, handled and controlled；
The Cache is that a kind of cache memory subsystem is used to replicate the data that frequently use in favor of quickly accessing；
The MSHR is that a kind of Computer Architecture is used to record the affairs that each single item does not complete；
The concurrent monitoring device is including Hit-Hit concurrently accesses monitor, Hit-miss concurrently accesses monitor and miss-
Miss concurrently accesses monitor；The Hit-Hit concurrently accesses monitor and is connect with Cache, and Hit-Hit concurrently accesses monitor
For measuring the lap of Hit-Hit；The Hit-miss concurrently accesses monitor and is connect respectively with Cache and MSHR, Hit-
Miss concurrently accesses monitor for measuring the lap of Hit-miss；The miss-miss concurrently accesses monitoring and connects with MSHR
It connects, miss-miss concurrently accesses monitor for measuring the lap of miss-miss.
A kind of 2. server performance measure according to claim 1, which is characterized in that the MSHR records affairs letter
Breath includes fail address, keyword message and renaming register information.
A kind of 3. server performance measure according to claim 1, which is characterized in that the concurrent monitoring device packet
Include signal monitoring device and counter register.
4. a kind of server performance measure according to claim 1, which is characterized in that the Hit-Hit information by
Front and rear access of multiple buffers forms overlapping；The Hit-miss is passed from cache processor dataport data to processor
There are caching MSHR components to be used to form overlapping during passing；The miss-miss is by caching multiple units in MSHR components
It is used to form overlapping.
5. a kind of server performance measure according to claim 1, which is characterized in that the server performance calculates
Formula is：Server mean access time ATMA=hits time HT+ (tri- kinds of concurrent laps of miss rate MR-) * miss penalties
MP。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810039311.7A CN108255690A (en) | 2018-01-16 | 2018-01-16 | A kind of server performance measure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810039311.7A CN108255690A (en) | 2018-01-16 | 2018-01-16 | A kind of server performance measure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108255690A true CN108255690A (en) | 2018-07-06 |
Family
ID=62741256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810039311.7A Pending CN108255690A (en) | 2018-01-16 | 2018-01-16 | A kind of server performance measure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108255690A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113127065A (en) * | 2021-04-19 | 2021-07-16 | 之江实验室 | Storage and computation integrated program partitioning method and device based on pure missing detection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150268963A1 (en) * | 2014-03-23 | 2015-09-24 | Technion Research & Development Foundation Ltd. | Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware |
| CN107169379A (en) * | 2017-05-19 | 2017-09-15 | 郑州云海信息技术有限公司 | A kind of method and server that integrity measurement is carried out based on BMC and TCM |
-
2018
- 2018-01-16 CN CN201810039311.7A patent/CN108255690A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150268963A1 (en) * | 2014-03-23 | 2015-09-24 | Technion Research & Development Foundation Ltd. | Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware |
| CN107169379A (en) * | 2017-05-19 | 2017-09-15 | 郑州云海信息技术有限公司 | A kind of method and server that integrity measurement is carried out based on BMC and TCM |
Non-Patent Citations (2)
| Title |
|---|
| XIAN-HE SUN等: "Concurrent Average Memory Access Time", 《IEEE》 * |
| XIAN-HE SUN等: "Evaluating the Combined Effect of Memory Capacity and Concurrency for Many-Core Chip Design", 《ACM》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113127065A (en) * | 2021-04-19 | 2021-07-16 | 之江实验室 | Storage and computation integrated program partitioning method and device based on pure missing detection method |
| CN113127065B (en) * | 2021-04-19 | 2022-07-08 | 之江实验室 | Storage and computation integrated program partitioning method and device based on pure missing detection method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101442913B1 (en) | Information processing apparatus, control method, and computer-readable recording medium having recorded therein control program | |
| KR100292642B1 (en) | Systems and Methods for Interfering Code Instrumentation | |
| Wenisch et al. | Temporal streaming of shared memory | |
| Elver et al. | TSO-CC: Consistency directed cache coherence for TSO | |
| US7360022B2 (en) | Synchronizing an instruction cache and a data cache on demand | |
| US10853219B2 (en) | Real-time input/output bandwidth estimation | |
| US9122508B2 (en) | Real time measurement of I/O interrupt delay times by hypervisor by selectively starting and/or stopping corresponding LPARs | |
| US20120173825A1 (en) | Cache Result Register for Quick Cache Information Lookup | |
| CN116627811A (en) | Method, computer system and medium for monitoring memory location where breakpoint occurs | |
| Wang et al. | CXL over Ethernet: A novel FPGA-based memory disaggregation design in data centers | |
| US20060242517A1 (en) | Monitoring a data processor to detect abnormal operation | |
| CN108255690A (en) | A kind of server performance measure | |
| Schuh et al. | CC-NIC: a Cache-Coherent Interface to the NIC | |
| US20150039834A1 (en) | Sharing local cache from a failover node | |
| JP5800058B2 (en) | Information processing apparatus, control method, and control program | |
| US8122278B2 (en) | Clock skew measurement for multiprocessor systems | |
| US11914517B2 (en) | Method and apparatus for monitoring memory access traffic | |
| Thober et al. | Improving coherency of runtime integrity measurement | |
| US20140372691A1 (en) | Counter policy implementation | |
| US8996816B2 (en) | Method and apparatus for selectively bypassing a cache for trace collection in a processor | |
| Jiang et al. | {Sync+ Sync}: A Covert Channel Built on fsync with Storage | |
| KR102627410B1 (en) | Quality of Service Dirty Line Tracking | |
| CN111552583A (en) | Locating potential problems to objects | |
| US20240111682A1 (en) | Runtime Flushing to Persistency in Heterogenous Systems | |
| US20220171656A1 (en) | Adjustable-precision multidimensional memory entropy sampling for optimizing memory resource allocation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180706 |