CN108234068A - Transmit the method and its equipment of low density parity check code - Google Patents
Transmit the method and its equipment of low density parity check code Download PDFInfo
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- CN108234068A CN108234068A CN201611159868.1A CN201611159868A CN108234068A CN 108234068 A CN108234068 A CN 108234068A CN 201611159868 A CN201611159868 A CN 201611159868A CN 108234068 A CN108234068 A CN 108234068A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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Abstract
The embodiment of the present application provides a kind of method for transmitting low-density checksum LDPC code, including：Obtain the modulation system that the code check of the first bit sequence to be sent and first bit sequence use；According to the modulation system that the code check of first bit sequence and first bit sequence use, coding post processing is carried out, obtains the second bit sequence, the coding post processing includes at least one of punching processing and interleaving treatment；Send second bit sequence.Therefore, it according to the code check size and modulation system of bit sequence, selects to carry out the first bit sequence punching processing or processing is interleaved to the first bit sequence, be conducive to the performance and equipment power dissipation of balanced communication system.
Description
Technical field
The invention relates to the communications field, and more particularly, to a kind of transmission low density parity check code
Method and its equipment.
Background technology
Transmit low-density checksum (English：Low-density Parity-check, write a Chinese character in simplified form：LDPC) code initially by
Gallager was proposed in 1962, but since the limitation of level of hardware at that time, excellent properties fail to be embodied, this causes
LDPC code is ignored within subsequent a very long time by people.Go out as the enhancing of computer capacity and iterative decoding are theoretical
Existing, 1996, Mackay and Neal et al. re-started LDPC code research, it was demonstrated that LDPC code is using based on confidence biography
The superperformance for having under the iterative decoding algorithm of BP (Belief propagation) and approaching shannon limit is broadcast, from this LDPC code
The extensive concern of people is caused, a large amount of research is unfolded therewith.
LDPC code is had excellent performance, and performance is better than Turbo code under big block length and high code check scene, and with relatively low mistake
Accidentally flat bed；Decoding complexity is low, and decoding architecture is suitble to parallel, it is easy to accomplish high-speed coding.More than advantage is based on, LDPC code obtains
It is widely applied.
Therefore, there is an urgent need for a kind of methods for transmitting LDPC code, are capable of the performance and equipment power dissipation of effective balanced communication system.
Invention content
The embodiment of the present application provide it is a kind of transmit LDPC code method, can effectively the performance of balanced communication system with set
Standby power consumption.
In a first aspect, a kind of method for transmitting low-density checksum LDPC code is provided, including：Obtain to be sent first
The modulation system that the code check of bit sequence and first bit sequence use；According to the code check of first bit sequence and institute
The modulation system of the first bit sequence use is stated, carries out coding post processing, obtains the second bit sequence, the coding post processing packet
Include at least one of punching processing and interleaving treatment；Send second bit sequence.
First bit sequence refers to the bit sequence encoded by LDPC encoder, what the first bit sequence used
Modulation system can be it is following in any one：Binary phase shift keying (English：Binary Phase Shift Keying,
It writes a Chinese character in simplified form：BPSK), binary orthogonal amplitude modulation (English：4Quadrature Amplitude Modulation, write a Chinese character in simplified form：
4QAM), 16QAM, 64QAM, 256QAM etc..
Therefore, it according to the code check size and modulation system of bit sequence, selects to carry out punching processing to the first bit sequence,
Or processing is interleaved to the first bit sequence, be conducive to the performance and equipment power dissipation of balanced communication system.
With reference to first aspect, it is described according to the first bit sequence in the first possible realization method of first aspect
The modulation system used is arranged, coding post processing is carried out to first bit sequence, obtains the second bit sequence, including：If institute
Modulation system that the first bit sequence uses is stated as high-order modulating, and the code check of first bit sequence is less than default threshold
Value, is interleaved processing to first bit sequence, obtains the second bit sequence；If or first bit sequence use
Modulation system is high-order modulating, and the code check of first bit sequence is more than or equal to predetermined threshold value, to described the
One bit sequence carries out punching processing, obtains the second bit sequence；If or the modulation system that uses of first bit sequence for
Low-order-modulated mode carries out punching processing to the bit sequence to be sent, obtains the second bit sequence.
It should be understood that the predetermined threshold value of code check is empirical value, such as it can be 2/3 or wait, in the first bit sequence using high
When rank modulation system and code check are less than predetermined threshold value, processing is interleaved to the first bit sequence, it can be with the communication of lifting system
Performance；When the first bit sequence is high-order modulating and code check is not less than predetermined threshold value, the first bit sequence is beaten
Hole is handled, and can obtain certain postiive gain at this time；When the first bit sequence is low-order-modulated mode, to the first bit sequence
Punching processing is carried out, can also obtain certain postiive gain at this time.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
With reference to first aspect and its above-mentioned realization method, it is described in second of possible realization method of first aspect
When the modulation system that first bit sequence uses is low-order-modulated mode, the bit sequence to be sent is punched
Processing, obtains the second bit sequence, including：Punching processing, institute are carried out to the target bits set in first bit sequence
It is corresponding with arranging the most heavy n row of weight in the check matrix of first bit sequence to state target bits set, wherein n is positive integer.
With reference to first aspect and its above-mentioned realization method, it is described in the third possible realization method of first aspect
High-order modulating is for quadrature amplitude modulation 16QAM or more than the modulation system of 16QAM higher order；The low-order-modulated mode is
The modulation system used than 16QAM more low orders.
With reference to first aspect and its above-mentioned realization method, in the third possible realization method of first aspect, code check
The predetermined threshold value be 2/3.
Second aspect provides a kind of method for transmitting low-density checksum LDPC code, including：Receive the first bit sequence
Row, wherein, first bit sequence is to carry out the bit sequence that coding post processing obtains, and the coding post processing includes punching
At least one of processing and interleaving treatment；It is used according to the code check of first bit sequence and first bit sequence
Modulation system is decoded processing, obtains the second bit sequence.
It should be understood that the first bit sequence described in second aspect embodiment refers to the bit received by channel sources
Set.
Therefore, it according to the code check size and modulation system of bit sequence, selects to be decoded processing to the first bit sequence,
Be conducive to the performance and equipment power dissipation of balanced communication system.
It is described according to first bit in the first possible realization method of second aspect with reference to second aspect
The modulation system that the code check of sequence and first bit sequence use, is decoded processing, obtains the second bit sequence, wraps
It includes：If the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is small
In predetermined threshold value, processing is interleaved to first bit sequence, obtains the second bit sequence；If or the first bit sequence
The modulation system used is arranged as high-order modulating, and the code check of first bit sequence is more than or equal to predetermined threshold value,
Punching processing is carried out to first bit sequence, obtains the second bit sequence；If the or tune that first bit sequence uses
Mode processed is low-order-modulated mode, carries out punching processing to the bit sequence to be sent, obtains the second bit sequence.
It is described in second of possible realization method of second aspect with reference to second aspect and its above-mentioned realization method
High-order modulating is for quadrature amplitude modulation 16QAM or more than the modulation system of 16QAM higher order；The low-order-modulated mode is
The modulation system used than 16QAM more low orders.
It is described in the third possible realization method of second aspect with reference to second aspect and its above-mentioned realization method
The predetermined threshold value of code check is 2/3.
The third aspect provides another network equipment, can for performing above-mentioned first aspect or the arbitrary of first aspect
Method in the realization method of energy.Specifically, which includes times for performing above-mentioned first aspect or first aspect
The unit for the method anticipated in possible realization method.
Fourth aspect provides another network equipment, can for performing above-mentioned second aspect or the arbitrary of second aspect
Method in the realization method of energy.Specifically, which includes times for performing above-mentioned second aspect or second aspect
The unit for the method anticipated in possible realization method.
5th aspect, provides a kind of network equipment, which includes：Transceiver, memory, processor and bus
System.Wherein, the transceiver, the memory and the processor are connected by the bus system, the memory for storing instruction,
The processor is used to perform the instruction of memory storage, transceiver to be controlled to receive and/or sends signal, and when the processing
When device performs the instruction of memory storage, which causes the processor to perform the arbitrary possibility of first aspect or first aspect
Realization method in method.
6th aspect, provides a kind of network equipment, which includes：Transceiver, memory, processor and bus
System.Wherein, the transceiver, the memory and the processor are connected by the bus system, the memory for storing instruction,
The processor is for performing the instruction of memory storage, transceiver to be controlled to receive signal and/or sends signal, and work as and be somebody's turn to do
When processor performs the instruction of memory storage, which causes the processor to perform the arbitrary of second aspect or second aspect
Method in possible realization method.
7th aspect, provides a kind of computer-readable medium, for storing computer program, which includes
For performing the instruction of the method in the arbitrary possible realization method of first aspect or first aspect.
Eighth aspect provides a kind of computer-readable medium, and for storing computer program, which includes
For performing the instruction of the method in the arbitrary possible realization method of second aspect or second aspect.
Description of the drawings
Fig. 1 is the schematic flow chart of the method for the application one embodiment.
Fig. 2 shows the schematic diagrames of the method for the application one embodiment.
Fig. 3 shows the perforation structure schematic diagram of the check matrix of the LDPC code of the application one embodiment.
Fig. 4 shows the schematic flow chart of the method for the transmission LDPC code of another embodiment of the application.
Fig. 5 A and Fig. 5 B show the schematic diagram of the performance gain of the method for the application one embodiment.
Fig. 6 shows the schematic diagram of the performance gain of the method for another embodiment of the application.
Fig. 7 shows the schematic block diagram of the network equipment 700 of the application one embodiment.
Fig. 8 shows the schematic block diagram of the network equipment 800 of the application one embodiment.
Fig. 9 is the schematic block diagram of the device 900 of another embodiment of the application.
Figure 10 is the schematic block diagram of the device 1000 of another embodiment of the application.
Specific embodiment
Fig. 1 is the schematic flow chart of the method for the application one embodiment.As shown in Figure 1, the execution master of this method 100
Body is the network equipment of transmitting terminal, can be applied to base station, terminal, Wireless Fidelity (Wireless-Fidelity, Wi-Fi) skill
The coding of the equipment such as the access point (Access Point, AP) of art, the terminal of Wi-Fi technology, relay node (Relay Node)
In the process, but the embodiment of the present application is not limited to more than communication equipment.
Wherein, base station can be the network equipment for communicating with terminal device, for example, it may be gsm system or
In base station (Base Transceiver Station, BTS) or WCDMA system in CDMA base station (NodeB,
NB), it can also be evolved base station (Evolutional Node B, eNB or eNodeB) or base station in LTE system
It can be network side equipment in relay station, access point, mobile unit, wearable device and future 5G networks etc..
Terminal can be carried out through wireless access network (Radio Access Network, RAN) and one or more core nets
Communication, terminal can refer to user equipment (User Equipment, UE), access terminal, subscriber unit, subscriber station, movement station, shifting
Dynamic platform, remote station, remote terminal, mobile equipment, user terminal, wireless telecom equipment, user agent or user apparatus.Access is eventually
End can be cellular phone, wireless phone, session initiation protocol (Session Initiation Protocol, SIP) phone,
Wireless local loop (Wireless Local Loop, WLL) is stood, personal digital assistant (Personal Digital
Assistant, PDA), have the handheld device of wireless communication function, computing device or be connected to radio modem its
Its processing equipment, mobile unit, wearable device, the terminal device in following 5G networks etc..
Method 100 includes：
Step 110, the modulation system that the code check of the first bit sequence to be sent and the first bit sequence use is obtained.
Step 120, the modulation system used according to the code check of the first bit sequence and the first bit sequence, after being encoded
Processing, obtains the second bit sequence, and coding post processing includes at least one of punching processing and interleaving treatment.
Step 130, the second bit sequence is sent.
Specifically, in step 110, the first bit sequence refers to the bit sequence encoded by LDPC encoder
Row, the modulation system that the first bit sequence uses can be any one in following：Binary phase shift keying (English：
Binary Phase Shift Keying, write a Chinese character in simplified form：BPSK), binary orthogonal amplitude modulation (English：4Quadrature
Amplitude Modulation, write a Chinese character in simplified form：4QAM), 16QAM, 64QAM, 256QAM etc..
Specifically, in LDPC channel codings, the data block of K symbol sizes passes through code of the coding mapping for N symbol sizes
Word K/N is code check, for example, code check can be 8/9,5/6,3/4,2/3,1/3,1/5 etc..
It should be understood that transmitting terminal can by communication environment, look into modulation and coding strategy (English：
Modulation and Coding Scheme, write a Chinese character in simplified form：MCS) the modes such as table obtain the first bit sequence to be sent
The modulation system that the code check of row and the first bit sequence use.
Specifically, in step 120, according to the code check size of the first bit sequence and the modulation methods of the first bit sequence use
Formula, selection obtain the second bit sequence using punching processing either interleaving treatment.
Therefore, it according to the code check size and modulation system of bit sequence, selects to carry out punching processing to the first bit sequence,
Or processing is interleaved to the first bit sequence, be conducive to the performance and equipment power dissipation of balanced communication system.
Optionally, as the application one embodiment, the modulation system used according to first bit sequence is right
First bit sequence carries out coding post processing, obtains the second bit sequence, including：If what first bit sequence used
Modulation system is high-order modulating, and the code check of first bit sequence is less than predetermined threshold value, to the first bit sequence
Row are interleaved processing, obtain the second bit sequence；If or the modulation system that first bit sequence uses is high order modulation
Mode, and the code check of first bit sequence is more than or equal to predetermined threshold value, and first bit sequence is punched
Processing, obtains the second bit sequence；If or the modulation system that first bit sequence uses is low-order-modulated mode, to described
Bit sequence to be sent carries out punching processing, obtains the second bit sequence.
It should be understood that some modulation systems that high-order modulating can be due up, in some cases it may define high-order
It is modulated to 64QAM or the modulation system than 64QAM higher order, then low-order-modulated mode can be 64QAM or lower than 64QAM
The modulation system of rank；In other cases, high-order modulating is for quadrature amplitude modulation 16QAM or more than 16QAM higher order
Modulation system；Low-order-modulated mode is the modulation system used than 16QAM more low orders, and the embodiment of the present application is without being limited thereto.
After should also be understood that if the bit number of the modulation the latter symbol carrying of modulation system one is modulated than modulation system two
The bit number of carrying is more, then modulation system one is exactly than the modulation system of two higher order of modulation system, conversely, then modulation methods
First formula is than the modulation system of the more low order of modulation system two.
It should be understood that the predetermined threshold value of code check is empirical value, such as it can be 2/3 or wait, in the first bit sequence using high
When rank modulation system and code check are less than predetermined threshold value, processing is interleaved to the first bit sequence, it can be with the communication of lifting system
Performance；When the first bit sequence is high-order modulating and code check is not less than predetermined threshold value, the first bit sequence is beaten
Hole is handled, and can obtain certain postiive gain at this time；When the first bit sequence is low-order-modulated mode, to the first bit sequence
Punching processing is carried out, can also obtain certain postiive gain at this time.
It should be understood that interleaver is optimized according to the structure of specific modulation format and check matrix, it can cause system
Better gain is obtained in high order modulation.
Fig. 2 shows the schematic diagrames of the method for the application one embodiment.As described in Figure 2, coding is sequentially shown in figure
Device, perforating module, interleaving block, modulator, channel, demodulator, de-interleaving block and decoder, wherein, selector 203 is beaten
Casement block, selector 205 and interleaving block constitute transmitting terminal 201, and de-interleaving block and selector 207 constitute receiving terminal
202.Specifically, if the first bit sequence exported after encoder is unsatisfactory for threshold condition using high order modulation but code check
When or LDPC code use low-order-modulated when, then into perforating module carry out punching processing without be interleaved processing, that is,
Say, transmitting terminal 201 determine the first bit sequence need be sent into perforating module carry out punching processing when, the first bit sequence can be led to
It crosses the selection of selector 203 to carry out perforating module and carry out punching handling to obtain the second bit sequence, is sent into selector 205, selector
Second bit sequence is sent to modulator by 205 through access 206.Otherwise, the first bit sequence is passed through access by selector 203
204 are sent into selectors 205, at this time if it is determined that the first bit sequence needs to be sent into interleaving block when being interleaved processing, selection
First bit sequence will be sent into interleaving block and obtain the second bit sequence by device 205, will further be obtained by interleaving block
The second bit sequence be sent into modulator in.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
Optionally, as the application one embodiment, the modulation system used when first bit sequence is low
During rank modulation system, punching processing is carried out to the bit sequence to be sent, obtains the second bit sequence, including：To described
Target bits set in one bit sequence carries out punching processing, the target bits set and the school of first bit sequence
It tests in matrix and arranges the most heavy n row correspondences of weight, wherein n is positive integer.
For example, n can be 1 or 2, that is to say, that for row weight in the check matrix of the first bit sequence it is most heavy first
Row or the corresponding bit set of secondary series carry out punching processing, as shown in figure 3, Fig. 3 shows the application one embodiment
The perforation structure schematic diagram of the check matrix of LDPC code.In figure 3, rectangular box expression is the corresponding school of the first bit sequence
Matrix is tested, what black portions represented is the most heavy n row of row weight, and what white portion represented is the relatively low part of row weight, then row weight
It is exactly the bit set for needing to punch that most heavy n, which arranges corresponding bit set, that is, the target bits in the first bit sequence
Set.When carrying out punching processing, punching processing just is carried out to this partial bit.
Therefore, in low-order-modulated, the most heavy corresponding bit of n row of weight will be arranged in corresponding check matrix and will be carried out at punching
Reason, and in high order modulation, coding gain bigger that bits of some row most heavy in corresponding check matrix are remained, together
When interleaver can obtain more apparent performance boost, therefore more property can be exchanged for some processing delay and power consumption
It can gain.
Optionally, as the application one embodiment, the predetermined threshold value of code check is 2/3.
When the modulation system that the first bit sequence uses is high order modulation, and code check is less than 2/3, the first bit is carried out
Interleaving treatment can obtain the coding gain of bigger.
Fig. 4 shows the schematic flow chart of the method for the transmission LDPC code of another embodiment of the application.This method is held
The network equipment of the row main body for receiving terminal, such as base station or terminal device.As shown in figure 4, this method includes：
Step 410, the first bit sequence is received, wherein, the first bit sequence is to carry out the bit that coding post processing obtains
Sequence, coding post processing include at least one of punching processing and interleaving treatment；
Step 420, the modulation system used according to the code check of the first bit sequence and the first bit sequence, is decoded place
Reason, obtains the second bit sequence.
It should be understood that the first bit sequence described in Fig. 4 embodiments refers to by coding post processing passing through in sending side
The bit set that channel sources receive, coding post processing can be in punching processing or interleaving treatment as described in Fig. 1 or Fig. 2
At least one, for brevity, details are not described herein.
Specifically, if according to the modulation system and code check of the use of the first bit sequence, determine the first bit sequence for warp
Cross the bit sequence obtained after interleaving treatment, then the decoding process of step 420 is included to the deinterleaving of the first bit sequence
Processing.
Specifically, the modulation system used when the first bit sequence is high-order modulating (such as 64QAM), and code check is small
When predetermined threshold value (such as 2/3), then then can determine that the first bit sequence is the bit sequence obtained after interleaving treatment, that
To include the deinterleaving to the first bit sequence in the decoding process of step 420 to handle.Otherwise, if the first bit
The modulation system that sequence uses for high-order modulating, and code check be not less than predetermined threshold value when or the first bit sequence use
Modulation system be low-order-modulated mode when, then do not need to then include to the first bit sequence in the decoding process of step 420
Deinterleaving processing.
Therefore, it according to the code check size and modulation system of bit sequence, selects to be decoded processing to the first bit sequence,
Be conducive to the performance and equipment power dissipation of balanced communication system.
Optionally, it is described according to the code check of first bit sequence and described first as the application one embodiment
The modulation system that bit sequence uses, is decoded processing, obtains the second bit sequence, including：If first bit sequence
The modulation system used is high-order modulating, and the code check of first bit sequence is less than predetermined threshold value, to described first
Bit sequence is interleaved processing, obtains the second bit sequence；If or the modulation system that first bit sequence uses is height
Rank modulation system, and the code check of first bit sequence be more than or equal to predetermined threshold value, to first bit sequence into
Row punching is handled, and obtains the second bit sequence；If or the modulation system that first bit sequence uses is low-order-modulated mode,
Punching processing is carried out to the bit sequence to be sent, obtains the second bit sequence.
Specifically, if as shown in Fig. 2, the modulation system used when the first bit sequence received is high order modulation side
Formula, and when code check is less than predetermined threshold value, processing and decoding are deinterleaved, that is, pass through choosing to first bit sequence
It selects device 207 and is interleaved processing into de-interleaving block, subsequently enter decoder and be decoded processing.Otherwise, selector is by
One bit sequence imports access 208, and processing is decoded into decoder.
Optionally, as the application one embodiment, the high-order modulating is quadrature amplitude modulation 16QAM or more compares
The modulation system of 16QAM higher orders；The low-order-modulated mode is the modulation system used than 16QAM more low orders.
Optionally, as the application one embodiment, the predetermined threshold value of the code check is 2/3.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
Fig. 5 shows the schematic diagram of the performance gain of the method for the application one embodiment.
Specifically, for the modulation system used when the first bit sequence for 256QAM, code word is third generation partner program
(English：3rd Generation Partnership Project, write a Chinese character in simplified form：It 3GPP) organizes in 86 meeting motions by high pass public affairs
Take charge of the quasi- cycle (English in (1640,1040) proposed：Quasi-cyclic writes a Chinese character in simplified form：QC) QC-LDPC codes.The verification of the LDPC code
The corresponding base matrix structure of matrix is as shown in A figures in Fig. 5.
The modulation system used due to first bit sequence is high order modulation, and code check is 1040/1640=0.6341,
The code check is less than 2/3.Therefore, processing is interleaved to first bit sequence, and is handled without punching, that is to say, that the square
The maximum row of array weight or two row are all retained and participate in interweaving.
Interleaver mapping ratio can use mj,iIt represents, wherein subscript j represents the reliability rank in high order modulation symbol
(for example, 256QAM has 4 grades), i represent the row weight type in the corresponding basic matrix of check matrix of LDPC code.In this example, row weight
8 kinds are shared, is 11,12,6,5,4,3,2,1 respectively.mj,iIllustrate that the bit of i-th kind of row weight in corresponding check matrix is mapped
To the ratio of high order modulation symbol jth kind reliability position.
The corresponding interleaver mapping ratio of the present embodiment is shown by table 1.
Table 1
| mj,i | I=1 | I=2 | I=3 | I=4 | I=5 | I=6 | I=12 | I=11 |
| J=1 | 0.037750 | 0.005000 | 0.367000 | 0.370000 | 0.534000 | 0.103000 | 0.006000 | 0.010000 |
| J=2 | 0.690250 | 0.012400 | 0.377000 | 0.259000 | 0.050000 | 0.115000 | 0.023000 | 0.011000 |
| J=3 | 0.019000 | 0.587600 | 0.195500 | 0.369000 | 0.217000 | 0.359000 | 0.132000 | 0.045000 |
| J=4 | 0.253000 | 0.395000 | 0.060500 | 0.002000 | 0.199000 | 0.423000 | 0.839000 | 0.934000 |
Assuming that channel is Gaussian white noise channel, the decoder of receiving terminal is using 50 confidence spread (English：Belief
Propagation writes a Chinese character in simplified form：BP in the case of) decoding, the frame error rate (English of system：Frame error rate, write a Chinese character in simplified form：FER)
As shown in Figure 5.
B shows the frame error rate curve of the embodiment of the present application in 5 in figure, and such as B in Fig. 5, wherein abscissa is signal-to-noise ratio, is indulged
Coordinate is frame error rate, and wherein curve 1 is the performance of the present embodiment, and curve 2 is using performance when punching.As seen from the figure, this reality
The scheme applied can obtain the performance gain of about 0.5dB.
Fig. 6 shows the schematic diagram of the performance gain of the method for another embodiment of the application.
Specifically, for the modulation system used when the first bit sequence for QPSK, code word is identical with embodiment shown in fig. 5.
During due to low-order-modulated, punching can obtain additional performance gain, therefore the selector of perforating module will encode
Data afterwards are sent to card punch, and a row most heavy in corresponding check matrix or the corresponding bit of two row are punched；It is in addition, low
Interleaver does not have gain during contrast, so data are routed directly to modulator by the selector of interleaving block in the present embodiment, with
It reduces processing delay and reduces system power dissipation
Assuming that channel is Gaussian white noise channel, in the case that the decoder of receiving terminal is using 50 BP decodings, system
Frame error rate is as shown in Figure 6.
Wherein curve 1 is the frame error rate curve of the present embodiment, and curve 2 is frame error rate curve when being handled using punching.By
Scheme as it can be seen that punching can obtain the gain of 0.15dB or so in the case where reducing transfer resource in low-order-modulated.
The flow of the method for the embodiment of the present application is described in detail above in conjunction with Fig. 1 to Fig. 6, with reference to Fig. 7 to Figure 10
The equipment of the embodiment of the present application is discussed in detail.
Fig. 7 shows the schematic block diagram of the network equipment 700 of the application one embodiment.The network equipment 700 can be held
By each step performed in the method for row Fig. 1 to Fig. 3 and Fig. 5 and Fig. 6, in order to avoid repeating, no further details here.It should
The network equipment 700 includes：
Acquiring unit, shown acquiring unit are used to obtain the code check of the first bit sequence to be sent and first bit
The modulation system that sequence uses；
Processing unit, the processing unit is for the code check according to first bit sequence and first bit sequence
The modulation system of use carries out coding post processing, obtains the second bit sequence, and the coding post processing includes punching processing and hands over
Knit at least one of processing；
Transmitting element, the transmitting element are used to send second bit sequence.
Optionally, as the application one embodiment, the processing unit is specifically used for：
When the modulation system that first bit sequence uses is high-order modulating, and when code check is less than predetermined threshold value
When, processing is interleaved to first bit sequence, obtains the second bit sequence；Or
When the modulation system that first bit sequence uses is high-order modulating, and when code check is not less than predetermined threshold value
When, punching processing is carried out to first bit sequence, obtains the second bit sequence；Or
When the modulation system that first bit sequence uses is low-order-modulated mode, to the bit sequence to be sent
Punching processing is carried out, obtains the second bit sequence.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
Fig. 8 shows the schematic block diagram of the network equipment 800 of the application one embodiment.The network equipment 800 can be held
By each step performed in the method for row fig. 4 to fig. 6, in order to avoid repeating, no further details here.The network equipment 800 wraps
It includes：
Receiving unit 810, the receiving unit 810 are used to receive the first bit sequence, wherein, first bit sequence
The bit sequence obtained to carry out coding post processing, the coding post processing include at least one in punching processing and interleaving treatment
Kind.
Decoding unit 820, the decoding unit 820 are used for code check and first ratio according to first bit sequence
The modulation system that special sequence uses, is decoded processing, obtains the second bit sequence.
Optionally as the application one embodiment, the decoding unit is specifically used for：When first bit sequence is adopted
Modulation system is high-order modulating, and when code check is less than predetermined threshold value, solution friendship is carried out to first bit sequence
Processing and decoding are knitted, obtains the second bit sequence；
When the modulation system that first bit sequence uses is high-order modulating, and when code check is not less than predetermined threshold value
When, processing is decoded to first bit sequence, obtains the second bit sequence；Or
When the modulation system that first bit sequence uses is low-order-modulated mode, to first bit sequence into
Row decoding process obtains the second bit sequence.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
Fig. 9 is the schematic block diagram of the device 900 of another embodiment of the application.It should be understood that device 900 is able to carry out
By each step performed in the method for Fig. 1 to Fig. 3 and Fig. 5 and Fig. 6, in order to avoid repeating, no further details here.The dress
900 are put to include：
Memory 910, for storing program；
Transceiver 920, for communicating with other equipment；
Processor 930, for performing the program in memory 910, processor 930 and the memory 910 and the receipts
Hair device 920 is respectively connected with, for performing the described instruction that the memory 910 stores, to be performed such as when performing described instruction
Lower step：
Obtain the modulation system that the code check of the first bit sequence to be sent and first bit sequence use；According to institute
The modulation system that the code check of the first bit sequence and first bit sequence use is stated, coding post processing is carried out, obtains second
Bit sequence, the coding post processing include at least one of punching processing and interleaving treatment；The transmitting element is used to send out
Send second bit sequence.
Optionally, as the application one embodiment, the processor 930 is specifically used for：When first bit sequence
The modulation system used hands over first bit sequence for high-order modulating, and when code check is less than predetermined threshold value
Processing is knitted, obtains the second bit sequence；Or the modulation system used when first bit sequence is high-order modulating, and works as
When code check is not less than predetermined threshold value, punching processing is carried out to first bit sequence, obtains the second bit sequence；Or when described
When the modulation system that first bit sequence uses is low-order-modulated mode, punching processing is carried out to the bit sequence to be sent,
Obtain the second bit sequence.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
Figure 10 is the schematic block diagram of the device 1000 of another embodiment of the application.It should be understood that device 1000 can
It performs by each step performed in the method for fig. 4 to fig. 6, in order to avoid repeating, no further details here.The device 1000 wraps
It includes：
Memory 1010, for storing program；
Transceiver 1020, for communicating with other equipment；
Processor 1030, for performing the program in memory 1010, processor 1030 and the memory 1010 and institute
It states transceiver 1020 to be respectively connected with, for performing the described instruction that the memory 1010 stores, with when performing described instruction
Perform following steps：Receive the first bit sequence；It is adopted according to the code check of first bit sequence and first bit sequence
Modulation system is decoded processing, obtains the second bit sequence.
Optionally, as the application one embodiment, the processor 1030 is specifically used for：When first bit sequence
The modulation system used solves first bit sequence for high-order modulating, and when code check is less than predetermined threshold value
Interleaving treatment and decoding obtain the second bit sequence；When the modulation system that first bit sequence uses is high order modulation side
Formula, and when code check is not less than predetermined threshold value, processing is decoded to first bit sequence, obtains the second bit sequence；
Or when the modulation system that first bit sequence uses is low-order-modulated mode, first bit sequence is decoded
Processing, obtains the second bit sequence.
Therefore, the embodiment of the present application is interleaved when LDPC code meets certain threshold value using high order modulation and code check
It handles and is handled without punching, be capable of the communication performance of lifting system, avoid carrying out the negative gain that punching processing is brought；And
When LDPC code is unsatisfactory for threshold condition using high order modulation but code check or when LDPC code uses low-order-modulated, carry out at punching
Reason can realize certain postiive gain without being interleaved processing, and avoid and be interleaved the extra process that processing introduces
The waste of time delay and equipment power dissipation.
Those of ordinary skill in the art may realize that with reference to each method step described in the embodiments described herein
Rapid and unit can realize with the combination of electronic hardware, computer software or the two, in order to clearly demonstrate hardware and soft
The interchangeability of part, the step of generally describing each embodiment according to function in the above description and composition.These
Function is performed actually with hardware or software mode, specific application and design constraint depending on technical solution.Ability
Domain those of ordinary skill can realize described function to each specific application using distinct methods, but this reality
Now it is not considered that beyond scope of the present application.
It is apparent to those skilled in the art that for convenience of description and succinctly, foregoing description is
The specific work process of system, device and unit can refer to the corresponding process in preceding method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of division of logic function can have other dividing mode, such as multiple units or component in actual implementation
It may be combined or can be integrated into another system or some features can be ignored or does not perform.In addition, shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be the INDIRECT COUPLING by some interfaces, device or unit
Or communication connection or electricity, the connection of mechanical or other forms.
The unit illustrated as separating component may or may not be physically separate, be shown as unit
The component shown may or may not be physical unit, you can be located at a place or can also be distributed to multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the embodiment of the present application scheme
Purpose.
The terms "and/or", only a kind of incidence relation for describing affiliated partner, expression may have three kinds of passes
System, for example, A and/or B, can represent：Individualism A exists simultaneously A and B, these three situations of individualism B.In addition, herein
Middle character "/", it is a kind of relationship of "or" to typically represent forward-backward correlation object.
In addition, each functional unit in each embodiment of the application can be integrated in a processing unit, it can also
It is that each unit is individually physically present or two or more units integrate in a unit.It is above-mentioned integrated
The form that hardware had both may be used in unit is realized, can also be realized in the form of SFU software functional unit.
If the integrated unit is realized in the form of SFU software functional unit and is independent product sale or uses
When, it can be stored in a computer read/write memory medium.Based on such understanding, the technical solution of the application is substantially
The part to contribute in other words to the prior art or all or part of the technical solution can be in the form of software products
It embodies, which is stored in a storage medium, is used including some instructions so that a computer
Equipment (can be personal computer, server or the network equipment etc.) performs the complete of each embodiment the method for the application
Portion or part steps.And aforementioned storage medium includes：USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, letter
Referred to as " ROM "), random access memory (Random Access Memory, referred to as " RAM "), magnetic disc or CD etc. it is each
Kind can store the medium of program code.
The specific embodiment of the above, only the application, but the protection domain of the application is not limited thereto, it is any
In the technical scope that those familiar with the art discloses in the application, various equivalent modifications can be readily occurred in or replaced
It changes, these modifications or substitutions should all cover within the protection domain of the application.Therefore, the protection domain of the application should be with right
It is required that protection domain subject to.
Claims (18)
- A kind of 1. method for transmitting low-density checksum LDPC code, which is characterized in that including：Obtain the modulation system that the code check of the first bit sequence to be sent and first bit sequence use；According to the modulation system that the code check of first bit sequence and first bit sequence use, after being encoded Reason, obtains the second bit sequence, and the coding post processing includes at least one of punching processing and interleaving treatment；Send second bit sequence.
- 2. the according to the method described in claim 1, it is characterized in that, modulation methods used according to first bit sequence Formula carries out coding post processing to first bit sequence, obtains the second bit sequence, including：If the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is small In predetermined threshold value, processing is interleaved to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is big In or equal to predetermined threshold value, punching processing is carried out to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses for low-order-modulated mode, beats the bit sequence to be sent Hole is handled, and obtains the second bit sequence.
- 3. the according to the method described in claim 2, it is characterized in that, modulation system used when first bit sequence During for low-order-modulated mode, punching processing is carried out to the bit sequence to be sent, obtains the second bit sequence, including：Punching processing, the target bits set and described first are carried out to the target bits set in first bit sequence It arranges the most heavy n row of weight in the check matrix of bit sequence to correspond to, wherein n is positive integer.
- 4. according to the method in claim 2 or 3, which is characterized in that the high-order modulating is quadrature amplitude modulation 16QAM or the modulation system than 16QAM higher order；The low-order-modulated mode is the modulation system used than 16QAM more low orders.
- 5. method according to any one of claim 2 to 4, which is characterized in that the predetermined threshold value is 2/3.
- A kind of 6. method for transmitting low-density checksum LDPC code, which is characterized in that including：The first bit sequence is received, wherein, first bit sequence is to carry out the bit sequence that coding post processing obtains, described Coding post processing includes at least one of punching processing and interleaving treatment；According to the modulation system that the code check of first bit sequence and first bit sequence use, processing is decoded, Obtain the second bit sequence.
- 7. the according to the method described in claim 6, it is characterized in that, code check according to first bit sequence and described The modulation system that first bit sequence uses, is decoded processing, obtains the second bit sequence, including：If the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is small In predetermined threshold value, processing and decoding are deinterleaved to first bit sequence, obtain the second bit sequence；If the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is big In or equal to predetermined threshold value, processing is decoded to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses for low-order-modulated mode, is decoded first bit sequence Processing, obtains the second bit sequence.
- 8. the method according to the description of claim 7 is characterized in that the high-order modulating is quadrature amplitude modulation 16QAM Or the modulation system than 16QAM higher order；The low-order-modulated mode is the modulation system used than 16QAM more low orders.
- 9. method according to claim 7 or 8, which is characterized in that the predetermined threshold value of the code check is 2/3.
- 10. a kind of network equipment, which is characterized in that including：Acquiring unit, shown acquiring unit are used to obtain the code check of the first bit sequence to be sent and first bit sequence The modulation system of use；Processing unit, the processing unit are used to be used according to the code check of first bit sequence and first bit sequence Modulation system, carry out coding post processing, obtain the second bit sequence, the coding post processing includes punching handle and intertexture at At least one of reason；Transmitting element, the transmitting element are used to send second bit sequence.
- 11. the network equipment according to claim 10, which is characterized in that the processing unit is specifically used for：If the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is small In predetermined threshold value, processing is interleaved to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is big In or equal to predetermined threshold value, punching processing is carried out to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses for low-order-modulated mode, beats the bit sequence to be sent Hole is handled, and obtains the second bit sequence.
- 12. the network equipment according to claim 11, which is characterized in that the processing unit is specifically used for：To described Target bits set in one bit sequence carries out punching processing, the target bits set and the school of first bit sequence It tests in matrix and arranges the most heavy n row correspondences of weight, wherein n is positive integer.
- 13. the network equipment according to claim 11 or 12, which is characterized in that the high-order modulating is orthogonal amplitude Modulate 16QAM or the modulation system than 16QAM higher order；The low-order-modulated mode is the modulation used than 16QAM more low orders Mode.
- 14. the network equipment according to any one of claim 10 to 13, which is characterized in that the predetermined threshold value of code check It is 2/3.
- 15. a kind of network equipment, which is characterized in that including：Receiving unit, the receiving unit are used to receive the first bit sequence, wherein, first bit sequence is is encoded Obtained bit sequence is post-processed, the coding post processing includes at least one of punching processing and interleaving treatment；Decoding unit, the decoding unit are used to be used according to the code check of first bit sequence and first bit sequence Modulation system, be decoded processing, obtain the second bit sequence.
- 16. the network equipment according to claim 15, which is characterized in that the decoding unit is specifically used for：If the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is small In predetermined threshold value, processing is interleaved to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses is high-order modulating, and the code check of first bit sequence is big In or equal to predetermined threshold value, punching processing is carried out to first bit sequence, obtains the second bit sequence；OrIf the modulation system that first bit sequence uses for low-order-modulated mode, beats the bit sequence to be sent Hole is handled, and obtains the second bit sequence.
- 17. the network equipment according to claim 16, which is characterized in that the high-order modulating is quadrature amplitude modulation 16QAM or more than the modulation system of 16QAM higher order；The low-order-modulated mode is the modulation methods used than 16QAM more low orders Formula.
- 18. the network equipment according to claim 16 or 17, which is characterized in that the predetermined threshold value of the code check is 2/3.
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