CN108231597A - Thin film transistor (TFT) and its manufacturing method, array substrate, display device - Google Patents
Thin film transistor (TFT) and its manufacturing method, array substrate, display device Download PDFInfo
- Publication number
- CN108231597A CN108231597A CN201810002456.XA CN201810002456A CN108231597A CN 108231597 A CN108231597 A CN 108231597A CN 201810002456 A CN201810002456 A CN 201810002456A CN 108231597 A CN108231597 A CN 108231597A
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode layer
- auxiliary electrode
- thin film
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 75
- 239000000758 substrate Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 94
- 239000010410 layer Substances 0.000 claims description 262
- 230000008569 process Effects 0.000 claims description 52
- 239000010408 film Substances 0.000 claims description 38
- 238000000059 patterning Methods 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000005611 electricity Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 17
- 239000011248 coating agent Substances 0.000 description 12
- 238000000576 coating method Methods 0.000 description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 238000007639 printing Methods 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 10
- 239000011265 semifinished product Substances 0.000 description 9
- 238000011161 development Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 6
- 229920001621 AMOLED Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000002520 cambial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000003431 cross linking reagent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000004925 denaturation Methods 0.000 description 1
- 230000036425 denaturation Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005816 glass manufacturing process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- FGIUAXJPYTZDNR-UHFFFAOYSA-N potassium nitrate Chemical compound [K+].[O-][N+]([O-])=O FGIUAXJPYTZDNR-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of thin film transistor (TFT) and its manufacturing method, including：Auxiliary electrode layer is formed on underlay substrate；By the use of the auxiliary electrode layer as mask plate, technique is patterned by back exposing and forms active layer, gate insulating layer and transparent grid electrode layer；Source-drain electrode layer is formed on the auxiliary electrode layer.The invention also discloses a kind of array substrate and display devices.Thin film transistor (TFT) proposed by the present invention and its manufacturing method, array substrate, display device can improve the electrology characteristic of thin film transistor (TFT), so as to improve display effect.
Description
Technical field
The present invention relates to display technology fields, particularly relate to a kind of thin film transistor (TFT) and its manufacturing method, array substrate, show
Showing device.
Background technology
Active matrix organic light-emitting diode (Active Matrix Organic Light Emitting Diode, letter
Claim AMOLED) display have actively shine, luminous efficiency height, contrast height, high resolution, low in energy consumption, colour gamut is wide, it is light, thin,
No angle limit, and luminescent material enriches, and easily realizes colored display；Fast response time, dynamic menu quality are high；Use temperature
Degree range is wide, shock resistance is strong；Flexible Displays can be achieved；Cost reduction space is huge to wait many advantages.Therefore AMOLED is in mesh
There is great potential in former world FPD industry.AMOLED display technologies are swift and violent in the development of past ten years, obtain
Great breakthrough.One of approach for realizing large scale displayer is to use active matrix thin film transistor
(Thin Film Transistor, abbreviation TFT) backboard.
For large scale OLED using oxide thin film transistor (abbreviation TFT) as backboard, TFT structure therein is main at present
There are 2 kinds：One kind is bottom gate (bottom gate) structure, including etching barrier layer (ESL), back of the body channel etching (BCE)；It is another
It is top-gated (top gate) structure.
But inventor is in the implementation of the present invention, it is found that the prior art has at least the following problems：
The source-drain electrode of bottom grating structure TFT and grid (gate) overlapping area are larger, are also easy to produce parasitic capacitance, and output is caused to be believed
Number delay and waveform distortions distortion, it is uneven to eventually lead to OLED display display.
Top gate structure is in order to control the size of leakage current, and there are lightly doped drain (Lightly between source-drain electrode and grid
Doped Drain, abbreviation LDD), parasitic capacitance is greatly reduced, reduces signal delay and distortion, improves display effect.But LDD
The active layer material (such as indium gallium zinc oxide, IGZO) in area needs to handle by ammonia (NH3) or high-temperature process, Cai Nengbao
Demonstrate,prove its high electric conductivity, but the technique of this IGZO conductors can introduce excessive hydrogen (H), the H in NH3 easily from LDD region to
It is spread in the IGZO of channel region, easily leads to the deterioration of TFT performances.
Invention content
In view of this, the first purpose of the embodiment of the present invention is to propose a kind of thin film transistor (TFT) and its manufacturing method, battle array
Row substrate, display device can improve the electrology characteristic of thin film transistor (TFT), so as to improve display effect.
Based on above-mentioned purpose, the first aspect of the embodiment of the present invention provides a kind of manufacturing method of thin film transistor (TFT),
Including：
Auxiliary electrode layer is formed on underlay substrate；
By the use of the auxiliary electrode layer as mask plate, it is exhausted that technique formation active layer, grid are patterned by back exposing
Edge layer and transparent grid electrode layer；
Source-drain electrode layer is formed on the auxiliary electrode layer.
Optionally, by the use of the auxiliary electrode layer as mask plate, by back exposing be patterned technique formed active layer,
Gate insulating layer and transparent grid electrode layer, including：
Semiconductive thin film, grid insulating film and transparent grid electrode film are formed on auxiliary electrode layer；
By the use of the auxiliary electrode layer as mask plate, by back exposing be patterned technique formation include transparent grid electrode,
The pattern of gate insulating layer and semiconductor regions.
Optionally, by the use of the auxiliary electrode layer as mask plate, technique is patterned by back exposing and is formed including saturating
The pattern of bright grid, gate insulating layer and semiconductor regions, including：
On the transparent grid electrode film, negative photoresist is coated；
The direction that the opposite face of the auxiliary electrode layer is formed from the underlay substrate is exposed, and utilizes the auxiliary
Electrode layer obtains the photoresist pattern layer consistent with required gate pattern as mask plate；
Using the photoresist pattern layer as resist layer, sequentially form including transparent grid electrode, gate insulating layer and semiconductor region
The pattern in domain.
Optionally, auxiliary electrode layer is formed on underlay substrate, including：
Buffer layer is formed on the underlay substrate；
Metallic film is formed on the buffer layer；
The metallic film includes the pattern of auxiliary electrode by a patterning processes formation.
Optionally, it after active layer is formed, further includes：
Form interlayer dielectric layer.
Optionally, it after interlayer dielectric layer is formed, further includes：
Via is formed in the interlayer dielectric layer, orthographic projection of the via on the underlay substrate is located at described auxiliary
It helps in orthographic projection of the electrode layer on the underlay substrate.
Optionally, source-drain electrode layer is formed on the auxiliary electrode layer, including：
It is formed after via in the interlayer dielectric layer, source and drain very thin films is formed on the interlayer dielectric layer；
The source and drain very thin films include the pattern of source-drain electrode by a patterning processes formation.
The second aspect of the embodiment of the present invention provides a kind of thin film transistor (TFT), including underlay substrate, active layer, grid
Pole insulating layer, transparent grid electrode layer, source-drain electrode layer and auxiliary electrode layer；
The auxiliary electrode layer is in contact with the active layer, and positive throwing of the source-drain electrode layer on the underlay substrate
Shadow is located among orthographic projection of the auxiliary electrode layer on the underlay substrate.
In terms of the third of the embodiment of the present invention, a kind of array substrate is provided, including foregoing thin film transistor (TFT).
4th aspect of the embodiment of the present invention, provides a kind of display device, including foregoing array substrate.
From the above it can be seen that thin film transistor (TFT) provided in an embodiment of the present invention and its manufacturing method, array substrate,
Display device manufactures transparent grid electrode layer, grid by setting auxiliary electrode layer, and using the auxiliary electrode layer by self-registered technology
Pole insulating layer and active layer, then source-drain electrode layer is formed on auxiliary electrode layer；On the one hand, nothing is realized using self-registered technology to cover
Film version process so as to save technique, on the other hand, is connect with active layer and source-drain electrode layer respectively by auxiliary electrode layer
The problem of touching, both ensure that the high conductivity of LDD region, in turn avoiding the overlapping caused higher Cgs of grid and other electrode districts,
It is final to ensure that thin film transistor (TFT) and corresponding array substrate and display device have preferable electrology characteristic.
Description of the drawings
Fig. 1 is the structure diagram of top gate type thin film transistor of the prior art；
Fig. 2 is the flow diagram of one embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention；
Fig. 3 is the flow diagram of another embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention；
Fig. 3 a are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, and buffering is formed on underlay substrate
Semi-finished product structure schematic diagram after layer；
Fig. 3 b are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, are formed after auxiliary electrode layer
Semi-finished product structure schematic diagram；
Fig. 3 c are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, are formed after semiconductive thin film
Semi-finished product structure schematic diagram；
Fig. 3 d are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, are formed after grid insulating film
Semi-finished product structure schematic diagram；
Fig. 3 e are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, are formed after transparent grid electrode film
Semi-finished product structure schematic diagram；
Fig. 3 f are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, are formed after photoresist pattern layer
Semi-finished product structure schematic diagram；
Fig. 3 g be thin film transistor (TFT) provided by the invention manufacturing method embodiment in, sequentially form transparent grid electrode layer,
Semi-finished product structure schematic diagram after gate insulating layer and active layer；
Fig. 3 h are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, remove the photoresist pattern layer
Semi-finished product structure schematic diagram later；
Fig. 3 i are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, form interlayer dielectric layer and via
Semi-finished product structure schematic diagram later；
Fig. 3 j are in the embodiment of the manufacturing method of thin film transistor (TFT) provided by the invention, form half after source-drain electrode layer
Finished product structure schematic diagram.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
It should be noted that all statements for using " first " and " second " are for differentiation two in the embodiment of the present invention
The non-equal entity of a same names or non-equal parameter, it is seen that " first " " second " should not only for the convenience of statement
The restriction to the embodiment of the present invention is interpreted as, subsequent embodiment no longer illustrates this one by one.
As shown in Figure 1, the structure diagram for top gate type thin film transistor of the prior art.
Top gate type thin film transistor of the prior art, it is exhausted including underlay substrate 10, buffer layer 11, active layer 12, grid
Edge layer 13, grid 14, interlayer dielectric layer 15 and source-drain electrode 16.
Wherein, grid and source-drain electrode no overlap, i.e. gate-source capacitance Cgs on TFT is almost 0, but in grid and source and drain
LDD region between pole only has IGZO, and the firing current Ion for easily leading to TFT is too low, it is therefore desirable to pass through NH3 processing or high temperature
Technique handles IGZO into column conductorization.And in actual experiment, the H in NH3 easily expands from LDD region into the IGZO of channel region
It dissipates or high-temperature technology easily leads to metal electrode oxidation.
To solve the above-mentioned problems, as the first purpose of the embodiment of the present invention, the first aspect of the embodiment of the present invention,
A kind of manufacturing method of thin film transistor (TFT) is provided, the electrology characteristic of thin film transistor (TFT) can be improved, so as to improve display effect.
As shown in Fig. 2, the flow diagram of one embodiment of manufacturing method for thin film transistor (TFT) provided by the invention.
The manufacturing method of the thin film transistor (TFT), including：
Step 201：Auxiliary electrode layer is formed on underlay substrate.
In some optional embodiments, the step 201 of auxiliary electrode is formed on underlay substrate, can also be further comprised
Following steps：
Buffer layer is formed on underlay substrate；
Auxiliary electrode layer is formed on the buffer layer；So as to form buffering between auxiliary electrode layer and underlay substrate
Layer, to be planarized to underlay substrate, meets the requirement of flat performance.
In some optional embodiments, auxiliary electrode layer is formed on the buffer layer, can also be further comprised following
Step：
Metallic film is formed on the buffer layer；Optionally, the metallic film is formed, usually has deposition, applies, splashes
It penetrates and waits various ways；
The metallic film includes the pattern of auxiliary electrode by a patterning processes formation.Classical mask (mask plate)
The patterning processes of process generally include the techniques such as photoresist coating, exposure, development, etching, photoresist lift off.Sometimes it is not required to
Want traditional patterning processes can pattern-making, for example utilize liftoff lift-off technology.In reality also exist without mask into
The situation of row composition, for example can be more other modes of composition such as printing, printing.Therefore, as long as can be formed required
The technique of pattern can be known as patterning processes in embodiments of the present invention, here, should not be limited to the patterning processes only
Using the patterning processes of classical mask processes.Step 202：By the use of the auxiliary electrode layer as mask plate, pass through back exposing
It is patterned technique and forms active layer, gate insulating layer and transparent grid electrode layer.
In some optional embodiments, by the use of the auxiliary electrode layer as mask plate, it is patterned by back exposing
Technique forms active layer, gate insulating layer and transparent grid electrode layer, can also further comprise the steps：
Semiconductive thin film, grid insulating film and transparent grid electrode film are formed on auxiliary electrode layer；
By the use of the auxiliary electrode layer as mask plate, by back exposing be patterned technique formation include transparent grid electrode,
The pattern of gate insulating layer and semiconductor regions.
The patterning processes of classical mask (mask plate) process generally include photoresist coating, exposure, development, etching, light
The techniques such as photoresist stripping.Do not need to sometimes traditional patterning processes can pattern-making, for example utilize liftoff lift-off technology.It is existing
Also there is a situation where to be patterned without mask in reality, for example can be more other modes of composition such as printing, printing.
Therefore, patterning processes can be known as in embodiments of the present invention as long as the technique of required pattern can be formed, here, should not
The patterning processes are limited to the patterning processes only with classical mask processes.
Grid line also sometimes is made simultaneously when making grid, in addition, according to specific technique or structure change, may be used also
Common pattern of electrodes can be formed while grid, grid line is formed.
In some optional embodiments, by the use of the auxiliary electrode layer as mask plate, it is patterned by back exposing
Technique forms the pattern for including transparent grid electrode, gate insulating layer and semiconductor regions, can also further comprise the steps：
On the transparent grid electrode film, negative photoresist is coated；
The direction that the opposite face of the auxiliary electrode layer is formed from the underlay substrate is exposed, and utilizes the auxiliary
Electrode layer obtains the photoresist pattern layer consistent with required gate pattern as mask plate；
Using the photoresist pattern layer as resist layer, sequentially form including transparent grid electrode, gate insulating layer and semiconductor region
The pattern in domain；So as to by self-registered technology, complete the making of transparent grid electrode layer, gate insulating layer and active layer so that should
Without using mask plate in step, technique and corresponding auxiliary tool are saved.
Step 203：Source-drain electrode layer is formed on the auxiliary electrode layer.
It subsequently is further continued for making other corresponding layers, you can complete the making of thin film transistor (TFT).
From above-described embodiment as can be seen that the manufacturing method of thin film transistor (TFT) provided in an embodiment of the present invention, passes through setting
Auxiliary electrode layer, and transparent grid electrode layer, gate insulating layer and active layer are manufactured by self-registered technology using the auxiliary electrode layer,
Source-drain electrode layer is formed on auxiliary electrode layer again；On the one hand, no mask plate process is realized using self-registered technology, so as to
Technique has been saved, on the other hand, has been contacted respectively with active layer and source-drain electrode layer by auxiliary electrode layer, both ensure that LDD region
High conductivity in turn avoids grid and the problem of overlapping caused higher Cgs, finally ensure that film crystal with other electrode districts
Pipe has preferable electrology characteristic.
In some optional embodiments, after active layer is formed, can also it further comprise the steps：
Form interlayer dielectric layer；To realize the electrical isolation between the layer of conductive energy, while there is the work of planarization
With.
In some optional embodiments, after interlayer layer of dielectric material is formed, can also it further comprise the steps：
Via is formed in the interlayer dielectric layer, orthographic projection of the via on the underlay substrate is located at described auxiliary
It helps in orthographic projection of the electrode layer on the underlay substrate；During so that being subsequently formed source-drain electrode layer, the source-drain electrode layer can lead to
It crosses between the via and the auxiliary electrode layer and forms preferable electrical contact.
In some optional embodiments, on the auxiliary electrode layer formed source-drain electrode layer, can also further comprise with
Lower step：
It is formed after via in the interlayer dielectric layer, source-drain electrode material layer is formed on the interlayer dielectric layer；
The source and drain very thin films include the pattern of source-drain electrode by a patterning processes formation；So that the source-drain electrode
Preferable electrical contact is formed between layer and the auxiliary electrode layer.
The patterning processes of classical mask (mask plate) process generally include photoresist coating, exposure, development, etching, light
The techniques such as photoresist stripping.Do not need to sometimes traditional patterning processes can pattern-making, for example utilize liftoff lift-off technology.It is existing
Also there is a situation where to be patterned without mask in reality, for example can be more other modes of composition such as printing, printing.
Therefore, patterning processes can be known as in embodiments of the present invention as long as the technique of required pattern can be formed, here, should not
The patterning processes are limited to the patterning processes only with classical mask processes.
The embodiment of the present invention additionally provides another embodiment of the manufacturing method of the thin film transistor (TFT).As shown in figure 3,
The flow diagram of another embodiment of the manufacturing method for thin film transistor (TFT) provided by the invention.
The manufacturing method of the thin film transistor (TFT), including：
Step 301：Refer to the attached drawing 3a forms buffer layer 41 on underlay substrate 40.
Optionally, the underlay substrate 40 is transparent substrates, and thickness is about 50-1000 μm, optionally, using the healthy and free from worry or rising sun
Nitre glass and other such as quartz glass making.
Optionally, using PECVD, (Plasma Enhanced Chemical Vapor Deposition, plasma increase
Extensive chemical vapour deposition process) method, deposit the buffer layer 41, the ingredient of the buffer layer 41 can be include SiOx and/or
The single-layer or multi-layer inorganic material of SiNx, thickness are about 300~500nm.
Step 302：Metallic film is formed on the buffer layer 41；The metallic film is formed by a patterning processes
Pattern including auxiliary electrode, i.e. auxiliary electrode layer 42, refer to the attached drawing 3b.
Optionally, the metallic film is formed, usually there are the various ways such as deposition, coating, sputtering.
The patterning processes of classical mask (mask plate) process generally include photoresist coating, exposure, development, etching, light
The techniques such as photoresist stripping.Do not need to sometimes traditional patterning processes can pattern-making, for example utilize liftoff lift-off technology.It is existing
Also there is a situation where to be patterned without mask in reality, for example can be more other modes of composition such as printing, printing.
Therefore, patterning processes can be known as in embodiments of the present invention as long as the technique of required pattern can be formed, here, should not
The patterning processes are limited to the patterning processes only with classical mask processes.
Optionally, using sputtering (sputter) equipment, the deposited metal film on buffer layer 41, then by photoetching work
Skill obtains required pattern (with the required corresponding pattern of gate shapes), is obtained using wet etching or dry carving technology required
The metal pattern of auxiliary electrode layer 42.
Step 303：Refer to the attached drawing 3c forms semiconductive thin film 43.Optionally, the semiconductive thin film 43 is formed, usually
There are the various ways such as deposition, coating, sputtering.
Optionally, using sputtering (sputter) equipment, deposition oxide is as the semiconductive thin film 43, the oxidation
Object can be one of amorphous oxides such as IGZO, ZnON, ITZO or two or more mixtures.
Step 304：Refer to the attached drawing 3d forms grid insulating film 44.Optionally, the grid insulating film 44 is formed,
Usually there are the various ways such as deposition, coating, sputtering.
Optionally, using CVD (Chemical Vapor Deposition, chemical vapour deposition technique) method, described in deposition
Grid insulating film 44；Further, it can also remove H excessive in the grid insulating film 44 by annealing process, make thin
Film is finer and close.
Step 305：Refer to the attached drawing 3e forms transparent grid electrode film 45.Optionally, the transparent grid electrode film 45 is formed,
Usually there are the various ways such as deposition, coating, sputtering.
Optionally, continue, using sputtering (sputter) equipment, it is thin that transparent grid electrode to be deposited on the grid insulating film 44
Film 45 (such as ITO, IZO), thickness are about 200-1000nm.
Step 306：Refer to the attached drawing 3f, after the transparent grid electrode film 45 is formed, in the transparent grid electrode film 45
Upper coating negative photoresist；Direction (such as Fig. 3 f of the opposite face of the auxiliary electrode layer 42 are formed from the underlay substrate 40
Middle arrow direction) it is exposed, by the use of auxiliary electrode layer 42 as mask plate, obtain consistent with required gate pattern
Photoresist pattern layer 46.
Optionally, the spin coating negative photoresist on the transparent grid electrode film 45, strictly controls light exposure, in underlay substrate
40 back sides are exposed, and define gate pattern, are ensured that semiconductive thin film 43 has with auxiliary electrode layer 42 and are adequately contacted.
Optionally, stringent control light exposure here, refers to accurately calculate light exposure, accurate management and control CD values (Critical
Dimension, critical size).Because in wet etching, during general material etch, etching liquid all can be from the boundary of photoresist inwards
Carve, all can be there are certain CD deviations (bias), and CD bias correspond to FICD-DICD (FICD, final critical size, Final
Inspection Critical Dimension；DICD, critical size after etching, Development Inspection
Critical Dimension).Negative photoresist is in exposure, because of the diffraction reason of mask plate (mask) edge-light, actual exposure
The area size of denaturation may be inconsistent with mask sizes, there are the difference of CD bias, it may be understood herein that for FICD-Mask
CD.And not of the same race or different content emulsion and crosslinking agent are added in different materials, material obtains under identical light exposure
CD values it is also different.Therefore saying and strictly control light exposure, the CD bias mainly exposed make up the CD bias of wet etching, this
Sample can guarantee that CD is consistent with mask values.Specific technological parameter can be designed according to actual conditions, not do special limit herein
System.
Step 307：Refer to the attached drawing 3g is resist layer with the photoresist pattern layer 46, sequentially form including transparent grid electrode,
The pattern of gate insulating layer and semiconductor regions, i.e., described transparent grid electrode layer 451, gate insulating layer 441 (GI layers of abbreviation) and have
Active layer 431.Grid line also sometimes is made simultaneously when making grid, in addition, according to specific technique or structure change, may be used also
Common pattern of electrodes can be formed while grid, grid line is formed.
Optionally, it is resist layer with the photoresist pattern layer 46, the figure of transparent grid electrode layer 451 is obtained by wet-etching technique
Case；Retain photoresist pattern layer 46 not remove, continue with the photoresist pattern layer 46 as resist layer, dry etching goes out gate insulating layer
441 pattern is further continued for the photoresist pattern layer 46 as resist layer, and wet etching goes out the pattern of active layer 431, control etching slope
Angle is spent, ensures that transparent grid electrode layer 451 is small as possible with the overlapping region of auxiliary electrode layer 42.
The patterning processes of classical mask (mask plate) process generally include photoresist coating, exposure, development, etching, light
The techniques such as photoresist stripping.It is formed although being given in the present embodiment using the patterning processes of classical mask (mask plate) process
The embodiment of bright grid layer 451, gate insulating layer 441 (GI layers of abbreviation) and active layer 431, still, does not need to sometimes pass
The patterning processes of system can pattern-making, for example utilize liftoff lift-off technology.Also exist in reality and carry out structure without mask
The situation of figure, for example can be more other modes of composition such as printing, printing.Therefore, as long as required pattern can be formed
Technique can be known as patterning processes in embodiments of the present invention, here, the patterning processes should not be limited to only with
The patterning processes of classical mask processes.
Step 308：Refer to the attached drawing 3h removes the photoresist pattern layer 46.
Optionally, using the photoresist on dedicated 451 surface of stripping (strip) liquid removal grid of negative photoresist.
Step 309：Refer to the attached drawing 3i forms interlayer dielectric layer 47 (ILD)；Via is formed in the interlayer dielectric layer 47
48, orthographic projection of the via 48 on the underlay substrate 40 is located at the auxiliary electrode layer 42 on the underlay substrate 40
Orthographic projection in.Optionally, the interlayer dielectric layer 47 is formed, usually there are the various ways such as deposition, coating, sputtering.
Optionally, using PECVD methods, the interlayer dielectric layer 47 is deposited, ingredient can be SiNx, SiOx or SiOxNy
One or more of it is overlapping form, thickness is about 100~500nm, and interlayer dielectric layer 47 is obtained by a patterning processes
The pattern of via 48, the via 48 are used to connect source-drain electrode layer 49 and auxiliary electrode layer 42, then by auxiliary electrode layer 42 with having
Active layer 431 is attached.
Step 310：Refer to the attached drawing 3j is formed in the interlayer dielectric layer 47 after via 48, forms source and drain very thin films；
The source and drain very thin films include the pattern of source-drain electrode, i.e., described source-drain electrode layer 49 by a patterning processes formation.Optionally, shape
Into the source and drain very thin films, usually there are the various ways such as deposition, coating, sputtering.
Optionally, using sputtering (sputter) equipment, source-drain electrode film is deposited on the interlayer dielectric layer 47, is passed through
Photoetching process obtains required pattern, and the pattern of required source-drain electrode layer 49 is obtained using wet-etching technique.
Step 311：Other layers are formed, complete the making of thin film transistor (TFT).
From above-described embodiment as can be seen that the manufacturing method of thin film transistor (TFT) provided in an embodiment of the present invention, by using
Metal pattern forms auxiliary electrode layer on the buffer layer, then proceedes to form semiconductive thin film, grid insulating film, transparent grid
Very thin films, then using negative photoresist, using auxiliary electrode layer as mask (mask), by self-registered technology in substrate base
Back is exposed, and it is overlapping that control light exposure ensures that auxiliary electrode and grid are reduced, but ensure simultaneously auxiliary electrode with it is active
The good electric conductivity of layer carries out additional conductive eventually by the auxiliary electrode of bottom, both ensure that the height electricity of the LDD region of active layer
Conductance in turn avoids grid and the problem of overlapping caused higher Cgs, it is preferable finally to ensure that TFT has with other electrode districts
Electrology characteristic.
To solve the above-mentioned problems, as the first purpose of the embodiment of the present invention, the second aspect of the embodiment of the present invention,
A kind of thin film transistor (TFT) is provided, there is improved electrology characteristic, so as to improve display effect.
With reference to attached drawing 3j, the thin film transistor (TFT), including underlay substrate 40, active layer 431, gate insulating layer 441, transparent
Grid layer 451, source-drain electrode layer 19 and auxiliary electrode layer 42；
The auxiliary electrode layer 42 is in contact with the active layer 431, and the source-drain electrode layer 49 is in the underlay substrate
Orthographic projection on 40 is located among orthographic projection of the auxiliary electrode layer 42 on the underlay substrate 10.
From above-described embodiment as can be seen that thin film transistor (TFT) provided in an embodiment of the present invention, by setting auxiliary electrode, makes
It obtains auxiliary electrode to contact with active area and source-drain electrode respectively, both ensure that the high conductivity of LDD region, in turn avoided grid and other
The problem of overlapping caused higher Cgs of electrode district, finally ensure that thin film transistor (TFT) has preferable electrology characteristic.
In some optional embodiments, the thin film transistor (TFT) further includes buffer layer 41, and the buffer layer is arranged on institute
It states between underlay substrate 40 and auxiliary electrode layer 42；So as to be planarized using the buffer layer to underlay substrate, meet flat
The requirement of smooth performance.
In some optional embodiments, the thin film transistor (TFT) further includes interlayer dielectric layer 47, the interlayer dielectric layer
47 are arranged between the source-drain electrode layer 49 and the auxiliary electrode layer 42, to realize the electricity between the layer of conductive energy absolutely
Edge, while there is planarization.
To solve the above-mentioned problems, as the first purpose of the embodiment of the present invention, in terms of the third of the embodiment of the present invention,
A kind of array substrate is provided, there is improved electrology characteristic, display effect can be improved.
The array substrate, including foregoing thin film transistor (TFT).
From above-described embodiment as can be seen that array substrate provided in an embodiment of the present invention, thin film transistor (TFT) therein pass through
Auxiliary electrode is set so that auxiliary electrode contacts respectively with active area and source-drain electrode, not only ensure that the high conductivity of LDD region, but also
It is preferable finally to ensure that thin film transistor (TFT) has for the problem of avoiding the overlapping caused higher Cgs of grid and other electrode districts
Electrology characteristic.
To solve the above-mentioned problems, as the first purpose of the embodiment of the present invention, the 4th aspect of the embodiment of the present invention,
A kind of display device is provided, there is improved electrology characteristic, display effect can be improved.
The display device, including array substrate as described above.
From above-described embodiment as can be seen that display device provided in an embodiment of the present invention, thin film transistor (TFT) therein pass through
Auxiliary electrode is set so that auxiliary electrode contacts respectively with active area and source-drain electrode, not only ensure that the high conductivity of LDD region, but also
It is preferable finally to ensure that thin film transistor (TFT) has for the problem of avoiding the overlapping caused higher Cgs of grid and other electrode districts
Electrology characteristic.
It should be noted that the display device in the various embodiments described above can be：Electronic Paper, mobile phone, tablet computer, TV
Any product or component with display function such as machine, laptop, Digital Frame, navigator.
It should be noted that cambial operation in the various embodiments described above, includes but are not limited to (chemical phase, physics phase)
Deposition film forming, (magnetic control) spatter film forming, and it will be understood by those skilled in the art that after each layer is formed, it can basis
It needs to be further formed corresponding pattern on it, the present invention repeats no more this.
Technical scheme of the present invention is described in detail above in association with attached drawing, it is contemplated that in the prior art, source-drain electrode and active
Layer is in different layers so that substrate thickness is larger, complex manufacturing technology.It, can be by nitrogen by the technical solution of the application
Change copper and be doped processing, source electrode, drain electrode, data line and active layer are prepared within the same layer, so as to reduce array substrate
Thickness simplifies the manufacture craft of array substrate.
It should be pointed out that in the accompanying drawings, for the clear size that may be exaggerated layer and region of diagram.It and can be with
Understand, when element or layer be referred to as another element or layer " on " when, it directly in other elements or can may have
Intermediate layer.Additionally, it is appreciated that when element or layer be referred to as another element or layer " under " when, it can be directly at other
Under element or there may be the layer or element of more than one centre.In addition, it is to be appreciated that when layer or element are referred to as
Two layers or two elements " between " when, layer or there may also be one that it can be only between two layers or two elements
Above middle layer or element.Similar reference marker indicates similar element in the whole text.
In the present invention, term " first ", " second ", " third ", " the 4th " are only used for description purpose, and it is not intended that
Instruction implies relative importance.Term " multiple " refers to two or more, unless otherwise restricted clearly.
Those of ordinary skills in the art should understand that：The above is only a specific embodiment of the present invention, and
The limitation present invention is not used in, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done,
It should be included within protection scope of the present invention.
Claims (10)
1. a kind of manufacturing method of thin film transistor (TFT), which is characterized in that including：
Auxiliary electrode layer is formed on underlay substrate；
By the use of the auxiliary electrode layer as mask plate, technique is patterned by back exposing and forms active layer, gate insulating layer
With transparent grid electrode layer；
Source-drain electrode layer is formed on the auxiliary electrode layer.
2. according to the method described in claim 1, it is characterized in that, by the use of the auxiliary electrode layer as mask plate, pass through the back of the body
Exposure is patterned technique and forms active layer, gate insulating layer and transparent grid electrode layer, including：
Semiconductive thin film, grid insulating film and transparent grid electrode film are formed on auxiliary electrode layer；
By the use of the auxiliary electrode layer as mask plate, technique formation is patterned by back exposing and includes transparent grid electrode, grid
The pattern of insulating layer and semiconductor regions.
3. according to the method described in claim 2, it is characterized in that, by the use of the auxiliary electrode layer as mask plate, pass through the back of the body
Exposure is patterned the pattern that technique formation includes transparent grid electrode, gate insulating layer and semiconductor regions, including：
On the transparent grid electrode film, negative photoresist is coated；
The direction that the opposite face of the auxiliary electrode layer is formed from the underlay substrate is exposed, and utilizes the auxiliary electrode
Layer obtains the photoresist pattern layer consistent with required gate pattern as mask plate；
Using the photoresist pattern layer as resist layer, sequentially form including transparent grid electrode, gate insulating layer and semiconductor regions
Pattern.
4. according to the method described in claim 1, it is characterized in that, form auxiliary electrode layer on underlay substrate, including：
Buffer layer is formed on the underlay substrate；
Metallic film is formed on the buffer layer；
The metallic film includes the pattern of auxiliary electrode by a patterning processes formation.
5. according to the method described in claim 1, it is characterized in that, after active layer is formed, further include：
Form interlayer dielectric layer.
6. according to the method described in claim 5, it is characterized in that, after interlayer dielectric layer is formed, further include：
Via is formed in the interlayer dielectric layer, orthographic projection of the via on the underlay substrate is located at the auxiliary electricity
In orthographic projection of the pole layer on the underlay substrate.
7. according to the method described in claim 6, it is characterized in that, on the auxiliary electrode layer formed source-drain electrode layer, including：
It is formed after via in the interlayer dielectric layer, source and drain very thin films is formed on the interlayer dielectric layer；
The source and drain very thin films include the pattern of source-drain electrode by a patterning processes formation.
8. a kind of thin film transistor (TFT), which is characterized in that including underlay substrate, active layer, gate insulating layer, transparent grid electrode layer, source
Drain electrode layer and auxiliary electrode layer；
The auxiliary electrode layer is in contact with the active layer, and orthographic projection position of the source-drain electrode layer on the underlay substrate
Among orthographic projection of the auxiliary electrode layer on the underlay substrate.
9. a kind of array substrate, which is characterized in that including thin film transistor (TFT) as claimed in claim 8.
10. a kind of display device, which is characterized in that including array substrate as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810002456.XA CN108231597A (en) | 2018-01-02 | 2018-01-02 | Thin film transistor (TFT) and its manufacturing method, array substrate, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810002456.XA CN108231597A (en) | 2018-01-02 | 2018-01-02 | Thin film transistor (TFT) and its manufacturing method, array substrate, display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108231597A true CN108231597A (en) | 2018-06-29 |
Family
ID=62642540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810002456.XA Pending CN108231597A (en) | 2018-01-02 | 2018-01-02 | Thin film transistor (TFT) and its manufacturing method, array substrate, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108231597A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225363A (en) * | 1988-03-04 | 1989-09-08 | Nec Corp | Thin-film transistor and its manufacture |
| CN101488459A (en) * | 2009-02-13 | 2009-07-22 | 北京大学深圳研究生院 | Production method for self-aligned metallic oxide thin-film transistor |
| CN106935660A (en) * | 2017-05-12 | 2017-07-07 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
-
2018
- 2018-01-02 CN CN201810002456.XA patent/CN108231597A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225363A (en) * | 1988-03-04 | 1989-09-08 | Nec Corp | Thin-film transistor and its manufacture |
| CN101488459A (en) * | 2009-02-13 | 2009-07-22 | 北京大学深圳研究生院 | Production method for self-aligned metallic oxide thin-film transistor |
| CN106935660A (en) * | 2017-05-12 | 2017-07-07 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10367073B2 (en) | Thin film transistor (TFT) with structured gate insulator | |
| CN106158978B (en) | Thin film transistor (TFT), array substrate and preparation method thereof | |
| US10707236B2 (en) | Array substrate, manufacturing method therefor and display device | |
| CN107204309B (en) | The production method and its structure of dual gate metal oxide semiconductor TFT substrate | |
| CN103872060B (en) | Array base palte and manufacture method thereof | |
| US20150214249A1 (en) | Array Substrate, Display Device and Manufacturing Method | |
| US9716108B2 (en) | Thin film transistor and fabrication method thereof, array substrate, and display device | |
| CN110010626B (en) | Display substrate, manufacturing method thereof and display device | |
| CN104332477A (en) | Thin film transistor component, array substrate, method for manufacturing array substrate and display device comprising array substrate | |
| WO2016165186A1 (en) | Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate | |
| CN104600083B (en) | Thin-film transistor array base-plate and preparation method thereof, display panel and display device | |
| US9842915B2 (en) | Array substrate for liquid crystal display device and method of manufacturing the same | |
| CN102646632A (en) | Array substrate, manufacturing method thereof and display device | |
| WO2018040608A1 (en) | Oxide thin-film transistor and preparation method therefor, array substrate, and display device | |
| CN103165471A (en) | Thin film transistor and manufacture method and display device thereof | |
| CN104900654A (en) | Preparation method and structure of double-grid oxide semiconductor TFT substrate | |
| WO2017008345A1 (en) | Thin-film transistor, manufacturing method for thin-film transistor, and display device | |
| US20160247823A1 (en) | Ltps tft array substrate, its manufacturing method, and display device | |
| CN107516661B (en) | Display substrate, display device and manufacturing method of display substrate | |
| CN106876481B (en) | Oxide thin film transistor, manufacturing method thereof, array substrate and display device | |
| US20140080254A1 (en) | Fabricating Method Of Thin Film Transistor, Fabricating Method Of Array Substrate And Display Device | |
| WO2015096307A1 (en) | Oxide thin-film transistor, display device and manufacturing method for array substrate | |
| US10205029B2 (en) | Thin film transistor, manufacturing method thereof, and display device | |
| US10134765B2 (en) | Oxide semiconductor TFT array substrate and method for manufacturing the same | |
| CN102629589B (en) | Array substrate and manufacturing method thereof, and display apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180629 |
|
| RJ01 | Rejection of invention patent application after publication |