CN108228075A - The method and apparatus for accessing memory - Google Patents
The method and apparatus for accessing memory Download PDFInfo
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- CN108228075A CN108228075A CN201611131828.6A CN201611131828A CN108228075A CN 108228075 A CN108228075 A CN 108228075A CN 201611131828 A CN201611131828 A CN 201611131828A CN 108228075 A CN108228075 A CN 108228075A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The application provides a kind of method for accessing memory, including：The order is sent out to the memory；After set time interval, the implementing result of the order is inquired, to obtain query result, wherein set time interval represents to be issued to the time interval for proceeding by the inquiry from the order.The technical solution of the application can at least reduce the occupancy to flash memory channel, promote solid state disk performance, and reduce the power consumption of solid state disk.
Description
Technical field
This application involves storage device fields, and NVM chips are operated more particularly, to by the command interface of NVM chips
Method and apparatus.
Background technology
Fig. 1 is the block diagram of the solid storage device of the prior art.Solid storage device 102 is coupled with host, for for
Host provides storage capacity.Host can be coupled in several ways between solid storage device 102, coupled modes include but
Be not limited by such as SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment),
SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached
SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated drive electronics), USB
(Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect
Express, PCIe, peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical fiber leads to
Road, cordless communication network etc. connect host and solid storage device 102.Host can be set through the above way with storage
The standby information processing equipment communicated, for example, personal computer, tablet computer, server, portable computer, network exchange
Machine, router, cellular phone, personal digital assistant etc..Storage device 102 includes interface 103, control unit 104, one or more
A NVM chips 105 and DRAM (Dynamic Random Access Memory, dynamic RAM) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistance-change memory
Device) etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 passes for data of the control between interface 103, NVM chips 105 and firmware memory 110
It is defeated, it is additionally operable to storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..Control unit
104 can be realized by the various ways of software, hardware, firmware or combination, for example, control unit 104 can be FPGA
(Field-programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form；Control unit 104 can also include place
Device or controller are managed, software is performed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders；Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110；
DRAM can store the data of the I/O command of FTL tables and/or caching.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), dodges
It deposits interface controller and is coupled to NVM chips 105, and sent out in a manner of following the interface protocol of NVM chips 105 to NVM chips 105
Go out order, to operate NVM chips 105, and receive the command execution results exported from NVM chips 105.Known NVM chips connect
Mouth agreement includes " Toggle ", " ONFI " etc..
The order such as reading, programming, erasing is provided in the interface protocol of NVM chips 105 and (also referred to as accesses NVM chips
Order), each order have the respective execution time.After NVM chips 105 send out order, based on command type, predetermined
Time after by the status registers (such as SR registers) of inquiry/poll NVM chips 105, be with the execution for knowing order
It is no to complete and whether succeed.
Invention content
It finds under study for action, even for the order of the access NVM chips of same type, the execution time may also can be sent out
Changing.If according to the parameter setting time window that NVM chip products handbook provides, in the order for sending out access NVM chips
In specified time window afterwards may constantly querying command implementing result, thus increase to coupling NVM chips and control unit
The occupancy of the flash memory channel of part 104, so as to reduce the performance of solid state disk, increases power consumption.
The purpose of the application is, by improving the inquiry mechanism of command execution results, reduces the occupancy to flash memory channel,
Solid state disk performance is promoted, and reduces the power consumption of solid state disk.
According to the first aspect of the invention, the first method of access memory according to a first aspect of the present invention, packet are provided
It includes：The order is sent out to the memory；After set time interval, the implementing result of the order is inquired, with
Query result is obtained, wherein set time interval represents to be issued between the time for proceeding by the inquiry from the order
Every.
The first method of access memory according to a first aspect of the present invention, provides a kind of second party for accessing memory
Method, wherein, the order is the erasing order for the memory, and the inquiry is carried out by performing read states order.
The first or second method of access memory according to a first aspect of the present invention provides a kind of access memory
Third method, wherein, the time interval is set according to PE number of the accessed storage unit of the order.
The first of access memory according to a first aspect of the present invention provides one of to third method and a kind of accesses storage
The fourth method of device, wherein, the time interval be according to the range of PE number of the accessed storage unit of the order come
Setting.
One of first to fourth method of access memory according to a first aspect of the present invention provides a kind of access and stores
5th method of device, wherein, the time interval t is set according to following equation：T=a+b*f (x), wherein, described in x expressions
PE number of the accessed storage unit of order, a is the coefficient specified, and b is the coefficient specified.
5th method of access memory according to a first aspect of the present invention, provides a kind of the 6th side for accessing memory
Method, wherein, f (x)=xk, values of the wherein k between 0-1.
5th method of access memory according to a first aspect of the present invention, provides a kind of the 7th side for accessing memory
Method, wherein, f (x)=logmX, wherein m>1.
One of the 5th to the 7th method of access memory according to a first aspect of the present invention provides a kind of access and stores
The eighth method of device, wherein, the current time interval t is set according to following equation1：t1=t0+(b*f(x1)-b*f
(x0)), wherein, x0Represent the accessed storage unit of the order in t0The PE number at moment, x1Represent that the order is accessed
Storage unit in t1The PE number at moment, b are the coefficient specified.
6th method of access memory according to a first aspect of the present invention, provides a kind of the 9th side for accessing memory
Method, wherein, k is 1/2 or 1/3.
The first method of access memory according to a first aspect of the present invention, provides a kind of the tenth side for accessing memory
Method, wherein, the order is the program command for the memory, and the inquiry is carried out by performing read states order.
Tenth method of access memory according to a first aspect of the present invention provides the 11st of a kind of access memory
Method, wherein, the time interval is set according to the program command data volume to be written.
The first method of access memory according to a first aspect of the present invention provides the 12nd of a kind of access memory
Method, wherein, the order is the read command for the memory, and the inquiry is carried out by performing read states order
12nd method of access memory according to a first aspect of the present invention provides the tenth of a kind of access memory
Three methods, wherein, the time interval is set according to the read command data volume to be read.
One of first to the 13rd method of access memory according to a first aspect of the present invention provides a kind of access and deposits
14th method of reservoir, further comprises：If the query result shows that the memory is in " busy " state, again
Implementing result of the order on the memory is inquired, until the memory is in " ready " state.
One of first to the 13rd method of access memory according to a first aspect of the present invention provides a kind of access and deposits
15th method of reservoir, further comprises：If the query result shows that the memory is in " busy " state,
Implementing result of the order on the memory is inquired after one specified time interval again, until the memory is in
" ready " state.
One of first to the 13rd method of access memory according to a first aspect of the present invention provides a kind of access and deposits
16th method of reservoir, further comprises：If after specified maximum time interval, the query result shows described
Memory is in " busy " state, then sends out indicating fault.
One of first to the 16th method of access memory according to a first aspect of the present invention provides a kind of access and deposits
17th method of reservoir, wherein, if in high performance mode, will be described between be set to the first value；And if
In low-power consumption mode, then the time interval is set as second value；Wherein foundation is sent to from order and is deposited what is accessed
Storage unit indicates that order performs minimum value the first value of setting for the time interval completed to the storage unit；It is sent out according to from order
It gives and indicates that order performs the average value setting for the time interval completed in the storage unit accessed to the storage unit
Two-value.
17th method of access memory according to a first aspect of the present invention provides the tenth of a kind of access memory
All directions method, wherein, according to from order be sent to its PE times number accessed belong to the storage units of specified PE numbers ranges to
The minimum value that the storage unit instruction order performs the time interval completed sets the first value；Foundation is sent to from order in institute
Its PE time number accessed belong to the storage units of specified PE numbers ranges to storage unit instruction order execution completion when
Between be spaced average value setting second value.
According to a second aspect of the present invention, a kind of storage control is provided, including：One or more processor；One or
Multiple memories；And the program in the memory is stored in, it is described when being performed by one or more of processors
Program makes the controller perform method as described above.
According to a third aspect of the present invention, a kind of be used for ordering what implementing result on a memory inquired to set is provided
It is standby, including：For sending out the device of the order to the memory；For after set time interval, inquiring institute
The implementing result of order is stated, to obtain the device of query result, wherein set time interval represents to send out from the order
To the time interval for proceeding by the inquiry.
According to the fourth aspect of the invention, a kind of computer readable storage medium, the computer-readable storage medium are provided
Matter has program stored therein, when described program is performed by an equipment so that the equipment performs methods described above.
The technical solution of the application can at least reduce the occupancy to flash memory channel, promote solid state disk performance, and reduce
The power consumption of solid state disk.
Description of the drawings
Fig. 1 illustrates the block diagram of the storage device of the prior art；
Fig. 2 illustrates the block diagram of the control unit of storage device according to embodiments of the present invention；
Fig. 3 is the sequence diagram for the erasing order for accessing NVM chips；
Fig. 4 is the sequence diagram for the read states order for accessing NVM chips；
Fig. 5 is the method being used for implementing result on a memory is ordered to be inquired according to embodiments of the present invention
Flow chart；
Fig. 6 is from the time graph for sending out erasing order to SR registers instruction " ready " state；
Fig. 7 is the flow chart according to the execution erasing order of further embodiment of this invention；
Fig. 8 is the sequence diagram for the program command for accessing NVM chips；
Fig. 9 is the flow chart according to another embodiment of the present invention for performing read command；And
Figure 10 is the flow chart that control unit according to embodiments of the present invention performs read command.
Specific embodiment
The specific embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.It is to be appreciated that in the disclosure
" first ", " second " are only used for instruction object, and are not limited to quantity and/or sequence.
Fig. 2 illustrates the block diagram of the control unit of storage device according to embodiments of the present invention.Control unit 104 includes master
Machine interface 210, front end processing block 220, flash memory management module 230 and back end processing module 240.
Host interface 210 is used for host exchange command and data.In one example, host passes through with storage device
NVMe/PCIe protocol communications, host interface 210 handle PCIe protocol data packet, extract NVMe protocol commands, and return to host
Return the handling result of NVMe protocol commands.The logical address of flash memory visit order is converted to physical address by FTL modules 230, and
Flash memory is implemented to manage, the services such as abrasion equilibrium, garbage reclamation are provided.Back end processing module 240 accesses one according to physical address
A or multiple NVM chips.Processing before FTL is accessed is known as front-end processing, and the processing after FTL is accessed is known as
Back-end processing.Front-end control component 104 is additionally coupled to external memory (for example, RAM) 260.The segment space quilt of memory 260
As front end caching (front end caching 265), front end processing block 220 may have access to memory 260 front end to be used to cache.It is optional
Ground provides front end cache module 225 as front end caching in control unit 104.
The present invention describes technical scheme of the present invention by taking erasing order and program command as an example.When order is for storage
When the erasing order or program command of device, erasing order or program command can be inquired by performing read states order
Execution state or result.By sending out read states order to NVM chips, the state of the NVM chips is known.If to NVM chips
Program command or erasing order have not carried out and finish, then can know that the NVM chips are in " busy " state, if to NVM cores
The program command of piece or erasing order executed finish, then can know that the NVM chips are in " ready " state.
Embodiment 1
Fig. 3 is the sequence diagram for the erasing order for accessing NVM chips.In figure 3, it is from left to right time passage direction.DQ
Indicate one or more DQ pins of NVM chips, the state performed in response to erasing order of SR instruction NVM chips (is posted by SR
Indicated by the value of storage).To send out erasing order, control unit 104 (referring to Fig. 1 and Fig. 2) on the DQ pins of NVM chips according to
It is secondary to generate " order 1 ", one or more instructions by " address " (being 3 addresses shown in Fig. 3) and " order 2 " of erasable block.Make
For response, NVM chips carry out the block of specified address erasable.After the t1 moment, " SR " register becomes the state of " doing ", and instruction is wiped
Division operation is carrying out；And the t2 moment after the completion of erasable, the correspondence position of " SR " register become " ready " state.Send out wiping
After order, control unit 104 inquires SR registers, is " ready " state in response to SR registers, and control unit 104 knows to wipe
Except order has been completed.
Fig. 4 is the sequence diagram for the read states order for accessing NVM chips.
In Fig. 4, to send out read states order, control unit 104 (referring to Fig. 1) on the DQ pins of NVM chips successively
Generate " order 3 ", one or more optional " address " (being in Fig. 43 addresses).When the one or more optional addresses of offer
When, optional address is used to refer to tube core (DIE), logic unit (LUN) and/or the target (Target) of NVM chips.As sound
Should, after the shorter predetermined time, NVM chips export on DQ pins one or more data, be used to indicate NVM chips (or
Tube core, logic unit, target) on as the order execution state indicated by the value of SR registers.Thus, together with Fig. 3, controlling
Component 104 is after NVM chips send out erasing order, by sending out read states order to NVM chips repeatedly, to know erasing order
Implementing result.
Read states order read memory state when, relative to sent out order (such as erasing order, programming order
Order or read command) between, need suitable time interval.Be spaced it is too long, then can lead to not in time obtain NVM state；
Interval is too short, then can repeatedly reading state, cause channel occupied, system performance reduces.
Fig. 5 is the method being used for implementing result on a memory is ordered to be inquired according to embodiments of the present invention
Flow chart.It, can be in the later inquiry at reasonable time interval after order is sent out (such as erasing order as shown in Figure 3)
The implementing result of order.
As shown in figure 5, in step S510, control module 104 (referring to Fig. 1) sends out erasing order or programming to NVM chips
Order.Next, after set time interval, by sending out read states order to NVM chips come query steps S510
In the implementing result (S520) of the program command that sends out or erasing order.If " SR " register indicates " busy " state, show step
The program command sent out in S510 or the execution of erasing order are not yet completed, after being at the appointed time spaced (t2), control module 104
Read states order is sent out to NVM chips again, until reading " SR " register instruction " ready " state, shows step S510
In the execution of the program command that sends out or erasing order completed.
Embodiment 2
The setting of time interval depends on Multiple factors.From erasing order is sent out to SR when applicant is to accessing NVM chips
The time of register instruction " ready " state is studied, and illustrate result of study in figure 6.
Fig. 6 is from the time graph for sending out erasing order to SR registers instruction " ready " state.During the longitudinal axis instruction of Fig. 6
Between, and the number being wiped free of of the physical block of command access is wiped free of in horizontal axis instruction NVM chips.In figure 6, it is every in solid line
The instruction of a point is when specifying PE number (Program-Erase Counts), to the erasing operation of multiple physical blocks of NVM chips,
From send out erasing order to SR registers instruction erasing order complete time average value；By putting each of formed dotted line
Point instruction, to multiple pieces of erasing operation of NVM chips, is indicated when specified PE times several from erasing order is sent out to SR registers
The maximum value for the time that erasing order is completed；And each point for the dotted line being made of strigula is indicated when specified PE times is several,
To multiple pieces of erasing operation of NVM chips, from erasing order is sent out to the time of SR registers instruction erasing order completion
Minimum value.
It can be appreciated that with PE number increase, NVM chips gradually increase the response time of erasing order from Fig. 6.
Further, NVM chips are segmented the maximum/minimum of erasing order response time relative to the value of PE number.Example
Such as, referring to Fig. 6, when PE number is 0-500 times, the maximum value to the erasing order response time is t3, is 0- in PE number
At 1000 times, the minimum value to the erasing order response time is t4, and when PE number is 500-1500 times, erasing order is responded
The maximum value of time is t5, and when PE number is 1000-3000 times, the minimum value to the erasing order response time is t6.And
And in the case where identical PE times is several, NVM chips are not definite value to the response time of erasing order, but in certain maximum/minimum
In the range of fluctuate.And the average value of the response time of erasing order with PE number is increased and is gradually increased.
It is understood that Fig. 6 and its relevant description are specifically counted only merely for the purpose of signal and citing in Fig. 6
According to can be different according to different application scenarios, those skilled in the art should not be described according to above-mentioned example and by this Shen
The scope limitation that please be claimed is in above specific example.
Foundation Fig. 6, in one embodiment according to the present invention, wherein, after NVM chips send out erasing order, look into
PE times of the physical block number being accessed according to erasing order of time interval of erasing order is ask to determine.From Fig. 6 it can be seen that with
Increasing for PE number, NVM chips also gradually increase the response time of erasing order.Therefore correspondingly, when to higher
PE number physical block send out erasing order after, send out read states order to NVM chips again behind longer time interval, and
After the physical block with relatively low PE number sends out erasing order, read states are sent out to NVM chips after shorter time interval
Order.
In another embodiment, corresponding time interval is dynamically selected according to PE number.
According to another implementation of the invention, which can be according to the physical block that erasing order is accessed
The range of PE number is set so that after erasing order is sent out to physical block of the PE number in particular range, with this
Read states order is sent out after the corresponding time interval of particular range of PE number.
Referring to Fig. 6, time interval is arranged on same PE shown in fig. 6 by still another embodiment according to the present invention
Between the corresponding maximum value of number and minimum value.
According to embodiment of the present invention, according to following equation (1) come the t that sets interval：
T=a+b*f (x) (1)
Wherein, x represents to order PE number of accessed storage unit, and a is the coefficient specified, and b is the coefficient specified, f
(x) function of x is represented.Wherein, a and b can be by one of ordinary skill in the art by inquiring NVM chip handbooks, testing or dividing
It analyses to obtain.
Time interval is set as the average value of maximum value and minimum value by a kind of embodiment according to the present invention.To Fig. 6
The average value indicated by solid line shown is fitted, it can be found that the average value conforms generally to t=a+b*xkFunction, i.e. f
(x)=xk.Values of the wherein k between 0-1, preferably k are 1/2 or 1/3.
According to another implementation of the invention, f (x) can also be logarithmic function, such as f (x)=logmX, wherein
m>1.Preferably, logmX can be natural logrithm, i.e. f (x)=lnx.
Further, it can be set interval according to the mode of segmentation, without sending out erasing order every time
When all using new time interval, but can when the physical block being wiped free of is in certain PE numbers ranges the retention time
It is spaced constant, thereby simplifies operating process, improve system effectiveness.For example, as shown in fig. 6, PE times for 0-500 times
Time interval, can be set as (t3+t4)/2 by number；For the PE number of 500-1000 times, time interval can be set as
(t4+t5)/2；For the PE number of 1000-1500 times, time interval can be set as to (t5+t6)/2, and so on.It needs
Understand, above description is only to show a kind of easy embodiment, when the selection of time interval can be maximum
Between the average value of interval and minimum interval, can also select according to actual needs any suitable between maxima and minima
When value, can be that maximum time interval sets higher weight, thus for example, if necessary to relatively long time interval
Set time interval can suitably be increased.It is to be appreciated that above description is only one to set interval
A example, under the general idea of the application, any need carries out the situation of time interval setting, is wanted without departure from the application
The range of protection.
It, can also from above embodiment as can be seen that corresponding time interval can be set for each PE number
With regard to certain PE numbers ranges using identical time interval, and without continually adjustment time interval.
Embodiment 3
The time interval t0 for starting a query at SR registers is issued to from erasing order as set forth above, it is possible to set.It is sending out
After the erasing order t0 periods, read states order is sent out to NVM chips.
If the SR registers instruction read can send out read states order, until SR is deposited again in " busy " state
In " ready " state, this represents erasing order and performs completion for device instruction.
Optionally, time interval t is also set upmax, the maximum time of instruction execution erasing operation.If it is sent out in erasing order
T afterwardsmaxSR registers are still in the state of " doing " after time, then it is assumed that break down.
Optionally, repetition can also be set to send out the time interval dt of read states order.In response to the SR registers of reading
Instruction after the dt times, then sends out read states order to inquire SR registers, is sent out repeatedly with reducing high-frequency in " busy " state
Go out read states order and to the occupancy of flash memory channel, and reduce power consumption.Still optionally further, if sending out read states for the second time
It nevertheless indicates that SR registers are in " busy " state after order, then can send out read states life after dt time intervals again
It enables.
Further, if SR registers are nevertheless indicated that in " busy " shape after read states order is sent out for the second time
State, then since the possibility that following SR registers are in " ready " state is promoted, it is possible to again between the dt/2 times
Every sending out read states order again later.It is to be appreciated that dt/2, as just an example, which can be
The other values such as dt/3, dt/4, the application are not limited to these disclosed concrete numerical values.
In one example, according to PE number of physical block to be erased come the t0 that sets interval.For example, according to Fig. 6,
To PE number segmentation, to PE times, the different segmentations of several values, set different time interval t0.For example, it is in PE number
It at 0-1000 times, indicates that the minimum value of erasing order response time be t4, thus t0=t4 is set；And it is in PE number
At 1000-3000 times, the minimum value to the erasing order response time is t6, thus sets t0=t6.In the present example, without every
The secondary t0 that all sets interval when sending out erasing order, but can be in PE number or into the PE numbers ranges specified
When, correspondingly set interval t0.Time interval t0 can be set as to the minimum that NVM chips complete the time of erasing order
Value, so as to which control unit 104 can identify that erasing order performs completion as early as possible, so as to lifting system performance.It it is alternatively possible to will
T0 is set as the average value that NVM chips complete the time of erasing order, can more accurately read erasing order and perform completion
Instruction, send out the number of read states order to reduce, reduce the occupancy to flash memory channel, and reduce power consumption.
In another example, according to PE number of physical block to be erased, pass through power function t=a+b*xkTo calculate the time
Interval t0 can pass through b*x1 k-b*x0 kTo calculate the increment △ t=b*x of time interval t01 k-b*x0 k, without making
PE number is indicated with translation coefficient a, wherein x.Optionally, 0<k<1, such as K=1/2 or 1/3.It is to be appreciated that in power function
Value change in little range, without sending out erasing order every time when all sets interval t0, but counts and be at PE time
Or when entering the PE numbers ranges specified, correspondingly set interval t0.Optionally, it is obtained by way of tabling look-up between the time
Every the value of t0.For example, using PE number of the block to be wiped as index, table look-up to obtain the value of time interval t0.
It is to be appreciated that t=a+b*x may be usedkThe mode of this index determines time interval, but the application is simultaneously
It is not limited to this, such as t=a+b*log can also be usedmThis modes of x, wherein m>1, such as m can be the bottom of natural logrithm
Number e.
Embodiment 4
Fig. 7 is the flow chart that erasing order is performed according to the control unit 104 of further embodiment of this invention.
In the embodiment shown in fig. 7, it in operation S710, sets to be issued to from erasing order and starts a query at SR registers
Minimum interval tminAnd typical interval is tNoraml(S710), wherein tmin<tNoraml.Optionally, it is right with reference to Fig. 6
In specific PE number, according to the point setting minimum interval t on the dotted line being made of strigulamin, and according on solid line
Point setting typical interval tNoraml。
Still optionally, typical interval tNoramlCan be sent to NVM to NVM instruction lives from erasing order
Enable the average time interval for performing and completing.Alternatively, according to another embodiment, minimum interval tminWith typical time period
It is spaced tNoramlValue be segmented according to PE number.For example, minimum interval tminWith typical interval tNoraml
It is to be sent to PE number from erasing order to belong to the physical block of specified range to the time of NVM instruction order execution completions respectively
Minimum value and average value.So as to minimum interval tminWith typical interval tNoramlFor a certain range of PE number
Speech is kept constant respectively.
In the embodiment of Fig. 7, solid storage device is there are many operating mode, for example, low-power consumption mode or high-performance mould
Formula.In high performance mode, when the time interval t0 that starts a query at SR registers will be issued to from erasing order being set as minimum
Between be spaced tmin；And in low-power consumption mode, by be issued to from erasing order start a query at SR registers time interval t0 set
It is t for typical intervalNoraml(S720)。
After NVM chips send out erasing order, according to set time interval t0, started a query at after time interval t0
SR registers (S730/S740).
In one example, when sending out erasing order every time, the operating mode of solid storage device is identified, and will be between the time
Minimum interval t is set as every t0minOr typical interval is tNoraml。
It is low-power consumption mode or height in response to the operating mode for determining or changing solid storage device in preferred example
Performance mode, the t0 that correspondingly sets interval are minimum interval tminOr typical interval tNoraml, without
It sets interval when sending out erasing order every time, improves the efficiency of solid storage device processing erasing order.
If the state for inquiring the read states order instruction SR registers of SR registers is " busy ", read states can be sent out again
Order, until reading SR registers instruction " ready " state.
Preferably, the time interval dt of two read states orders is sent out according to the setting of the operating mode of solid storage device.
For example, in high performance mode, dt is set as the first value dt1；And under low-power consumption mode, dt is set as second value dt2, with
And dt1<dt2.
Embodiment 5
Fig. 8 is the sequence diagram for the program command for accessing NVM chips.In fig. 8, SR indicates that NVM chips are ordered in response to programming
The execution state of order (as indicated by the value of SR registers).To send out program command, control unit 104 (referring to Fig. 1) is in NVM cores
" order 4 " is sequentially generated on the DQ pins of piece, one or more " addresses " for indicating to be programmed Physical Page (is 4 " in Fig. 8
Location "), one or more data (being in Fig. 84 " data ") that be written into NVM chips and " order 5 ".In response, NVM
Chip to the Physical Page for specifying address is programmed that data are written.After the tp1 moment, " SR " register becomes the state of " doing ",
Instruction programming operation is carrying out；And tp2 moment after programming is completed, the correspondence position of " SR " register become " ready " shape
State.After sending out program command, control unit 104 inquire SR registers, in response to SR registers be " ready " state, control unit
104 know that program command has been completed.
It has been found that the time of NVM chip processing program commands is basically independent on PE number, and mainly with programming
Pattern is related.The programming mode of operation TLC flash memories includes, 3 page datas of one-time programming TLC Hash memory pages, one-time programming TLC flash memories
Preceding 2 page data of page, rear 2 page data of one-time programming TLC flash memories, with the 1st page data of one-time programming TLC Hash memory pages or last
Page data.In general, the data volume being written in one-time programming is bigger, required programming time is longer.
As a result, compared with being set interval according to PE times of erasing order number, for program command, according to volume
The data volume of journey order write-in sets interval.
Fig. 9 is the flow chart that control unit 104 according to embodiments of the present invention performs program command.As shown in figure 9, grasping
Make S910, set be issued to completely from program command the optional time interval of one or more for starting a query at SR registers (for example,
Tm1 or tm2).Next, in operation S920, program command is sent out, and according to the corresponding programming mode of program command, select institute
The time interval (tm1 or tm2) of setting.For example, in operation S920, if programming mode is the specific of one-time programming TLC Hash memory pages
Page (such as page 3) data set and are issued to the time interval for starting a query at SR registers completely from program command as tm1.And
In operation S930, according to set time interval, after tm1 time intervals, read states order is sent out to NVM chips.And
If the SR registers instruction NVM chips read are in " busy " state, read states order is sent out again, at SR register instructions
In " ready " state, represent program command and perform completion.In operation S920, if programming mode is the 2 of one-time programming TLC Hash memory pages
Page data sets and is issued to the time interval for starting a query at SR registers completely from program command as tm2.And it is operating
According to set time interval, after tm2 time intervals, read states order is sent out to NVM chips by S940.
Optionally, the time interval tm3 that repetition sends out read states order is also set up.It is indicated in response to the SR registers of reading
In " busy " state, after the tm3 times, read states order is sent out again, to reduce frequently and repeatedly send out read states order
To the occupancy of flash memory channel, and reduce power consumption.
Embodiment 6
Figure 10 is the flow chart that control unit 104 according to embodiments of the present invention performs read command.
It has been found that the time of NVM chip processing read commands depends on the data volume to be read.Such as NVM cores
The read command required time general time being greater than needed for the read command for reading 1KB data of 4KB data is read in piece.Cause
This, as shown in Figure 10, in operation S1010, inquiry is set (for example, sending out reading shape according to the read command data volume to be read
State order) at the beginning of,
Next, in operation S1020, read command is sent out to read data.Then, it in operation S1030, is opened in set
The implementing result of beginning time inquiring read command.If query result shows that " SR " register is " busy " state, then it represents that read operation
It is carrying out；If query result shows that " SR " register is " ready " state, then it represents that read operation has been completed, and is controlled as a result,
Component 104 processed knows that read command has been completed.
Further, if the read out SR registers nevertheless indicate that in " busy " state, then send out read states again and order
It enables, until SR registers indicate, in " ready " state, to represent read command and perform completion.Optionally, time interval is also set up
Tmax, instruction perform the maximum time of read operation.If SR registers are still in after the tmax times after read command is sent out completely
" busy " state, then it is assumed that break down.Optionally, the time interval t3 that repetition sends out read states order is also set up.In response to reading
The SR registers instruction gone out after the t3 times, is sending out read states order, to reduce frequently and repeatedly send out in " busy " state
Go out occupancy of the read states order to flash memory channel, and reduce power consumption.
Methods and apparatus of the present invention can with hardware, software, firmware and it is above-mentioned in arbitrary combination realize.Hardware
It can include digital circuit, analog circuit, digital signal processor (DSP), application specific integrated circuit (ASIC) etc..Software can
To include computer-readable program, these computer-readable programs are realized according to embodiments of the present invention when being computer-executed
The method provided.
For example, embodiments herein may be embodied as storage control, which can include：One or
Multiple processors；Memory；Program stored in memory, when being performed by one or more processor, program makes place
The method that reason device execution is provided according to embodiments of the present invention.
The software of the present invention can also be stored in computer readable storage medium, such as hard disk, CD etc., the computer
Readable storage medium storing program for executing has program stored therein, when program is performed by an equipment so that equipment performs institute according to embodiments of the present invention
The method of offer.
Above description is only to exemplary rather than exhaustive the description of the present invention, and those skilled in the art can be to upper
Method, unit, module etc. is stated to be added, delete, change, replacing etc., essence and guarantor without departing from the present invention
Protect range.
Claims (10)
1. a kind of method for accessing memory, including：
Order is sent out to the memory；
After set time interval, the implementing result of the order is inquired, to obtain query result, wherein set
Time interval represents to be issued to the time interval for proceeding by the inquiry from the order.
2. according to the method described in claim 1, wherein,
The order is the erasing order for the memory, and the inquiry is carried out by performing read states order.
3. method according to claim 1 or 2, wherein,
The time interval is set according to the erasing times of the accessed storage unit of the order.
4. according to the method described in any one in claim 1-3, wherein,
The time interval is set according to the range of the erasing times of the accessed storage unit of the order.
5. according to the method described in any one in claim 1-4, wherein,
The time interval t is set according to following equation：
T=a+b*f (x)
Wherein, x represents the erasing times of the accessed storage unit of the order, and a is the coefficient specified, and b is the coefficient specified.
6. according to the method described in any one in claim 1-5, further comprise：
If the query result shows that the memory is in " busy " state, looked into again after the first specified time interval
Implementing result of the order on the memory is ask, until the memory is in " ready " state.
7. according to the method described in any one in claim 1-6, wherein,
If in high performance mode, will be described between be set to the first value；And
If in low-power consumption mode, the time interval is set as second value；Wherein foundation is sent to from order in institute
The storage unit of access indicates that order performs minimum value the first value of setting for the time interval completed to the storage unit；Foundation
It is sent to from order and indicates that order performs being averaged for the time interval of completion in the storage unit accessed to the storage unit
Value setting second value.
8. according to the method described in claim 7, wherein
Belong to the storage unit of specified erasing times range to described in its erasing times accessed according to being sent to from order
The minimum value that storage unit instruction order performs the time interval completed sets the first value；It is being accessed according to being sent to from order
Its erasing times belong to the storage unit of specified erasing times range to the storage unit indicate order perform complete when
Between be spaced average value setting second value.
9. a kind of storage control, including：
One or more processor；
One or more memories；And
The program being stored in the memory, when being performed by one or more of processors, described program makes described
Controller performs the method as described in any one in claim 1-8.
10. a kind of equipment for accessing memory, including：
For sending out the device of the order to the memory；
For after set time interval, inquiring the implementing result of the order, to obtain the device of query result,
In set time interval represent to be issued to the time interval for proceeding by the inquiry from the order.
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