CN108206177A - Micro-space packaging and stacking method and micro-space packaging and stacking structure - Google Patents

Micro-space packaging and stacking method and micro-space packaging and stacking structure Download PDF

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Publication number
CN108206177A
CN108206177A CN201710166987.8A CN201710166987A CN108206177A CN 108206177 A CN108206177 A CN 108206177A CN 201710166987 A CN201710166987 A CN 201710166987A CN 108206177 A CN108206177 A CN 108206177A
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Prior art keywords
terminal
intermediary
micro
embedded
terminals
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CN201710166987.8A
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Inventor
陈裕纬
王启安
徐宏欣
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN108206177A publication Critical patent/CN108206177A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

The invention provides a micro-space packaging stacking method and a micro-space packaging stacking structure. Providing a carrier plate, and arranging a plurality of embedded terminals and a plurality of external terminals on the upper surface and the lower surface of the carrier plate respectively. A wafer is disposed on the carrier. A molding compound is formed on the carrier to seal the chip and the embedded terminals. The top end surfaces of the embedded terminals are exposed on the flat surface of the molding colloid in a coplanar manner by flattening and grinding the molding colloid. The top package structure is mounted on the flat surface, an intermediate rotating plate is arranged between the top package structure and the molding compound body, the top package structure comprises a plurality of top terminals, the intermediate rotating plate comprises a plurality of intermediate terminals, the top terminals are connected to corresponding connecting pads of the intermediate rotating plate in the reflow process, and the intermediate terminals are connected to the top end surfaces of the embedded terminals. Therefore, the intermediate terminal has the advantages of micro-space arrangement and miniaturization without the risk of fusion short circuit.

Description

Micro- pitch packages stacking method and micro- pitch packages stacking construction
Technical field
The present invention relates to semiconductor wafer package fields more particularly to a kind of micro- pitch packages stacking method to seal with micro- spacing Fill stacking construction.
Background technology
Semiconductor wafer package construction be that surface is bonded in external printed circuit board in early days, and can have have it is various The encapsulation kenel known.When top encapsulation structured surface is bonded on bottom package structurally, encapsulation stacking construction can be combined into (Package-On-Package,POP).It will with spacing to connect the size of intermediary's terminal of top and bottom packaging structure The making yield of encapsulation stacking construction is significantly influenced, usual intermediary's terminal is comprising soldered ball.
In the existing bottom package construction using laser drill, such as intermediary's terminal of soldered ball is pre-set at bottom envelope It is sealed on the substrate of assembling structure and with molding colloid.Then, in a manner of laser drill to expose intermediary's terminal by molding colloid packet The tin ball surface enclosed, for the soldered ball engagement of top encapsulation construction, therefore the top and bottom packaging structure of stacked on top can return Weldering composition one encapsulation stacking construction (POP).
Referring to Fig. 1, a kind of top of existing encapsulation stacking construction (POP) comprising bottom package construction 10 and stacked on top Portion's packaging structure 20 is for example made between bottom package construction 10 and top encapsulation construction 20 with multiple by intermediary's terminal 30 of molding Reflow engages.Bottom package construction 10 includes substrate 11, and chip 12 is installed on the substrate 11 and sealed with molding colloid 13, can profit Chip 12 is electrically connected to substrate 11 with the convex block of multiple chip bondings.Intermediary's terminal 30 is engaged in the upper surface of substrate 11 in advance And it is also sealed by molding colloid 13.Multiple external terminals 14 are engaged in the lower surface of substrate 11.Exposed with laser drill operation The top surface of intermediary's terminal 30, and molding colloid 13 will form barricade 15 between intermediary's terminal 30.20 packet of top encapsulation construction Containing another substrate 21, chip 22 is installed on the base plate (21 and is sealed with molding colloid 23.Using multiple routing (bonding Wire) bonding wire 24 formed is electrically connected chip 22 and substrate 21.The lower surface of substrate 21 is provided with connection gasket, to engage intermediary Terminal 30.
Fig. 2 shows the offices that bottom package when laser drill operation is carried out in the technique constructed in existing encapsulation stacking constructs Portion's schematic cross-section.Laser drill operation is carried out to the molding colloid 13 of bottom package construction 10 with laser drill 40, until Expose the top surface of intermediary's terminal 30；Meanwhile molding colloid 13 forms barricade 15 between intermediary's terminal 30, script purpose is to keep away Exempt to melt short circuit during the docking of tin ball.However, when the spacing microminiaturization of intermediary's terminal 30, the oblique angle of laser drill aperture needs, It will lead to the dwarfing of barricade, downsizing and disabler.Therefore, the bottom package construction of laser drill can not meet next-generation micro- The requirement of pitch packages stacking construction (POP), this is because the thickness of barricade and oblique angle requirement in technique, limit bottom package Construction moves towards the developing ability of micro- spacing.
Invention content
In order to solve the problem above-mentioned, it is a primary object of the present invention to provide a kind of micro- pitch packages stacking method, use It is bridged with the solder for preventing intermediary's breakover element of bottom packaging structure during encapsulation stacking constructs, intermediary's terminal can more micro- spacing Arrangement and microminiaturization.
Time the one of the present invention is designed to provide a kind of micro- pitch packages stacking method so that the spacing of intermediary's terminal can be with No more than the top terminals spacing of top encapsulation construction, it can also be not more than the spacing of the external terminal of bottom package construction simultaneously, More there is adjustment elasticity in the product design of encapsulation stacking construction (POP).
The object of the invention to solve the technical problems is realized using following technical scheme.The present invention discloses a kind of Micro- pitch packages stacking method, first, provides support plate, respectively set in the upper surface of support plate and lower surface it is multiple be embedded into terminal with it is more A external terminal.Later, chip is set on support plate.Later, molding colloid is formed on the support plate, wherein molding colloid is close should Chip is with being embedded into terminal.Later, in a manner of planarizing lap adhesive body, the top end face for being embedded into terminal is manifested coplanarly In the flat surface of molding colloid.Later, top encapsulation construction is installed on flat surface, and in top encapsulation construction and molding glue Intermediary's flap is intervened between body, top encapsulation construction includes multiple top terminals, and intermediary's flap includes multiple intermediary's terminals, in reflow In the process, top terminals are bonded to the correspondence connection pad of intermediary's flap, and intermediary's terminal is bonded to the top end face for being embedded into terminal.
The object of the invention to solve the technical problems also can be used following technical measures and further realize.
In aforementioned micro- pitch packages stacking method, support plate can be the two-sided plant ball circuit base plate of bottom package construction.
In aforementioned micro- pitch packages stacking method, it can be the soldered ball of identical size to be embedded into terminal with external terminal.
In aforementioned micro- pitch packages stacking method, the back side of chip can be revealed in the flat of molding colloid coplanarly Face.
The present invention discloses a kind of micro- pitch packages stacking construction, and it includes support plate, chip, molding colloid and top encapsulations Construction.It is respectively set in the upper surface of the support plate and lower surface and multiple is embedded into terminal and multiple external terminals.Chip is arranged on institute It states on support plate.Molding colloid is formed on the support plate, is embedded into wherein the molding colloid seals the chip with the multiple Terminal；Wherein in a manner that the molding colloid is ground in planarization, the multiple top for being embedded into terminal is manifested coplanarly Face is in the flat surface of the molding colloid.Top encapsulation construction is mounted on the flat surface, and in the top encapsulation structure It makes and intermediary's flap is intervened between the molding colloid, the top encapsulation construction includes multiple top terminals, intermediary's flap Comprising multiple intermediary's terminals, in reflow process, the multiple top terminals are bonded to the correspondence connection pad of intermediary's flap, described Multiple intermediary's terminals are bonded to the multiple top end face for being embedded into terminal.
By above-mentioned technological means, the present invention can reach intermediary's terminal for the arrangement of micro- spacing and the package stack of microminiaturization Folded construction, compared to the encapsulation stacking technique of existing laser drill, made construction does not have the risk of melting short circuit.In work It has been used in skill and terminal is for example embedded by molding metal ball, tentatively to reduce the size of intermediary's terminal, molding colloid has been put down Smoothization grinding is embedded into the top end face of terminal to expose, and for intermediary's terminal of engagement intermediary flap, thereby forms encapsulation stacking structure The bottom package construction made, and have effects that following：Firstth, it realizes and grafts the small tin ball with microballoon spacing as intermediary end The encapsulation stacking construction of son, the spacing that the bottom package construction of encapsulation stacking construction docks unit with intermediary flap can reduce, The melting short circuit risk constructed in encapsulation stacking technique without generating existing laser drill using bottom package；Secondth, it is flat The terminal connections output of smoothization grinding will to obtain higher than the terminal connections output of existing laser drill, to reduce process costs； Third, the chip back surface that can expose bottom package by planarizing grinding and construct, to improve chip heat dissipation.
Description of the drawings
Fig. 1 is the schematic cross-section that a kind of existing encapsulation stacking constructs (POP).
The part of bottom package construction when laser drill operation is carried out in the technique that Fig. 2 is constructed in existing encapsulation stacking is cut Face schematic diagram.
Fig. 3 is a kind of schematic cross-section of micro- pitch packages stacking construction of specific embodiment according to the present invention.
Fig. 4 A to Fig. 4 E are each main step in a kind of micro- pitch packages stacking method of a specific embodiment according to the present invention Rapid element cross-section schematic diagram.
Specific embodiment
Below in conjunction with the attached drawing embodiment that the present invention will be described in detail, so it should be noted that these attached drawings are simplified Schematic diagram only illustrates the basic framework of the present invention or implementation with illustrative method, therefore only shows the member related with the application Part is closed with combining, and shown element not does equal proportion drafting, certain rulers with the number, shape, size of actual implementation in figure Very little ratio and other relative dimensions ratios have been exaggerated or have simplified processing, to provide clearer description.The number of actual implementation Mesh, shape and dimension scale are a kind of selective design, and detailed component placement is likely more complexity.
Specific embodiment according to the present invention, the section that a kind of micro- pitch packages stacking construction 100 is illustrated in Fig. 3 show It is intended to.A kind of micro- pitch packages stacking method is illustrated in the element cross-section schematic diagram of each main steps of Fig. 4 A to Fig. 4 E.
Referring to Fig. 3, a kind of micro- pitch packages stacking construction 100 include support plate 110, chip 140, molding colloid 150 with And top encapsulation construction 160.The upper surface setting of support plate 110 is multiple to be embedded into terminal 120 and lower surface and respectively sets multiple external connection ends Son 130.Chip 140 is set to 110 upper surface of support plate.Molding colloid 150 is formed in 110 upper surface of support plate, wherein molding colloid 150 sealing chips 140 are with being embedded into terminal 120.In a manner of planarizing lap adhesive body 150, it is embedded into the top end face of terminal 120 121 manifest the flat surface 151 in molding colloid 150 coplanarly.Top encapsulation construction 160 is arranged on flat surface 151.And And the intervention intermediary flap 170 between top encapsulation construction 160 and molding colloid 150.Top encapsulation construction 160 includes multiple tops Terminal 161, intermediary's flap 170 include multiple intermediary's terminals 171.In reflow process, top terminals 161 are bonded to intermediary's flap 170 correspondence connection pad 172, intermediary's terminal 171 are bonded to the top end face 121 for being embedded into terminal 120.
The manufacturing method of encapsulation stacking construction 100 is further illustrated as after.First, Fig. 4 A are please referred to, support plate 110 is provided, It is respectively set in the upper surface of support plate 110 and lower surface and multiple is embedded into terminal 120 and multiple external terminals 130.In the present embodiment, Support plate 110 can be the two-sided plant ball circuit base plate of bottom package construction.It can be identical ruler to be embedded into terminal 120 with external terminal 130 Very little soldered ball.The upper surface of support plate 110 can form soldermask layer 181, and multiple substrate connection pads 182 are not covered simultaneously by soldermask layer 181 Corresponding external terminal 130 is electrically connected to, so that engagement is embedded into terminal 120.In this step, support plate 110 can be panel type State, big chip kenel or substrate strip kenel.
Fig. 4 B are please referred to, chip 140 is set on support plate 110.Chip 140 may include multiple convex blocks 141, be connect using flip Conjunction mode, convex block 141 engages the flip connection pad of support plate 110, and active face (active surface) direction of chip 140 carries Plate 110.Convex block 141 may include golden convex block or copper bump.The active face of chip 140 should be at least above by being embedded into terminal 120, and according to Actual demand, being embedded into terminal 120 can be higher than or the back side not higher than chip 140.
Please refer to Fig. 4 C, form molding colloid 150 on support plate 110, wherein molding colloid 150 seal chip 140 with it is embedding Bury terminal 120.Molding colloid 150 can be heat cured insulation compound, and be formed with compressing molding or transfer molding.In this step In rapid, the thickness of molding colloid 150 should be greater than being embedded into the height of terminal 120.
Fig. 4 D are please referred to, using flat mill 50 to planarize lap adhesive body 150, in this manner, being embedded into end The top end face 121 of son 120 is emerging in the flat surface 151 of molding colloid 150 coplanarly.In one embodiment, the back of the body of chip 140 Face 142 can be revealed in the flat surface 151 of molding colloid 150 coplanarly.
Fig. 4 E and Fig. 3 are please referred to, top encapsulation construction 160 is installed on flat surface 151, and construct in top encapsulation Intermediary's flap 170 is intervened between 160 and molding colloid 150.Top encapsulation construction 160 includes multiple top terminals 161, intermediary's flap 170 include multiple intermediary's terminals 171.In reflow process, top terminals 161 are bonded to the correspondence connection pad 172 of intermediary's flap 170, And intermediary's terminal 171 is bonded to the top end face 121 for being embedded into terminal 120.In addition, top encapsulation construction 160 can also include chip 162nd, it seals the adhesive body 163 of chip 162 and carries the substrate 164 of the chip 162.In the present invention, bottom package constructs Singulation process may be implemented in encapsulation stacking technique install top encapsulation construction after.
Therefore, the present invention provides a kind of micro- pitch packages stacking method, to prevent bottom in encapsulation stacking construction 100 from sealing Intermediary's breakover element such as intermediary's terminal 171 of assembling structure solder bridge joint, intermediary's terminal 171 can more micro- spacing arrangement With microminiaturization, for molding colloid to planarize surface grinding instead of laser drill, along with the combination of intermediary's flap, therefore Realize the bottom package construction of microballoon pitch packages stacking.In addition, the spacing of intermediary's terminal 171 can be not more than top terminals 161 spacing can also be not more than the spacing of external terminal 130, more have in the product design of encapsulation stacking construction (POP) simultaneously Adjustment elasticity.
The above disclosure is only the preferred embodiments of the present invention, cannot limit the right model of the present invention with this certainly It encloses, therefore equivalent variations made according to the claims of the present invention, is still within the scope of the present invention.

Claims (8)

1. a kind of micro- pitch packages stacking method, which is characterized in that include：
Support plate is provided, setting is multiple in the upper surface of the support plate is embedded into terminal with being set outside multiple in the lower surface of the support plate Connecting terminal；
In the upper surface of the support plate, chip is set；
Molding colloid is formed in the upper surface of the support plate, is embedded into wherein the molding colloid seals the chip with the multiple Terminal；
In a manner that the molding colloid is ground in planarization, the multiple top end face for being embedded into terminal is manifested coplanarly in institute State the flat surface of molding colloid；And
Top encapsulation is set to construct on the flat surface, and be situated between top encapsulation construction and the molding colloid Enter intermediary's flap, the top encapsulation construction includes multiple top terminals, and intermediary's flap includes multiple intermediary's terminals, in reflow In the process, the multiple top terminals are bonded to the correspondence connection pad of intermediary's flap, and the multiple intermediary's terminal is bonded to described Multiple top end faces for being embedded into terminal.
2. micro- pitch packages stacking method according to claim 1, which is characterized in that the support plate is constructed for bottom package Two-sided plant ball circuit base plate.
3. micro- pitch packages stacking method according to claim 2, which is characterized in that it is the multiple be embedded into terminal with it is described Multiple external terminals are the soldered ball of identical size.
4. micro- pitch packages stacking method according to claim 1,2 or 3, which is characterized in that in planarization grinding steps In, the back side of the chip is revealed in the flat surface of the molding colloid coplanarly.
5. a kind of micro- pitch packages stacking construction, which is characterized in that include：
Support plate respectively sets in the upper surface of the support plate and lower surface and multiple is embedded into terminal and multiple external terminals；
Chip is arranged on the support plate；
Molding colloid is formed on the support plate, wherein the molding colloid seals the chip is embedded into terminal with the multiple； Wherein in a manner that the molding colloid is ground in planarization, the multiple top end face for being embedded into terminal is manifested coplanarly in institute State the flat surface of molding colloid；And
Top encapsulation constructs, on the flat surface, and between top encapsulation construction and the molding colloid Intermediary's flap is intervened, the top encapsulation construction includes multiple top terminals, and intermediary's flap includes multiple intermediary's terminals, is returning During weldering, the multiple top terminals are bonded to the correspondence connection pad of intermediary's flap, and the multiple intermediary's terminal is bonded to institute State multiple top end faces for being embedded into terminal.
6. micro- pitch packages stacking construction according to claim 5, which is characterized in that the support plate is constructed for bottom package Two-sided plant ball circuit base plate.
7. micro- pitch packages stacking construction according to claim 6, which is characterized in that it is the multiple be embedded into terminal with it is described Multiple external terminals are the soldered ball of identical size.
8. micro- pitch packages stacking construction according to claim 5,6 or 7, which is characterized in that the back side of the chip is total to Plane earth is revealed in the flat surface of the molding colloid.
CN201710166987.8A 2016-12-20 2017-03-20 Micro-space packaging and stacking method and micro-space packaging and stacking structure Withdrawn CN108206177A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110089563A1 (en) * 2009-10-15 2011-04-21 Renesas Electronics Corporation Method for manufacturing semiconductor device and semiconductor device
CN102646668A (en) * 2011-02-17 2012-08-22 三星电子株式会社 Semiconductor package having tsv interposer and method of manufacturing same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110089563A1 (en) * 2009-10-15 2011-04-21 Renesas Electronics Corporation Method for manufacturing semiconductor device and semiconductor device
CN102646668A (en) * 2011-02-17 2012-08-22 三星电子株式会社 Semiconductor package having tsv interposer and method of manufacturing same

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Application publication date: 20180626