CN108197047B - Intelligent interface circuit - Google Patents
Intelligent interface circuit Download PDFInfo
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- CN108197047B CN108197047B CN201710718059.8A CN201710718059A CN108197047B CN 108197047 B CN108197047 B CN 108197047B CN 201710718059 A CN201710718059 A CN 201710718059A CN 108197047 B CN108197047 B CN 108197047B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses an intelligent interface circuit for realizing the program downloading of a control chip, which comprises a mode guide circuit and a communication interface circuit, wherein the input end of the mode guide circuit is used for receiving a mode selection signal input by a user, and the output end of the mode guide circuit is connected with an I/O port of the control chip; a first signal transmission end of the communication interface circuit is connected with an upper computer; the second signal transmission end of the communication interface circuit is connected with the signal sending/receiving end of the control chip; the mode guide circuit is used for receiving a mode selection signal input by a user and outputting the mode selection signal to the control chip so as to guide the control chip to enter a mode selected by the user; the selection mode comprises a program running mode, a burning mode and a serial port downloading mode; and the communication interface circuit is used for connecting and communicating the upper computer and the control chip under a serial port downloading mode so that the control chip obtains a corresponding program from the upper computer. The invention solves the problem that the control chip needs to be programmed on line through JTAG.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an intelligent interface circuit.
Background
In the research and development process of electrical equipment such as a variable frequency air conditioner and the like, the downloading, simulation and debugging of a control chip program in the electrical equipment are inevitably realized by the support of an external simulation tool interface.
Currently, a commonly used interface circuit is a standard JTAG (Joint Test Action Group) interface circuit, and the interface has 4 lines and respectively includes: mode select TMS, clock TCK, data input TDI, and data output TDO. Wherein, TCK is the test clock input, export to the control chip through the simulator; TDI is test data input, and data are sent to a control chip through a TDI by a simulator; TDO is test data output, and the data of the control chip is sent to the simulator through the TDO; TMS is test mode selection, and the test mode of the control chip can be set through TMS.
However, such JTAG interface circuit needs to be externally connected to the emulator and configure the emulator power supply, resulting in increased development cost. More importantly, the JTAG interface is liable to bring electrostatic interference to the controller, and if the JTAG interface is cancelled, it is inconvenient to upgrade the program of the control chip after sale.
Disclosure of Invention
The invention mainly aims to provide an intelligent interface circuit, which aims to solve the problem that the research and development cost of electrical equipment is increased because a control chip needs to be realized through JTAG online programming when a program is downloaded.
In order to achieve the above object, the present invention provides an intelligent interface circuit for downloading a control chip program in an electrical device, the intelligent interface circuit includes a mode directing circuit and a communication interface circuit, an input end of the mode directing circuit is used for receiving a mode selection signal input by a user, and an output end of the mode directing circuit is connected to an I/O port of the control chip; the first signal transmission end of the communication interface circuit is connected with the upper computer; the second signal transmission end of the communication interface circuit is connected with the signal sending/receiving end of the control chip; wherein the content of the first and second substances,
the mode guide circuit is used for receiving a mode selection signal input by a user and outputting the mode selection signal to the control chip so as to guide the control chip to enter a mode selected by the user; the selection mode comprises a program running mode, a burning mode and a serial port downloading mode;
and the communication interface circuit is used for connecting and communicating the upper computer and the control chip under the serial port downloading mode so as to enable the control chip to obtain a corresponding program from the upper computer.
Preferably, the mode directing circuit includes a mode selection switch for receiving a mode selection signal input by a user, a first delay circuit unit and a second delay circuit unit for respectively delaying the mode selection signal, and a first signal circuit processing unit and a second signal processing circuit unit for shaping a waveform of the mode selection signal, an input end of the mode selection switch is connected to a first dc power source VCC, and an output end of the mode selection switch is respectively connected to input ends of the first delay circuit unit and the second delay circuit unit; the output end of the first delay circuit unit is connected with the input end of the first signal processing circuit unit; the output end of the first signal processing circuit unit is connected with the reset end of the control chip; the output end of the second signal processing circuit unit is connected with a first I/O port of the control chip; wherein the content of the first and second substances,
the delay action time of the first delay circuit unit is shorter than that of the second delay circuit unit, so that the first signal circuit processing unit and/or the second signal processing circuit unit are triggered to act according to the mode selection signal, and the control chip is guided to enter a corresponding selection mode.
Preferably, the first delay circuit unit includes a first resistor and a first capacitor, a first end of the first resistor is an input end of the first delay circuit unit, and a second end of the first resistor is an output end of the first delay circuit unit and is connected to a first end of the first capacitor; the second end of the first capacitor is grounded.
Preferably, the second delay circuit unit includes a second resistor, a third resistor, and a second capacitor, a first end of the second resistor is interconnected with a second end of the first resistor and a first end of the third resistor, and a second end of the second resistor is an output end of the second delay circuit unit and is connected with a first end of the second capacitor; and the second end of the second capacitor and the second end of the third resistor are both grounded.
Preferably, the first signal processing circuit unit includes a first schmitt trigger and a third capacitor, an input end of the first schmitt trigger is an input end of the first signal processing circuit unit, and an output end of the first schmitt trigger is an output end of the first signal processing circuit unit and is connected to a first end of the third capacitor; and the second end of the third capacitor is grounded.
Preferably, the second signal processing circuit unit includes a second schmitt trigger and a fourth resistor, an input end of the second schmitt trigger is an input end of the second signal processing circuit unit, and an output end of the second schmitt trigger is connected to a first end of the fourth resistor; and the second end of the fourth resistor is the output end of the second signal processing circuit unit.
Preferably, the mode guidance circuit further includes a mode selection display unit for displaying a user selection mode, the mode selection unit includes a first LED lamp, a second LED lamp, a fifth resistor and a sixth resistor, anodes of the first LED lamp and the first LED lamp are both connected to the first dc power supply, and a cathode of the first LED lamp is connected to the output terminal of the first signal processing circuit unit through the fifth resistor; and the cathode of the second LED lamp is connected with the second signal processing circuit unit through the sixth resistor.
Preferably, the mode directing circuit comprises a mode selection switch for receiving a mode selection signal input by a user, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, wherein a first input end and a second input end of the mode selection switch are both grounded, and a first output end of the mode selection switch is interconnected with the first I/O port of the control chip and a first end of the ninth resistor through the seventh resistor; a second output end of the mode selection switch is interconnected with a second I/O port of the control chip and a first end of the tenth resistor through the eighth resistor; and the second end of the ninth resistor and the second end of the tenth resistor are both connected with a first direct current power supply.
Preferably, the communication interface circuit comprises a USB interface, a switching chip, an eleventh resistor and a twelfth resistor, and a first data terminal of the USB interface is connected to a USB signal input pin of the switching chip through the eleventh resistor; the second data end of the USB interface is connected with the USB signal output pin of the switching chip through the twelfth resistor; a serial data input pin of the switching chip and a signal receiving end of the chip; and the serial data output pin of the switching chip is connected with the signal transmitting end.
Preferably, the intelligent interface circuit further comprises a reset circuit for controlling the control chip to reset, the reset circuit comprises a reset key, a thirteenth resistor and a fourth capacitor, a first conduction end of the reset key is grounded, and a second conduction end of the reset key is interconnected with the reset end of the control chip, a first end of the thirteenth resistor and a first end of the fourth capacitor; the second end of the thirteenth resistor is connected with a first direct current power supply; and the second end of the fourth capacitor is grounded. .
The invention converts the electrical equipment from the serial port equipment to the plug-and-play USB equipment through the communication interface circuit, and when the user selects the serial port downloading mode, the mode guide circuit receives the mode selection signal output by the user and outputs the mode selection signal to the I/O port of the control chip so as to guide the control chip to enter the program downloading (SCI) mode, and then the communication connection between the upper computer and the control chip is realized through the USB-to-serial port circuit so as to download the edited program to the control chip through the USB-to-serial port circuit. The invention solves the problem that the research and development cost of the electrical equipment is increased because the control chip needs to be realized through JTAG online programming when the program is downloaded. In addition, the invention also solves the problems that the JTAG interface needs to be welded again after sale, the emulator and the power supply thereof are configured, or the drive board or the main control board is replaced, the product maintenance cost is higher, and great inconvenience is brought to the use of a user.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of an embodiment of an intelligent interface circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of an embodiment of the control chip and its peripheral circuits shown in FIG. 1;
FIG. 3 is a schematic circuit diagram of a first embodiment of the conductive circuit of the mode of FIG. 1;
FIG. 4 is a circuit diagram illustrating a second embodiment of the conductive circuit of FIG. 1;
fig. 5 is a schematic circuit diagram of an embodiment of the communication interface circuit in fig. 1.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides an intelligent interface circuit which is used for realizing control chip program downloading in electrical equipment.
Many electrical appliances such as air conditioners, washing machines, and refrigerators have a drive board and a main control board. In the process of research and development and after-sale of electrical equipment, debugging and upgrading of control chips on a drive board and a main control board are needed. The control chip, such as DSP, FPGA, and single chip, supports JTAG protocol, and JTAG is a universal worldwide standard, so the JTAG interface is usually adopted In the industry to implement ISP (In-System Programmable, online programming), for example, to program devices such as FLASH. The application of JTAG online programming simplifies the process of preprogramming the control chip and then mounting the control chip on the board into: firstly, fixing a control chip needing to be online on a drive board or a main control board, and then burning (downloading) a program through a JTAG interface.
Specifically, the JTAG interface has 4 lines and is: mode select TMS, clock TCK, data in TDI, and data out line TDO. Wherein, the data is sent to the control chip through the TDI through the simulator; TDO is test data output, and the data of the control chip is sent to the simulator through the TDO. Therefore, in the process of realizing online programming of the JTAG interface, the emulator needs to be connected to the outside of the JTAG interface, and the power supply of the emulator needs to be configured, which increases the development cost of the electrical equipment. In addition, the JTAG interface is directly connected to the internal control chip, so that the control chip may be damaged by static electricity. Therefore, before leaving the factory, manufacturers mostly take the JTAG interface off the drive board or the main control board, and thus need to weld the JTAG interface again after sale, and configure the emulator and the power supply thereof, otherwise, only the drive board or the main control board can be replaced, the product maintenance cost is high, and great inconvenience is brought to the use of users.
Referring to fig. 1 to 4, in order to solve the above problem, in an embodiment of the present invention, the intelligent interface circuit includes a mode directing circuit 10 and a communication interface circuit 20, an input end of the mode directing circuit 10 is used for receiving a mode selection signal input by a user, and an output end of the mode directing circuit 10 is connected to an I/O port of the control chip 200; a first signal transmission end of the communication interface circuit 20 is connected with the upper computer 100; a second signal transmission end of the communication interface circuit 20 is connected to a signal transmitting/receiving end of the control chip 200; wherein the content of the first and second substances,
the mode directing circuit 10 is configured to receive a mode selection signal input by a user and output the mode selection signal to the control chip 200, so as to direct the control chip 200 to enter a mode selected by the user; the selection mode comprises a program running mode, a burning mode and a serial port downloading mode;
the communication interface circuit 20 is configured to enable the upper computer 100 to connect and communicate with the control chip 200 in the serial port download mode, so that the control chip 200 obtains a corresponding program from the upper computer 100.
The mode directing circuit 10 outputs the mode selection signal to the I/O port corresponding to the control chip 200 according to the mode selection signal input by the user, so that the control chip 200 enters the corresponding mode under the guidance of the mode selection signal based on the preset mode protocol, the preset mode protocols of each control chip 200 are different, and the table lookup can be performed. In order to better describe the present invention, in the embodiment, a TMS320C28X DSP control chip 200 is taken as an example for explanation, and referring to fig. 2, fig. 2 is a DSP minimum system composed of a TMS320C28X DSP control chip and peripheral circuits thereof. The first I/O port TDO (fifty-seventh pin) and the second I/O port GPI/O34 (seventy-fourth pin) of the DSP control chip 200 of the TMS320C28X type are used for inputting mode selection signals, and the chip can be guided to enter different modes by changing the level of the first I/O port TDO and/or the second I/O port GPI/O34 of the DSP control chip 200 of the TMS320C28X type. As shown in table 1, which is a preset mode protocol table of the TMS320C28X DSP control chip 200:
TABLE 1
In this embodiment, when the level corresponding to the mode selection signals outputted from the mode directing circuit 10 to the first I/O port TDO and the second I/O port GPI/O34 on the DSP control chip 200 is 01, the control chip 200 is directed to enter a program download (SCI) mode, i.e., a serial port download mode. When the level of the mode selection signal outputted from the mode directing circuit 10 to the first I/O port TDO and the second I/O port GPI/O34 on the DSP control chip 200 is 11, the control chip 200 is directed to enter a program running (Run) mode. When the mode directing circuit 10 does not output the mode selecting signal to the control chip 200, the control chip 200 maintains the default programming (FLASH) mode.
The communication interface circuit 20 is preferably implemented as a USB to serial circuit. The upper computer 100 is in communication connection with the control chip 200 through a USB interface J1, and transmits the edited program to the control chip 200 through a USB interface J1, so as to upgrade the program of the control chip 200.
Specifically, after the level corresponding to the mode selection signal outputted by the mode directing circuit 10 to the first I/O port TDO and the second I/O port GPI/O34 on the DSP control chip 200 is 01, the control chip 200 enters a program downloading (SCI) mode, and at this time, the user can download the edited program to the control chip 200 through the USB to serial port circuit. After the program is downloaded, the mode directing circuit 10 outputs the corresponding level of the mode selection signal to the first I/O port TDO and the second I/O port GPI/O34 on the DSP control chip 200 to be 11, so as to direct the control chip 200 to enter a program running (Run) mode, so that the control chip 200 runs the updated program after being reset. Thus, the electrical equipment can be debugged or upgraded.
The invention converts the electrical equipment from the serial equipment into the plug-and-play USB equipment through the communication interface circuit 20, and when the user selects the serial download mode, the mode guide circuit 10 receives the I/O port of the control chip 200 from the user output and outputs the mode selection signal to guide the control chip 200 to enter the program download (SCI) mode, and then the communication connection between the upper computer 100 and the control chip 200 is realized through the USB-to-serial circuit, so as to download the edited program to the control chip 200 through the USB-to-serial circuit. The invention solves the problem that the research and development cost of the electrical equipment is increased because the control chip 200 needs to be realized by JTAG online programming when downloading the program. In addition, the invention also solves the problems that the JTAG interface needs to be welded again after sale, the emulator and the power supply thereof are configured, or the drive board or the main control board is replaced, the product maintenance cost is higher, and great inconvenience is brought to the use of a user.
It can be understood that, because the circuit structure of the invention is simple, and the communication interface circuit 20 can be compatible with the serial ports of the control chips 200 such as the DSP, the FPGA, the single chip microcomputer, etc., the intelligent interface circuit of the invention can be applied to the research, development and production of the electrical equipment with the control chips 200 such as the DSP, the FPGA, the single chip microcomputer, etc., or the program upgrade after sale.
It can also be understood that the circuit of the intelligent interface circuit is simple and easy to implement, so the thermal intelligent interface circuit can be arranged on a driving board or a main control board of the electrical equipment, and can also be independently arranged as an independent adapter small board to connect the upper computer 100 and the electrical equipment, which is not limited herein.
Referring to fig. 1 to 5, a first embodiment of a mode directing circuit 10 according to the present invention is proposed, in which the mode directing circuit 10A includes a mode selecting switch S1 for receiving a mode selecting signal input by a user, a first delay circuit unit 11 and a second delay circuit unit 12 for delaying the mode selecting signal, respectively, and a first signal processing circuit unit 13 and a second signal processing circuit unit 14 for shaping a waveform of the mode selecting signal, an input terminal of the mode selecting switch S1 is connected to a first dc power source VCC, and an output terminal of the mode selecting switch S1 is connected to input terminals of the first delay circuit unit 11 and the second delay circuit unit 12, respectively; the output end of the first delay circuit unit 11 is connected with the input end of the first signal processing circuit unit 13; the output end of the first signal processing circuit unit 13 is connected with the reset end of the control chip 200; the output end of the second signal processing circuit unit 14 is connected to the first I/O port TDO of the control chip 200; wherein the content of the first and second substances,
the delay action time of the first delay circuit unit 11 is shorter than that of the second delay circuit unit 12, so as to trigger the first signal processing circuit unit 13 and/or the second signal processing circuit unit 14 to act according to the mode selection signal and guide the control chip 200 to enter a corresponding selection mode.
In this embodiment, the mode selection switch S1 is a self-reset switch, and a user can output different key signals by long pressing or short pressing, that is, the mode selection switch S1, and optionally, the delay action time of the first delay circuit unit 11 is 10 to 20ms, and the delay action time of the second delay circuit unit 12 is 100 to 500 ms. In order to avoid noise in the output waveform of the mode selection signal due to jitter when the mode selection switch S1 is pressed, the first signal processing circuit unit 13 and the second signal processing circuit unit 14 perform shaping processing on the input mode selection signal. The output terminal of the first signal processing circuit unit 13 is connected to the reset terminal of the control chip 200, and the output terminal of the second signal processing circuit unit 14 is connected to the first I/O port TDO of the control chip 200, that is, a serial port download (program download) interface, and the control chip 200 can be triggered to enter the program download mode by changing the default level of the first I/O port TDO, for example, in the DSP control chip 200 of the TMS320C28X type, as can be known from table 1, the first default level is a high level, that is, a default Flash write mode, so that the mode selection switch S1 outputs a corresponding mode selection signal to control the level of the first I/O port TDO to be changed from a high level to a low level, that is, the DSP control chip 200 of the TMS320C28X type can enter the program download mode.
Specifically, when the user presses the mode selection switch S1 for a long time, since the delay action time of the first delay circuit unit 11 is shorter than the delay action time of the second delay circuit unit 12, the first delay circuit unit 11 operates first, and the mode selection signal is shaped by the first signal processing circuit unit 13 and then output to the reset terminal RS of the control chip 200, so as to trigger the reset of the control chip 200. Then, the second delay circuit unit 12 operates, shapes the mode selection signal through the second signal processing circuit unit 14, and outputs the shaped mode selection signal to the first I/O port TDO of the control chip 200, so that the level of the first I/O port TDO is changed from a high level to a low level, and the control chip 200 is triggered to enter the program downloading mode.
It is understood that, in the above embodiment, the mode directing circuit 10A directs the control chip 200 to enter different modes by outputting the mode selection signal to the reset terminal RS of the control chip 200 and the first I/O port TDO, and the level of the first I/O port TDO defaults to the high level.
Referring to fig. 3, based on the first embodiment of the mode directing circuit 10A, in an embodiment of the first delay circuit unit 11, the first delay circuit unit 11 includes a first resistor R1 and a first capacitor C1, a first end of the first resistor R1 is an input end of the first delay circuit unit 11, a second end of the first resistor R1 is an output end of the first delay circuit unit 11, and is connected to a first end of the first capacitor C1; the second terminal of the first capacitor C1 is grounded.
In this embodiment, the first resistor R1 and the first capacitor C1 form an RC delay circuit, when the mode selection switch S1 is pressed for a long time or a short time, the first capacitor C1 in the first delay circuit unit 11 is momentarily short-circuited when the mode selection switch S1 is pressed, the level of the mode selection signal is pulled down to ground, and then the mode selection signal is charged through the first resistor R1 until the mode selection signal is fully charged, so as to perform a delay process on the mode selection signal, and the delay action time T of the first delay circuit unit 11 is calculated according to the formula (1):
T＝RC；(1)
wherein R is the resistance of the first resistor R1, and C is the capacitance of the first capacitor C1, so that the delay action time of the first delay circuit unit 11 can be adjusted by adjusting the resistance of the first resistor R1 and/or the capacitance of the first capacitor C1.
Referring to fig. 3, based on the first embodiment of the above mode directing circuit 10A, the second delay circuit unit 12 includes a second resistor R2, a third resistor R3 and a second capacitor C2, a first end of the second resistor R2 is interconnected with a second end of the first resistor R1 and a first end of the third resistor R3, a second end of the second resistor R2 is an output end of the second delay circuit unit 12 and is connected with a first end of the second capacitor C2; the second end of the second capacitor C2 and the second end of the third resistor R3 are both grounded.
In this embodiment, the first resistor R1 and the third resistor R3 divide the voltage to output the mode selection signal, and according to the voltage division principle, the larger the ratio between the first resistor R1 and the second resistor R2 is, the larger the voltage divided across the first resistor R1 is, that is, the larger the voltage across the second resistor R2 is. The second resistor R2 and the second capacitor C2 form an RC delay circuit. When the mode selection switch S1 is pressed for a short time, since the delay action of the second delay circuit unit 12 is set to be longer, the selection mode signal disappears before the delay action thereof is ended, and is not output to the second signal processing circuit unit 14. When the mode selection switch S1 is pressed for a long time, the second capacitor C2 in the second delay circuit unit 12 is momentarily short-circuited when the mode selection switch S1 is pressed, the level of the mode selection signal is pulled down to the ground, and then the mode selection signal is charged through the second resistor R2 until the mode selection signal is fully charged, so as to perform delay processing on the mode selection signal, and the delay action time T of the second delay circuit unit 12 is calculated according to the formula (1):
T＝RC；(1)
wherein R is the resistance of the second resistor R2, and C is the capacitance of the second capacitor C2, so that the delay action time of the second delay circuit unit 12 can be adjusted by adjusting the resistance of the second resistor R2 and/or the capacitance of the second capacitor C2.
Referring to fig. 3, further, based on the first embodiment of the above mode directing circuit 10A, the first signal processing circuit unit 13 includes a first schmitt trigger U1 and a third capacitor C3, an input terminal of the first schmitt trigger U1 is an input terminal of the first signal processing circuit unit 13, and an output terminal of the first schmitt trigger U1 is an output terminal of the first signal processing circuit unit 13 and is connected to a first terminal of the third capacitor C3; the second terminal of the third capacitor C3 is grounded.
In this embodiment, the first schmitt trigger U1 performs inverse shaping on the waveform of the input mode selection signal and outputs the waveform to the reset terminal RS of the control chip 200, and the third capacitor C3 is a delay filter capacitor for filtering the mode selection signal output by the first schmitt trigger U1.
Referring to fig. 3, further, based on the first embodiment of the mode directing circuit 10A, the second signal processing circuit unit 14 includes a second schmitt trigger U2 and a fourth resistor R4, an input terminal of the second schmitt trigger U2 is an input terminal of the second signal processing circuit unit 14, and an output terminal of the second schmitt trigger U2 is connected to a first terminal of the fourth resistor R4; a second terminal of the fourth resistor R4 is an output terminal of the second signal processing circuit unit 14.
In this embodiment, the second schmitt trigger U2 performs inverse shaping on the waveform of the input mode selection signal and outputs the waveform to the first I/O port TDO of the control chip 200, and the fourth resistor R4 is a current-limiting resistor for preventing the control chip 200 from being damaged by an excessive current output to the first I/O port TDO of the control chip 200.
Referring to fig. 3, based on the first embodiment of the above-mentioned mode directing circuit 10A, in a further embodiment of the present invention, the mode directing circuit 10A further includes a mode selection display unit (not labeled) for displaying a user selection mode, the mode selection unit includes a first LED lamp D1, a second LED lamp D2, a fifth resistor R5 and a sixth resistor R6, anodes of the first LED lamp D1 and the first LED lamp D1 are both connected to the first direct current power VCC, and a cathode of the first LED lamp D1 is connected to an output terminal of the first signal processing circuit unit 13 through the fifth resistor R5; the cathode of the second LED lamp D2 is connected to the second signal processing circuit unit 14 via the sixth resistor R6.
In this embodiment, the first LED lamp D1 and the fifth resistor R5 form the first selection mode display unit 15, wherein the fifth resistor R5 is a pull-down resistor, and when the level of the mode selection signal output by the first signal processing circuit unit 13 is low, that is, when the cathode of the first LED lamp D1 is low, the first LED lamp D1 is turned on to indicate that the control chip 200 enters a program RUN (RUN) mode after being reset at this time.
The second LED lamp D2 and the sixth resistor R6 form the second selection mode display unit 16, wherein the sixth resistor R6 is a pull-down resistor, and the second LED lamp D2 is turned on when the level of the mode selection signal output by the second signal processing circuit unit 14 is low, that is, when the cathode of the second LED lamp D2 is low, so as to indicate that the control chip 200 enters a program download (SCI) mode at this time.
Referring to fig. 4, a second embodiment of the mode directing circuit 10B of the present invention is proposed, in which the mode directing circuit 10B includes a mode selecting switch SW1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10 for receiving a mode selecting signal input by a user, a first input terminal and a second input terminal of the mode selecting switch SW1 are grounded, and a first output terminal of the mode selecting switch SW1 is interconnected with the first I/O port TDO of the control chip 200 and a first terminal of the ninth resistor R9 via the seventh resistor R7; a second output terminal of the mode selection switch SW1 is interconnected with a first terminal of a second I/O port GPI/O34 and the tenth resistor R10 of the control chip 200 through the eighth resistor R8; the second end of the ninth resistor R9 and the second end of the tenth resistor R10 are both connected to a first dc power source VCC.
In this embodiment, the mode selection switch SW1 is a two-bit binary dial switch, the ninth resistor R9 and the tenth resistor R10 are pull-up resistors, and when the switch state of the two-bit binary dial switch is ON, that is, when one end of the switch is grounded, the seventh resistor R7 and the ninth resistor R9, and the eighth resistor R8 and the tenth resistor R10 form a series voltage division circuit, respectively. As can be seen from table 1, the level flipping of the first I/O port TDO and the second I/O port GPI/O34 can be realized by changing the switches of the dial switches, so as to direct the control chip 200 to enter different modes.
Referring to fig. 4, based on the above embodiment, in a further embodiment of the present invention, the intelligent interface circuit further includes a reset circuit 30 for controlling the control chip 200 to reset, where the reset circuit 30 includes a reset key S2, a thirteenth resistor R13 and a fourth capacitor C4, a first conduction terminal of the reset key S2 is grounded, and a second conduction terminal of the reset key S2 is interconnected with the reset terminal of the control chip 200, a first terminal of the thirteenth resistor R13 and a first terminal of the fourth capacitor C4; a second end of the thirteenth resistor R13 is connected to a first dc power source VCC; the second end of the fourth capacitor C4 is grounded.
It can be understood that in this embodiment, the reset terminal RS of the control chip 200 is in a high level by default, that is, the control chip 200 adopts a low level reset, and when the reset key S2 is pressed, the reset terminal RS of the control chip 200 is pulled low to start resetting. The RC delay circuit formed by the thirteenth resistor R13 and the fourth capacitor C4 is used for controlling the reset time of the control chip 200.
Referring to fig. 5, in a preferred embodiment, the communication interface circuit 20 includes a USB interface J1, a forwarding chip U3, an eleventh resistor R11 and a twelfth resistor R12, wherein a first data terminal of the USB interface J1 is connected to a USB signal input pin of the forwarding chip U3 via the eleventh resistor R11; the second data terminal of the USB interface J1 is connected with the USB signal output pin of the adapter chip U3 through the twelfth resistor R12; a serial data input pin of the switching chip U3 is connected with a signal receiving terminal RX of the control chip 200; the serial data output pin of the switching chip U3 is connected to the signal transmission terminal TX of the control chip 200.
In this embodiment, the USB interface J1 is used for the communication connection between the upper computer 100 and the control chip 200, the power pin of the USB interface J1 obtains 5V power supply voltage from the upper computer 100 and outputs the voltage to the switching chip U3, to supply power to the communication interface circuit 20, the switching chip U3 preferably uses the CH340G serial port switching chip U3, the switching chip U3 is used to implement USB switching, in a serial port mode, the switching chip U3 provides a common MODEM connection signal, which is used to extend an asynchronous serial port for the upper computer 100, or upgrade a control serial port to a USB bus, thereby implementing the communication between the upper computer 100 and the control chip 200.
In the above embodiment, the communication interface circuit 20 further includes a zener diode ZD1, a crystal oscillator Y1, capacitors C5, C6, C7, C8, and a fuse FU1, a cathode of the zener diode ZD1 is connected to a power pin of the USB interface J1, and an anode of the zener diode ZD1 is grounded. The protective tube FU1 is serially connected between the power pin of the USB interface J1 and the power supply terminal VCC1 of the upper computer. The crystal oscillator Y1 is arranged in parallel at two ends of the clock pin of the adapter chip U3. The capacitor C5 is serially connected between the first dc power VCC and the power pin of the adaptor chip. One end of the capacitor C7 is connected with the crystal oscillator Y1, and the other end of the capacitor C7 is grounded. One end of the capacitor C8 is connected with the crystal oscillator Y1, and the other end of the capacitor C8 is grounded.
It should be noted that, generally, the control chips 200 all have one or more serial interfaces, and when the control chip 200 has multiple serial interfaces, the program download and the communication between external chips can be simultaneously implemented, for example, in an air conditioner, the communication between the control chip 200 of the drive board and the control chip 200 of the main control board. When the control chip 200 has only one serial interface, if the driver chip and/or the control chip 200 needs to be upgraded, the shorting bar J2 needs to be configured to realize program downloading, and when the program downloading is completed, the shorting bar J2 is disconnected to recover the communication between the control chip 200.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. An intelligent interface circuit is used for realizing control chip program downloading in electrical equipment and is characterized in that the intelligent interface circuit comprises a mode guide circuit and a communication interface circuit, wherein the input end of the mode guide circuit is used for receiving a mode selection signal input by a user, and the output end of the mode guide circuit is connected with an I/O port of a control chip; the first signal transmission end of the communication interface circuit is connected with the upper computer; the second signal transmission end of the communication interface circuit is connected with the signal sending/receiving end of the control chip; wherein the content of the first and second substances,
the mode guide circuit is used for receiving a mode selection signal input by a user and outputting the mode selection signal to the control chip so as to guide the control chip to enter a mode selected by the user; the selection mode comprises a program running mode, a burning mode and a serial port downloading mode;
the communication interface circuit is used for connecting and communicating the upper computer and the control chip under the serial port downloading mode so as to enable the control chip to obtain a corresponding program from the upper computer;
the mode guiding circuit comprises a mode selection switch, a first delay circuit unit, a second delay circuit unit, a first signal circuit processing unit and a second signal processing circuit unit, wherein the mode selection switch is used for receiving a mode selection signal input by a user, the first delay circuit unit and the second delay circuit unit are used for delaying the mode selection signal respectively, the first signal circuit processing unit and the second signal processing circuit unit are used for shaping the waveform of the mode selection signal, the input end of the mode selection switch is connected with a first direct-current power supply VCC, and the output end of the mode selection switch is connected with the input ends of the first delay circuit unit and the second delay circuit unit respectively; the output end of the first delay circuit unit is connected with the input end of the first signal processing circuit unit; the output end of the first signal processing circuit unit is connected with the reset end of the control chip; and the output end of the second signal processing circuit unit is connected with the first I/O port of the control chip.
2. The intelligent interface circuit according to claim 1, wherein the delay action time of the first delay circuit unit is shorter than that of the second delay circuit unit, so as to trigger the first signal circuit processing unit and/or the second signal processing circuit unit to act according to the mode selection signal and guide the control chip to enter the corresponding selection mode.
3. The intelligent interface circuit according to claim 2, wherein the first delay circuit unit comprises a first resistor and a first capacitor, a first end of the first resistor is an input end of the first delay circuit unit, and a second end of the first resistor is an output end of the first delay circuit unit and is connected to a first end of the first capacitor; the second end of the first capacitor is grounded.
4. The intelligent interface circuit according to claim 3, wherein the second delay circuit unit comprises a second resistor, a third resistor and a second capacitor, a first end of the second resistor is interconnected with a second end of the first resistor and a first end of the third resistor, and a second end of the second resistor is an output end of the second delay circuit unit and is connected with a first end of the second capacitor; and the second end of the second capacitor and the second end of the third resistor are both grounded.
5. The intelligent interface circuit according to claim 2, wherein the first signal processing circuit unit comprises a first schmitt trigger and a third capacitor, an input terminal of the first schmitt trigger is an input terminal of the first signal processing circuit unit, and an output terminal of the first schmitt trigger is an output terminal of the first signal processing circuit unit and is connected to a first terminal of the third capacitor; and the second end of the third capacitor is grounded.
6. The intelligent interface circuit according to claim 2, wherein the second signal processing circuit unit comprises a second schmitt trigger and a fourth resistor, an input terminal of the second schmitt trigger is an input terminal of the second signal processing circuit unit, and an output terminal of the second schmitt trigger is connected to a first terminal of the fourth resistor; and the second end of the fourth resistor is the output end of the second signal processing circuit unit.
7. The intelligent interface circuit according to claim 2, wherein the mode guidance circuit further comprises a mode selection display unit for displaying a user selection mode, the mode selection display unit comprising a first LED lamp, a second LED lamp, a fifth resistor and a sixth resistor, the anodes of the first LED lamp and the first LED lamp are connected to the first dc power supply, and the cathode of the first LED lamp is connected to the output terminal of the first signal processing circuit unit via the fifth resistor; and the cathode of the second LED lamp is connected with the second signal processing circuit unit through the sixth resistor.
8. The intelligent interface circuit according to claim 1, wherein the communication interface circuit comprises a USB interface, a switching chip, an eleventh resistor and a twelfth resistor, and a first data terminal of the USB interface is connected to a USB signal input pin of the switching chip via the eleventh resistor; the second data end of the USB interface is connected with the USB signal output pin of the switching chip through the twelfth resistor; the serial data input pin of the switching chip is connected with the signal receiving end of the chip; and a serial data output pin of the switching chip is connected with the signal transmitting end.
9. The intelligent interface circuit according to claim 1, further comprising a reset circuit for controlling the reset of the control chip, wherein the reset circuit comprises a reset button, a thirteenth resistor and a fourth capacitor, a first conducting terminal of the reset button is grounded, and a second conducting terminal of the reset button is interconnected with the reset terminal of the control chip, a first terminal of the thirteenth resistor and a first terminal of the fourth capacitor; the second end of the thirteenth resistor is connected with a first direct current power supply; and the second end of the fourth capacitor is grounded.
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| CN201710718059.8A CN108197047B (en) | 2017-08-18 | 2017-08-18 | Intelligent interface circuit |
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| EP0954797A1 (en) * | 1995-12-08 | 1999-11-10 | Bell Communications Research, Inc. | Method and system for placing advertisements in a computer network |
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| CN202454228U (en) * | 2011-12-26 | 2012-09-26 | 青岛海信电器股份有限公司 | Liquid crystal display screen parameter selection circuit and television |
| US20140312928A1 (en) * | 2013-04-19 | 2014-10-23 | Kool Chip, Inc. | High-Speed Current Steering Logic Output Buffer |
| CN103336700B (en) * | 2013-06-09 | 2016-08-10 | 深圳市汇川技术股份有限公司 | The serial ports programming circuitry of a kind of digital signal processor and system |
| CN205372918U (en) * | 2015-12-18 | 2016-07-06 | 马爽 | Controller of intelligent air -conditioner |
| CN205384601U (en) * | 2016-02-01 | 2016-07-13 | 湖南铁道职业技术学院 | Singlechip downloader |
| CN106452995A (en) * | 2016-09-26 | 2017-02-22 | 上海电机学院 | WiFi remote control module |
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| EP0954797A1 (en) * | 1995-12-08 | 1999-11-10 | Bell Communications Research, Inc. | Method and system for placing advertisements in a computer network |
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