CN108196945A - A kind of communication method between cores, device and virtual equipment - Google Patents
A kind of communication method between cores, device and virtual equipment Download PDFInfo
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- CN108196945A CN108196945A CN201611122215.6A CN201611122215A CN108196945A CN 108196945 A CN108196945 A CN 108196945A CN 201611122215 A CN201611122215 A CN 201611122215A CN 108196945 A CN108196945 A CN 108196945A
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- notification message
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
Abstract
The embodiment of the present application provides a kind of communication method between cores, device and virtual equipment, this method is applied in virtual equipment, first assembly is run in the virtual equipment, the second component is built by virtualization in the first assembly, the method includes：The information of multiple virtual processors is notified first assembly by the second component；First assembly obtains the information of the multiple virtual processor；First assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.By the way that the information of virtual processor disposably is notified first assembly, greatly reduce the number of communications between the second component and first assembly, and then greatly reduce the number exited of the second component caused by the communication between the second component and first assembly, during a multicast, the number that second component exits is as little as primary, so as to reduce taking for intercore communication, the performance of the second component and first assembly is promoted.
Description
Technical field
This application involves the technical fields of virtualization, are filled more particularly to a kind of communication method between cores, a kind of intercore communication
It puts and a kind of virtual equipment.
Background technology
In the IaaS (Infrastructure as a Service, infrastructure service) of cloud computing, cloud operator
Physical machine, virtual machine and other facilities of trustship are provided, are used for different users according to the actual needs of oneself.
Virtual machine (Virtual Machine) service is one of kernel service of IaaS, refers to system virtual machine, you can with
It is being simulated, there is complete hardware system, operate in the complete computer in a completely isolated environment.
At present, processor generally has multiple cores, is carried out between processor (core) and processor (core) frequently by interruption
Communication, a processor (core) are referred to as internuclear to the interruption of another or multiple processors (core) (can include itself) transmission
It interrupts (Inter-Processor Interrupts, IPI), the mode that internuclear interruption is sent to multiple processors (core) is also referred to as
Multicast.
For example, each processor has TLB (Translation Lookaside Buffer transmit look-aside buffer),
I.e. to the buffering of page table mapping, if the thread on some processor is modified page table content, then on other processors
TLB just fail, at this time, it is necessary to notify other processors refresh TLB.
In virtualization, because it is not the notice between original physical processor that virtual machine, which sends IPI, but virtual processing
Notice between device.
But virtual processor and physical processor are not one-to-one fixed relationship, so locating when some is virtual
When reason device notifies other virtual processors, initiation is exited, and notifies first assembly, allows first assembly to help the virtual processor real
This existing notice.
For exiting the purpose processor generally equal to sent that a current multicast IPI causes in the processor of transmission
Number, it is more to exit number.
It needs to carry out a large amount of state preservation and switch operating when virtual machine exits, is again introduced into virtualization state and is also required to
Restore these states, so, exiting for virtual machine is cumbersome, it is more to take.
Invention content
In view of the above problems, it is proposed that the embodiment of the present application overcomes the above problem or at least partly in order to provide one kind
A kind of communication method between cores, a kind of intercore communication device and a kind of virtual equipment to solve the above problems.
To solve the above-mentioned problems, the embodiment of the present application discloses a kind of communication method between cores, applies in virtual equipment
In, first assembly is run in the virtual equipment, the second component is built by virtualization in the first assembly, it is described
Method includes：
The information of multiple virtual processors is notified first assembly by the second component；
First assembly obtains the information of the multiple virtual processor；
First assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.
The embodiment of the present application also discloses a kind of intercore communication device, applies in virtual equipment, in the virtualization
First assembly is run in equipment, the second component is built by virtualization in the first assembly, wherein,
Second component includes：
Information notification module, for the information of multiple virtual processors to be notified host；
The first assembly includes：
Data obtaining module, for obtaining the information of the multiple virtual processor；
Internuclear interruption sending module is believed for sending internuclear interrupt to the multiple virtual processor according to described information
Number.
The embodiment of the present application also discloses a kind of virtual equipment, including：
Multiple processors；
Memory；With
One or more modules, one or more of modules are stored in the memory and are configured to by described one
A or multiple processors perform, wherein, first assembly is run in the virtual equipment, passes through void in the first assembly
Planization builds the second component, and the multiple processor is configured as：
The information of multiple virtual processors is notified first assembly by the second component；
First assembly obtains the information of the multiple virtual processor；
First assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.
The embodiment of the present application includes advantages below：
In the embodiment of the present application, the information of multiple virtual processors is notified first assembly by the second component, and first assembly is pressed
Internuclear interrupt signal is sent to multiple virtual processors according to the information, by the way that the information of virtual processor disposably is notified first
Component greatly reduces the number of communications between the second component and first assembly, and then greatly reduces because of the second component and first
The number exited of second component caused by communication between component, during a multicast, the second component exits secondary
Number is as little as primary, so as to reduce taking for intercore communication, promotes the performance of the second component and first assembly.
Description of the drawings
Fig. 1 is a kind of step flow chart of communication method between cores embodiment of the application；
Fig. 2 is a kind of configuration diagram of virtual equipment of the application；
Fig. 3 is the step flow chart of another communication method between cores embodiment of the application；
Fig. 4 A are a kind of intercore communication exemplary plots provided by the embodiments of the present application；
Fig. 4 B are another intercore communication exemplary plots provided by the embodiments of the present application；
Fig. 5 is a kind of structure diagram of intercore communication device embodiment of the application；
Fig. 6 is the structure diagram of another intercore communication device embodiment of the application；
Fig. 7 is a kind of virtual equipment structure diagram provided by the embodiments of the present application.
Specific embodiment
Above-mentioned purpose, feature and advantage to enable the application are more obvious understandable, below in conjunction with the accompanying drawings and specific real
Mode is applied to be described in further detail the application.
With reference to Fig. 1, a kind of step flow chart of communication method between cores embodiment of the application is shown.
In the concrete realization, as shown in Fig. 2, the embodiment of the present application can be applied in virtual equipment 200, the virtualization
Equipment 200 be physical equipment, be deployed in virtual equipment 200 multiple processors (Central Processing Unit,
CPU), the hardware resources such as memory, network equipment storage device.
Run on the basis of virtually in general, virtualization is value computer components, with logical expressions resource, by
200 addition virtualization layer on virtual equipment, so as to fulfill virtualization, such as virtualization processor, Virtual Memory Manager
(Memory Management Unit, MMU) and virtual i/o system etc..Virtualization layer encapsulates lower resource, is abstracted as another
A form of resource, is supplied to upper strata to use.A resource can be abstracted as more parts by virtualization, can also be by more parts of resources
It is abstracted into portion.
First assembly 210, i.e. system where virtual platform are run in 200 on virtual equipment, in first assembly
Second component 220 is built by virtualization on 210, is separately operable multiple and different or identical operating system.
In an example of the embodiment of the present application, first assembly 210 can be that host, the second component 220 can be
Operate in the virtual machine on host, also referred to as client computer, such as Hyper-V, Xen, KVM (Kernel-based Virtual
Machine), Vmware etc..
Second component 220 (such as client computer) is the independent computer system provided by virtualization layer, possesses the void of oneself
Intend hardware (CPU, memory, the network equipment, storage device etc.), for upper strata, the second component 220 (such as client computer) is exactly true
It calculates, from the point of view of application program, program is operated on the second component 220 (such as client computer) with operating in first assembly 210
Being on (such as host).
In the concrete realization, a kind of mode of virtualization is half virtualization (Paravirtualization, PV), that is, is used
Hypervisor (virtual machine management program) shares the hardware resource of access bottom, fictionalizes the framework come and physical structure one
It causes, usually changes the kernel of the second component 220 (such as client computer), then realize and Hypervisor (virtual machines are transmitted to regard to request
Management program), Hypervisor (virtual machine management program) is allowed to return again to (hyper call) to the second component 220 after performing
(such as client computer).
This method specifically may include steps of：
Step 101, the information of multiple virtual processors is notified first assembly by the second component.
Second component can be inquired in the internuclear interruption of demand as communication object (object for sending internuclear interruption)
The information of virtual processor, and notify first assembly, first assembly is allowed to send internuclear interruption.
In one example, the information of virtual processor can be bitmap (bitmap), each data can represent one
A virtual processor as communication object, it is 1 virtual processor for being denoted as communication object such as to set bit, and setting bit is
0 represents the virtual processor not as communication object.
Certainly, the information of virtual processor can also be indicated using other forms, and the embodiment of the present application is not added with this
With limitation.
In one embodiment of the application, step 101 can include following sub-step：
Sub-step S11, the second component generation simulation register；
Sub-step S12, the second component generate the first notification message, and first notification message includes multiple virtual processing
The information of device；
Sub-step S13, the simulation register is written in first notification message by the second component, to notify first group
Part.
Register is simulated, is register (the machine specific realized under virtualization by the form of program
Register, MSR), simulation register is usually used to the communication done between the second component and first assembly, when the second component is grasped
When making this simulation register, it can cause and exit so that the first notification message can be reached at first assembly and be handled.
In the embodiment of the present application, one or more MSR can be simulated, one or more simulation registers are obtained, to expand
The data volume of big first notification message supports more processors (core).
For example, 0x830MSR can be simulated, by the use of its high 32 as bitmap, 32 cores can be supported.
In another example individually simulation 0x830MSR is bitmap, work together, one MSR of simulation is bitmap, and a MSR has 64
Position is 32 high plus 0x830MSR's, obtains 96 altogether, can support 96 cores.
If it should be noted that the quantity of virtual processor be more than it is single simulation the open ended data volume of register,
Then can first assembly be notified by write operation twice or more than twice, still, writing simulation register every time can cause and exit.
For example, the quantity of virtual processor is 128 cores, and 96bit can be accommodated by simulating register single, then can be passed through
One time bitmap, the bitmap of 32 of 96 writes simulation register, i.e., is led to by writing the operation of simulation register twice
Know first assembly, cause exiting twice for the second component.
In another embodiment of the application, step 101 can include following sub-step：
Sub-step S21, the second component application shared drive, and notify first assembly；
In the concrete realization, the second component can apply for one page shared drive in the memory of virtual machine, the second component and
First assembly can be written and read operation in the shared drive.
Second component and operation of the first assembly to shared drive, may be used atomic operation (atomic
Operation), i.e., the operation that will not be interrupted by thread scheduling mechanism, it is this operation once, just run to ends, centre
It does not have and context switch (being switched to another thread) occurs, which includes but not limited to XCHG (registers
The exchange instruction of content between memory variable) etc..
It should be noted that can run multiple second components in same first assembly, each second component can be with
The shared drive in its memory.
It, can be by writing MSR (machine specific register) after the success of second component application shared drive
Initiation such as exits at the modes, the base address of the shared drive is sent to first assembly so that first assembly can be according to the base
Location accesses the shared drive.
Hereafter, the second component and first assembly will parse this shared drive with same data structure, with shared void
Intend the information of processor.
The shared drive is written in the information of multiple virtual processors by sub-step S22, the second component；
Before internuclear interruption is sent, the second component will send the information (such as bitmap) of the virtual processor of internuclear interruption
It is written in shared drive, so that first assembly can be read.
It should be noted that the write operation of shared drive, will not cause exiting for the second component.
Sub-step S23, the second component generation second notification message simultaneously notify first assembly.
In the embodiment of the present application, it can notify first assembly by way of writing physical register (writing MSR), also may be used
To notify first assembly by other means.
Wherein, physical register refers to there is true register on physical processor, which is grasped into row write
Work can cause exiting for the second component, so that the second notification message reaches first assembly, notice first assembly is in sharing
The middle information (such as bitmap) for obtaining virtual processor is deposited, and then completes the transmission of internuclear interruption.
Certainly, the mode of the information of above-mentioned notice virtual processor is intended only as example, when implementing the embodiment of the present application,
The mode of the information of other notice virtual processors can be set according to actual conditions, and the embodiment of the present application does not limit this
System.In addition, other than the mode of the information of above-mentioned notice virtual processor, those skilled in the art can also be according to actual needs
By the way of the information of other notice virtual processors, the embodiment of the present application does not also limit this.
Step 102, first assembly obtains the information of the virtual processor.
After the information for needing the virtual processor for sending internuclear interruption is notified first assembly by the second component, first assembly
The information that corresponding mode obtains virtual processor may be used, and then send internuclear interruption.
In one embodiment of the application, step 102 can include following sub-step：
Sub-step S31, first assembly recognize the first mark of half virtualization intercore communication from first notification message
Know；
Sub-step S32, first assembly read the multiple virtual according to the first flag from first notification message
The information of processor.
In the embodiment of the present application, if the second component is by simulating register by the information of virtual processor (such as
Bitmap first assembly) is notified, then first assembly receives the first notification message by simulating register.
It is operated accordingly for the ease of notice first assembly, the second component disappears in the first notice for writing simulation register
During breath, the reserved bit in MSR information formats can be utilized, such as the 31st of ICR (interrupt control register), the first mark of write-in
Know, represent half virtualization intercore communication.
First assembly can virtualize after identifying that the expression half virtualizes the first flag of intercore communication according to half
The specification that intercore communication is made an appointment reads the information (such as bitmap) of virtual processor from the first notification message.
In another embodiment of the application, step 102 can include following sub-step：
Sub-step S41, first assembly recognize the second mark of half virtualization intercore communication from the second notification message
Know；
Sub-step S42, first assembly read from the shared drive according to the second identifier it is the multiple it is virtual from
Manage the information of device.
In the embodiment of the present application, if the second component by shared drive by the information (such as bitmap) of virtual processor
Notify first assembly, then first assembly receives second notification message by physical register.
It is operated accordingly for the ease of notice first assembly, the second component disappears in the second notice for writing physical register
During breath, the reserved bit in MSR information formats can be utilized, such as the 31st of ICR (interrupt control register), the second mark of write-in
Know, represent half virtualization intercore communication.
First assembly can virtualize after identifying that the expression half virtualizes the second identifier of intercore communication according to half
The specification that intercore communication is made an appointment reads the information of virtual processor (such as from the shared drive of second component
bitmap)。
Certainly, the mode of the information of above-mentioned acquisition virtual processor is intended only as example, when implementing the embodiment of the present application,
The mode that other can be set to obtain the information of virtual processor according to actual conditions, the embodiment of the present application do not limit this
System.In addition, other than the mode of the information of above-mentioned acquisition virtual processor, those skilled in the art can also be according to actual needs
By the way of other information for obtaining virtual processor, the embodiment of the present application does not also limit this.
Step 103, first assembly sends internuclear interrupt signal according to described information to the virtual processor.
In the concrete realization, first assembly safeguards the correspondence between virtual processor and physical processor.
First assembly can know the virtual processor as communication object according to the information (such as bitmap), according to virtual
Correspondence between processor and physical processor inquires physical processor where the virtual processor, is sent out by hardware
The signal of internuclear interruption is sent to the physical processor, to notify the virtual processor.
At present, for the processor of the frameworks such as x2apic, sending internuclear interruption, there are two types of address pattern, Yi Zhongshi
Physical (physics), another kind are cluster (clusters).
If sending internuclear interruption using physical patterns, during a multicast, internuclear interruption is being sent
The second component caused on processor exits number, equal with receiving the quantity of processor of internuclear interruption.
If sending internuclear interruption using cluster patterns, IOMMU (input/output memory are needed
Management unit, input/output memory management unit) hardware carry out interrupt remap, can not in the environment of virtualization
IOMMU hardware is simulated, therefore, can not IPI be sent by using cluster patterns in the environment of virtualization.
Even if realizing the simulation of IOMMU hardware, during a multicast, on the processor for sending internuclear interruption
The second component caused exits number, equal with the quantity of the cluster belonging to the processor for receiving internuclear interruption.
In the embodiment of the present application, the information of multiple virtual processors is notified first assembly by the second component, and first assembly is pressed
Internuclear interrupt signal is sent to multiple virtual processors according to the information, by the way that the information of virtual processor disposably is notified first
Component greatly reduces the number of communications between the second component and first assembly, and then greatly reduces because of the second component and first
The number exited of second component caused by communication between component, during a multicast, the second component exits secondary
Number is as little as primary, so as to reduce taking for intercore communication, promotes the performance of the second component and first assembly.
With reference to Fig. 3, show the step flow chart of another communication method between cores embodiment of the application, apply virtual
Change in equipment, first assembly is run in the virtual equipment, by virtualizing second group of structure in the first assembly
Part, the method specifically may include steps of：
Step 301, whether the second component queries first assembly supports half virtualization intercore communication.
Step 302, the second component is when knowing that first assembly supports half virtualization intercore communication, notice first assembly, institute
It states the second component and supports half virtualization intercore communication.
Step 303, the information of multiple virtual processors is notified first assembly by the second component.
Step 304, first assembly obtains the information of the multiple virtual processor.
Step 305, first assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.
Since the system version of the second component and first assembly is not necessarily constant, half virtualization intercore communication is not all supported
(PV-IPI), therefore, the second component is before the specification setting timer using half virtualization intercore communication (PV-IPI), can be with
It is synchronous that characteristic is carried out with first assembly.
It in the concrete realization, can if the second component supports the characteristic of half virtualization intercore communication (PV-IPI) in itself
Whether to support the characteristic of half virtualization intercore communication (PV-IPI) using cpuid instruction inquiry first assembly.
If the second component knows that first assembly supports the characteristic of half virtualization intercore communication (PV-IPI), the second component can
First assembly is notified in a manner of by writing register MSR, this second component supports half virtualization intercore communication (PV-IPI)
Characteristic can subsequently be timed the setting of device according to half virtualization intercore communication (PV-IPI).
Wherein, half virtualization (Paravirtualization, PV) refers to need to make an amendment the second component operating system
Or some virtualized natures that the cooperation of the second component operating system is needed to complete.
It should be noted that half virtualization intercore communication (PV-IPI) can refer to the hair of intercore communication in the embodiment of the present application
Delivery method, such as step 101- steps 103, step 301-305, etc., related part referring to communication method between cores embodiment portion
It defends oneself bright, is not described in detail herein.
In addition, if the second component or any feature for not supporting half virtualization intercore communication of first assembly, then can lead to
It crosses other modes and sends intercore communication, the embodiment of the present application does not limit this.
For those skilled in the art is made to more fully understand the embodiment of the present application, illustrate this Shen below by way of specific example
Communication method between cores that please be in embodiment.
As shown in Figure 4 A and 4 B shown in FIG., the system where virtual platform is first assembly 340, is existed in first assembly more
A CPU including CPU_0, CPU_1, CPU_2, CPU_3, runs the second component 420, the second component 420 in first assembly 410
Vcpu_1 correspond to the CPU_0 of first assembly 410, the vcpu_2 of the second component 420 corresponds to the CPU_3 of first assembly 410, second
The vcpu_0 of component 320 corresponds to the CPU_2 of first assembly 410, the vcpu_3 of the second component 420 corresponds to first assembly 410
CPU_1。
As shown in the dotted arrow in Fig. 4 A and Fig. 4 B, in the second component 420, vcpu_1 is intended to send internuclear interruption extremely
vcpu_0、vcpu_2。
In a kind of mode, as shown in Figure 4 A, the second component 420 simulation 0x830MSR generates MSR421, performs step
The bitmap (00000101) of vcpu_0, vcpu_2 are generated a MSR information, and the 31st in ICR is written PV-IPI's by A1
Mark by way of writing 0x830MSR, causes exiting, and the MSR information is sent to first assembly for the second component 320
310。
The 31st mark for identifying PV-IPI of the ICR from MSR information of first assembly 410, according to the specification of PV-IPI,
The bitmap (00000101) of vcpu_0, vcpu_2 are read from the MSR information.
First assembly 410 performs step A2, according to pair between the vcpu of the CPU of first assembly 410 and the second component 420
It should be related to, IPI be sent to CPU_2, CPU_3 from CPU_0, so as to convey vcpu_0, vcpu_2.
In a further mode of operation, as shown in Figure 4 B, step S2 is performed, the second component 420 applies for shared drive 422, and will
Its address notifies first assembly 410, and the second component 420 performs step B1, by the bitmap (00000101) of vcpu_0, vcpu_2
It is written in shared drive 422, performs step B2, generate a MSR information, and the mark of the 31st write-in PV-IPI in ICR, lead to
The mode for writing MSR is crossed, causes exiting, and the MSR information is sent to first assembly 410 for the second component 420.
The 31st mark for identifying PV-IPI of the ICR from MSR information of first assembly 410, according to the specification of PV-IPI,
Step B3 is performed, the bitmap (00000101) of vcpu_0, vcpu_2 are read from shared drive 321.
First assembly 410 performs step B4, according to pair between the vcpu of the CPU of first assembly 410 and the second component 420
It should be related to, IPI be sent to CPU_2, CPU_3 from CPU_0, so as to convey vcpu_0, vcpu_2.
During a multicast, vcpu_1 send simultaneously it is internuclear interrupt to vcpu_0, vcpu_2, only cause one time the
Two components 420 exit.
It should be noted that for embodiment of the method, in order to be briefly described, therefore it is all expressed as to a series of action group
It closes, but those skilled in the art should know, the embodiment of the present application is not limited by described sequence of movement, because according to
According to the embodiment of the present application, certain steps may be used other sequences or be carried out at the same time.Secondly, those skilled in the art also should
Know, embodiment described in this description belongs to preferred embodiment, and involved action not necessarily the application is implemented
Necessary to example.
With reference to Fig. 5, show a kind of structure diagram of intercore communication device embodiment of the application, apply and set in virtualization
In standby, first assembly 510 is run in the virtual equipment, by virtualizing structure second in the first assembly 510
Component 520, wherein,
Second component 520 includes：
Information notification module 521, for the information of multiple virtual processors to be notified first assembly 510；
The first assembly 510 includes：
Data obtaining module 511, for obtaining the information of the multiple virtual processor；
Internuclear interruption sending module 512, for sending internuclear interruption to the multiple virtual processor according to described information
Signal.
In one embodiment of the application, described information notification module 521 includes：
Register analog submodule simulates register for generating；
Notification message generates submodule, and for generating the first notification message, first notification message includes multiple void
Intend the information of processor；
Write simulation register submodule, for will first notification message write-in simulation register, to notify the
One component.
In another embodiment of the application, described information notification module 521 includes：
Shared drive application submodule for applying for shared drive, and notifies first assembly 510；
Shared drive submodule is write, for the information of multiple virtual processors to be written the shared drive；
Notification message notifies submodule, for that will generate second notification message and notify first assembly 510.
In one embodiment of the application, described information acquisition module 511 includes：
First flag identifies submodule, for recognizing the of half virtualization intercore communication from first notification message
One mark；
First information reading submodule, it is the multiple for being read according to the first flag from first notification message
The information of virtual processor.
In another embodiment of the application, described information acquisition module 511 includes：
Second identifier identifies submodule, for recognizing the of half virtualization intercore communication from the second notification message
Two marks；
Second information reading submodule, for reading the multiple void from the shared drive according to the second identifier
Intend the information of processor.
With reference to Fig. 6, show the structure diagram of another intercore communication device embodiment of the application, apply and virtualizing
In equipment, first assembly 610 is run in the virtual equipment, by virtualizing structure the in the first assembly 610
Two components 620, wherein,
Second component 620 includes：
Characteristic supports inquiry module 621, for inquiring whether first assembly 610 supports half virtualization intercore communication；
Characteristic supports notification module 622, for when knowing that first assembly 610 supports half virtualization intercore communication, notifying
First assembly 610, second component 620 support half virtualization intercore communication；
Information notification module 623, for the information of multiple virtual processors to be notified first assembly 610；
The first assembly 610 includes：
Data obtaining module 611, for obtaining the information of the multiple virtual processor；
Internuclear interruption sending module 612, for sending internuclear interruption to the multiple virtual processor according to described information
Signal.
For device embodiment, since it is basicly similar to embodiment of the method, so description is fairly simple, it is related
Part illustrates referring to the part of embodiment of the method.
Fig. 7 is a kind of virtual equipment structure diagram provided by the embodiments of the present application.The virtual equipment 700 can be because matching
It puts or performance is different and generate bigger difference, multiple central processing units (central processing can be included
Units, CPU) 722 (for example, multiple processors) and memory 732, one or more storage application programs 742 or data
744 storage medium 730 (such as one or more mass memory units).Wherein, memory 732 and storage medium 730
Can be of short duration storage or persistent storage.One or more moulds can be included by being stored in the program of storage medium 730
Block (diagram does not mark), each module can include operating the series of instructions in virtual equipment.Further, it is central
Processor 722 could be provided as communicating with storage medium 730, and the system in storage medium 730 is performed on virtual equipment 700
Row instruction operation.
Virtual equipment 700 can also include one or more power supplys 726, one or more are wired or wireless
Network interface 750, one or more input/output interfaces 758, one or more keyboards 756 and/or, one or
More than one operating system 741, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM
Etc..Wherein, central processing unit 722 can perform the following instruction operated on virtual equipment 700：
The information of multiple virtual processors is notified first assembly by the second component；
First assembly obtains the information of the multiple virtual processor；
First assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.
Optionally, central processing unit 722 can also perform the following instruction operated on virtual equipment 700：
Whether the second component queries first assembly supports half virtualization intercore communication；
Second component is when knowing that first assembly supports half virtualization intercore communication, notice first assembly, the second component branch
Hold half virtualization intercore communication.
Optionally, central processing unit 722 can also perform the following instruction operated on virtual equipment 700：
Second component generation simulation register；
Second component generates the first notification message, and first notification message includes the information of multiple virtual processors；
The simulation register is written in first notification message by the second component, to notify first assembly.
Optionally, central processing unit 722 can also perform the following instruction operated on virtual equipment 700：
Second component application shared drive, and notify first assembly；
The shared drive is written in the information of multiple virtual processors by the second component；
Secondth component generates second notification message and notifies first assembly.
Optionally, central processing unit 722 can also perform the following instruction operated on virtual equipment 700：
First assembly recognizes the first flag of half virtualization intercore communication from first notification message；
First assembly reads the letter of the multiple virtual processor according to the first flag from first notification message
Breath.
Optionally, central processing unit 722 can also perform the following instruction operated on virtual equipment 700：
First assembly recognizes the second identifier of half virtualization intercore communication from the second notification message；
First assembly reads the information of the multiple virtual processor according to the second identifier from the shared drive.
Each embodiment in this specification is described by the way of progressive, the highlights of each of the examples are with
The difference of other embodiment, just to refer each other for identical similar part between each embodiment.
It should be understood by those skilled in the art that, the embodiment of the embodiment of the present application can be provided as method, apparatus or calculate
Machine program product.Therefore, the embodiment of the present application can be used complete hardware embodiment, complete software embodiment or combine software and
The form of the embodiment of hardware aspect.Moreover, the embodiment of the present application can be used one or more wherein include computer can
With in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) of program code
The form of the computer program product of implementation.
In a typical configuration, the computer equipment includes one or more processors (CPU), input/output
Interface, network interface and memory.Memory may include the volatile memory in computer-readable medium, random access memory
The forms such as device (RAM) and/or Nonvolatile memory, such as read-only memory (ROM) or flash memory (flash RAM).Memory is to calculate
The example of machine readable medium.Computer-readable medium includes permanent and non-permanent, removable and non-removable media can be with
Realize that information stores by any method or technique.Information can be computer-readable instruction, data structure, the module of program or
Other data.The example of the storage medium of computer includes, but are not limited to phase transition internal memory (PRAM), static RAM
(SRAM), dynamic random access memory (DRAM), other kinds of random access memory (RAM), read-only memory
(ROM), electrically erasable programmable read-only memory (EEPROM), fast flash memory bank or other memory techniques, CD-ROM are read-only
Memory (CD-ROM), digital versatile disc (DVD) or other optical storages, magnetic tape cassette, tape magnetic rigid disk storage or
Other magnetic storage apparatus or any other non-transmission medium, available for storing the information that can be accessed by a computing device.According to
Herein defines, and computer-readable medium does not include the computer readable media (transitory media) of non-standing, such as
The data-signal and carrier wave of modulation.
The embodiment of the present application is with reference to according to the method for the embodiment of the present application, terminal device (system) and computer program
The flowchart and/or the block diagram of product describes.It should be understood that flowchart and/or the block diagram can be realized by computer program instructions
In each flow and/or block and flowchart and/or the block diagram in flow and/or box combination.These can be provided
Computer program instructions are set to all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing terminals
Standby processor is to generate a machine so that is held by the processor of computer or other programmable data processing terminal equipments
Capable instruction generation is used to implement in one flow of flow chart or multiple flows and/or one box of block diagram or multiple boxes
The device for the function of specifying.
These computer program instructions, which may also be stored in, can guide computer or other programmable data processing terminal equipments
In the computer-readable memory to work in a specific way so that the instruction being stored in the computer-readable memory generates packet
The manufacture of command device is included, which realizes in one flow of flow chart or multiple flows and/or one side of block diagram
The function of being specified in frame or multiple boxes.
These computer program instructions can be also loaded into computer or other programmable data processing terminal equipments so that
Series of operation steps are performed on computer or other programmable terminal equipments to generate computer implemented processing, thus
The instruction offer performed on computer or other programmable terminal equipments is used to implement in one flow of flow chart or multiple flows
And/or specified in one box of block diagram or multiple boxes function the step of.
Although the preferred embodiment of the embodiment of the present application has been described, those skilled in the art once know base
This creative concept can then make these embodiments other change and modification.So appended claims are intended to be construed to
Including preferred embodiment and fall into all change and modification of the embodiment of the present application range.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements are not only wrapped
Those elements are included, but also including other elements that are not explicitly listed or are further included as this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, it is wanted by what sentence "including a ..." limited
Element, it is not excluded that also there are other identical elements in the process including the element, method, article or terminal device.
A kind of communication method between cores provided herein, a kind of intercore communication device and a kind of virtualization are set above
It is standby, it is described in detail, the principle and implementation of this application are described for specific case used herein, more than
The explanation of embodiment is merely used to help understand the present processes and its core concept；Meanwhile for the general skill of this field
Art personnel, according to the thought of the application, there will be changes in specific embodiments and applications, in conclusion this
Description should not be construed as the limitation to the application.
Claims (13)
1. a kind of communication method between cores, which is characterized in that apply in virtual equipment, is run in the virtual equipment
One component builds the second component in the first assembly by virtualization, the method includes：
The information of multiple virtual processors is notified first assembly by the second component；
First assembly obtains the information of the multiple virtual processor；
First assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.
2. according to the method described in claim 1, it is characterized in that, the information of virtual processor is notified in second component
Before the step of first assembly, the method further includes：
Whether the second component queries first assembly supports half virtualization intercore communication；
Second component notifies that the second component is supported described in first assembly when knowing that first assembly supports half virtualization intercore communication
Half virtualization intercore communication.
3. method according to claim 1 or 2, which is characterized in that second component is by the letter of multiple virtual processors
The step of breath notice first assembly, includes：
Second component generation simulation register；
The multiple virtual processors of second component generate the first notification message, and first notification message includes multiple virtual processing
The information of device；
The simulation register is written in first notification message by the second component, to notify first assembly.
4. method according to claim 1 or 2, which is characterized in that second component is by the letter of multiple virtual processors
The step of breath notice first assembly, includes：
Second component application shared drive, and notify first assembly；
The shared drive is written in the information of multiple virtual processors by the second component；Second component generation second notification message is simultaneously
Notify first assembly.
5. according to the method described in claim 3, it is characterized in that, the first assembly obtains the multiple virtual processor
The step of information, includes：
First assembly recognizes the first flag of half virtualization intercore communication from first notification message；
First assembly reads the information of the multiple virtual processor according to the first flag from first notification message.
6. according to the method described in claim 4, it is characterized in that, the first assembly obtains the multiple virtual processor
The step of information, includes：
First assembly recognizes the second identifier of half virtualization intercore communication from the second notification message；
First assembly reads the information of the multiple virtual processor according to the second identifier from the shared drive.
7. a kind of intercore communication device, which is characterized in that apply in virtual equipment, is run in the virtual equipment
One component builds the second component in the first assembly by virtualization, wherein,
Second component includes：
Information notification module, for the information of multiple virtual processors to be notified host；
The first assembly includes：
Data obtaining module, for obtaining the information of the multiple virtual processor；
Internuclear interruption sending module, for sending internuclear interrupt signal to the multiple virtual processor according to described information.
8. device according to claim 7, which is characterized in that second component further includes：
Characteristic supports inquiry module, for inquiring whether first assembly supports half virtualization intercore communication；
Characteristic supports notification module, for when knowing that first assembly supports half virtualization intercore communication, notifying first assembly, institute
It states the second component and supports half virtualization intercore communication.
9. device according to claim 7 or 8, which is characterized in that described information notification module includes：
Register analog submodule simulates register for generating；
Notification message generates submodule, the first notification message is generated for multiple virtual processors, in first notification message
Include the information of multiple virtual processors；
Simulation register submodule is write, for first notification message to be written the simulation register, to notify first group
Part.
10. device according to claim 7 or 8, which is characterized in that described information notification module includes：
Shared drive application submodule for applying for shared drive, and notifies first assembly；
Shared drive submodule is write, for the information of multiple virtual processors to be written the shared drive；
Notification message notifies submodule, for generating second notification message and notifying first assembly.
11. device according to claim 9, which is characterized in that described information acquisition module includes：
First flag identifies submodule, for recognizing the first of half virtualization intercore communication the mark from first notification message
Know；
First information reading submodule, it is the multiple virtual for being read according to the first flag from first notification message
The information of processor.
12. device according to claim 9, which is characterized in that described information acquisition module includes：
Second identifier identifies submodule, for recognizing the second of half virtualization intercore communication the mark from the second notification message
Know；
Second information reading submodule, for read from the shared drive according to the second identifier it is the multiple it is virtual from
Manage the information of device.
13. a kind of virtual equipment, which is characterized in that including：
Multiple processors；
Memory；With
One or more modules, one or more of modules be stored in the memory and be configured to by one or
Multiple processors perform, wherein, first assembly is run in the virtual equipment, passes through virtualization in the first assembly
The second component is built, the multiple processor is configured as：
The information of multiple virtual processors is notified first assembly by the second component；
First assembly obtains the information of the multiple virtual processor；
First assembly sends internuclear interrupt signal according to described information to the multiple virtual processor.
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