CN108196358A - FPGA board and telescope digital operation plate - Google Patents
FPGA board and telescope digital operation plate Download PDFInfo
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- CN108196358A CN108196358A CN201711437922.9A CN201711437922A CN108196358A CN 108196358 A CN108196358 A CN 108196358A CN 201711437922 A CN201711437922 A CN 201711437922A CN 108196358 A CN108196358 A CN 108196358A
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B23/00—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices
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Abstract
The present invention provides a kind of FPGA board and telescope digital operation plate, FPGA board include：The FPGA board includes multiphase filtering module, Fourier transform module, power detection module and cache module；The multiphase filtering module is used to carry out the signal from analog-to-digital conversion circuit system the parallel filtering of multi channel signals；The Fourier transform module is used to carry out fast Fourier transform to the signal after parallel filtering；The power detection module is used to carry out signal power detection to the signal after fast Fourier transform；The cache module is used to cache the signal after signal power detection.A kind of FPGA board and telescope digital operation plate provided by the invention, by setting Fourier transform module and multiphase filtering module, is combined using multistage DDC, PFB, FFT and FIR, realizes frequency resolution best on same level FPGA.With higher bandwidth.
Description
Technical field
The present invention relates to astronomy field, more particularly, to a kind of FPGA board and telescope digital operation plate.
Background technology
Astronomical telescope (Astronomical Telescope) is the important tool for observing celestial body, can not turgidly
Say, without the birth and development of telescope, just there is no modern astronomy.As telescope the improvement of performance and carries in all respects
Height, astronomy are also just experiencing huge leap, promote understanding of the mankind to universe rapidly.
Generally there are two lens barrels on astronomical telescope, big is primary mirror, is used in observed object；Small is finder,
It is to find used in target, is also gun sight.Eyepiece is individual individual, is the article for determining enlargement ratio, all can on eyepiece
There are F values, this is the focal length of eyepiece, with the F values of primary mirror divided by the F values of currently used eyepiece, is exactly current enlargement ratio, puts
Big multiplying power is standard, and the limit enlargement ratio of the telescope of 6 centimetres of bores is 120 times or so, and 8 centimetres of multiplying power is 160 times maximum
Left and right.
In existing major astronomical telescope, all using ROACH2 as rear end frequency spectrograph, the technology of operation platform should
With highly developed.Reach 3Gsps-8bit, 550Msps-12bit with its matched ADC performance.
But the external transmission bandwidths of ROACH2 compare relatively low, real-time Transmission is still difficult to realize.
Invention content
The present invention provides a kind of a kind of FPGA board for overcoming the above problem and telescope digital operation plate.
According to an aspect of the present invention, a kind of FPGA board is provided, including：The FPGA board is filtered including multiphase
Wave module, Fourier transform module, power detection module and cache module；The multiphase filtering module is used to turn to coming from modulus
The signal for changing circuit system carries out the parallel filtering of multi channel signals；After the Fourier transform module is used for parallel filtering
Signal carries out fast Fourier transform；The power detection module is used to carry out signal work(to the signal after fast Fourier transform
Rate detection；The cache module is used to cache the signal after signal power detection.
Preferably, the FPGA board further includes packing delivery module, after the packing delivery module is used for caching
Signal carry out the packing and transmission of UDP and TCP data form.
Preferably, the multiphase filtering module is identical with the port number of the Fourier transform module.
Preferably, the FPGA board is used to carry out multistage DDC, PFB, FFT and FIR of multi channel signals simultaneously to signal
Row filtering.
According to another aspect of the present invention, a kind of telescope digital operation plate is provided, including two FPGA motherboards, AD
Plate and tailgate；One FPGA motherboard is a FPGA board.
Preferably, the FPGA motherboards are 6U standard sizes.
Preferably, the AD daughter boards are 57.1 standard AD daughter boards of FMC VITA.
Preferably, the tailgate includes at least 12 ten thousand mbit ethernet mouths.
A kind of FPGA board and telescope digital operation plate provided by the invention, by set Fourier transform module and
Multiphase filtering module is combined using multistage DDC, PFB, FFT and FIR, realizes frequency resolution best on same level FPGA.
With higher bandwidth.
Description of the drawings
Fig. 1 is a kind of structure diagram of FPGA board in the embodiment of the present invention；
Fig. 2 is a kind of firmware parallel computation schematic diagram in the embodiment of the present invention；
Fig. 3 is a kind of structure diagram of telescope digital operation plate in the embodiment of the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, the specific embodiment of the present invention is described in further detail.Implement below
Example is used to illustrate the present invention, but be not limited to the scope of the present invention.
Fig. 1 is a kind of structure diagram of FPGA board in the embodiment of the present invention, as shown in Figure 1, including：It is described
FPGA board includes multiphase filtering module, Fourier transform module, power detection module and cache module；The multiphase filtering
Module is used to carry out the signal from analog-to-digital conversion circuit system the parallel filtering of multi channel signals；The Fourier transform mould
Block is used to carry out fast Fourier transform to the signal after parallel filtering；The power detection module is used to turn fast Fourier
Signal after changing carries out signal power detection；The cache module is used to cache the signal after signal power detection.
It should be noted that the FPGA board is located in telescope digital operation plate FDB.
In the present embodiment, there are two FMC interfaces for FPGA board, can be with external two pieces of analog-digital converters, and integrate two panels
High-performance Virtex6FPGA processing chips and a piece of Virtex5FPGA control chips, 12 10G/s Ethernet output interfaces,
DDR3 (Double Data Rate) memory space of QDR (Quad Data Rate) memory spaces and 16GB on the plate of 288MB,
It can extend as needed.
When FPGA board is handled on line：19 wave beams, dual polarized signals, signal only need spectral power.During variable integration
Between, 300MHz bandwidth, 1k channels, 4-bit data flows, streaming rate during disk：100Mbytes/sec(0.36TByte/
hour)；The spectral line data obtained by FPGA is accessed, is transferred in GPU cluster and analyzes：300MHz bandwidth.
Fig. 2 is a kind of firmware parallel computation schematic diagram in the embodiment of the present invention, and the present embodiment also please refers to Fig.2.
Realize that the processing to signal optimizes on FPGA, so as to which the information of needs is extracted.The programming of this part will pass through
Xilinx EDK, Matlab Simulink, Verilog, VHDL, CASPER software library and the software library of the right independent development of section
It realizes.In brief, this includes the FPGA accesses of digital-to-analog circuit, Fast Fourier Transform, correlator (correlator), FIR
Filtering, sampling (Decimation) and optimization, the detection of echo signal (such as pulse signal) and sample take, add time tag sum number
According to the packing and transmission of head, UDP or TCP data.Design is respectively used to the FPGA operations of observation continuous spectrum, spectral line and pulsar
Pattern.In specific subchannel method, multistage more passband technologies will be used, realize the index and advance of optimization.
A kind of FPGA board provided by the invention by setting Fourier transform module and multiphase filtering module, uses
Multistage DDC, PFB, FFT and FIR are combined, and realize frequency resolution best on same level FPGA.With higher bandwidth.
Based on above-described embodiment, the FPGA board further includes packing delivery module, and the packing delivery module is used for
The packing and transmission of UDP and TCP data form are carried out to the signal after caching.
Specifically, UDP is the abbreviation of User Datagram Protocol, and Chinese name is User Datagram Protocol, is OSI
A kind of connectionless transport layer protocol in (Open System Interconnection, open system interconnection) reference model,
The simple unreliable information transmission service towards affairs is provided, IETF RFC 768 are the formal specifications of UDP.UDP is in IP packet
Protocol number be 17.Udp protocol full name is User Datagram Protocol, it is used to handle data as Transmission Control Protocol in a network
Packet, is a kind of connectionless agreement.In osi model, at the 4th layer --- transport layer, the last layer in IP agreement.UDP has
Not the shortcomings that data packet grouping, assembling are not provided and data packet cannot be ranked up, that is to say, that after message is sent, be
It can not learn its whether safe and complete arrival.UDP is used for that those is supported to need the network for transmitting data between the computers should
With.The network application of numerous Client/Servers including Video Conference System is required for assisting using UDP
View.Udp protocol has been used many years so far from coming out, although its initial brilliance is covered by some similar agreements
Lid, even but today UDP still can yet be regarded as a very useful and feasible network transmission layer protocol.
Further, TCP (Transmission Control Protocol transmission control protocols) is a kind of towards connection
, reliable, the transport layer communication protocol based on byte stream, defined by the RFC793 of IETF.In simplified computer network OSI
In model, it completes the function specified by the 4th layer of transport layer, and User Datagram Protocol (UDP) is that another is important in same layer
Transport protocol.In internet protocol suite (Internet protocol suite), TCP layer is located on IP layers, application
Middle layer under layer.Be frequently necessary to the reliable, connection as pipeline between the application layer of different hosts, but IP layers not
Stream mechanism as offer, and it is to provide insecure packet switch.
A kind of FPGA board provided by the invention is packaged delivery module by setting, data can be beaten in real time
Packet transmission.
Based on above-described embodiment, the multiphase filtering module is identical with the port number of the Fourier transform module.
Based on above-described embodiment, the FPGA board be used for signal carry out multi channel signals multistage DDC, PFB,
FFT and FIR parallel filterings.
FFT uses real discrete Fourier transformation module, and output data only chooses real part, and data volume reduces half.Data
After FFT module output, digital power detection is needed, i.e., is believed the power for obtaining signal after digital signal square by integration
Breath, is mainly made of squaring module and accumulator module, and accumulative frequency is that host computer is controllable, value 10000 times, and the time of integration is
12.8ms.The realization of FPGA control process units reuses ISE using the emulation of SIMULINK tools and realization of MATLAB softwares
The System Generator tools generation black box subfile of software, runs in ISE softwares.
Firmware and algorithm running on the FPGA, the method that will be combined using multistage DDC, PFB, FFT and FIR are realized
In the case of 3GHz bandwidth and 12bit ADC precision, longest Fourier transform port number, so as to fulfill on same level FPGA
Best frequency resolution.This equally has important science and more practical value and wide influence power.
The present embodiment describes the realization of million channel FFT below：
FPGA operation boards realize frequency spectrograph function in terms of astronomical signal processing module, and key job is exactly base
Digital signal is converted in Discrete Fourier Transform, frequency domain is become from the time domain of script.
When being realized on FPGA operation boards, module packaged Xilinx such as FFT, multiphase filter group PFB are used
Deng the foundation for carrying out algorithm, signal generator can generate signal, then be received by ADC, convert analog signal, can thus obtain
Digital signal is obtained, fully optimizes sampled digital signal sample sequence using multiphase filter group.
Implement cascade FFT operations：One-dimensional signal sequence is transmitted, realization is transferred into module Transpose, after the completion,
To the sequence of data expansion again, level-one FFT calculation process data by result and rotation fac-tor, are transferred into
In Transpose module transposition, hereafter two level FFT handles it, and power P ower modules handle spectrum information,
It is obtained with spectrum power in this way.To ensure that signal-to-noise ratio is sufficiently strong, module Vacc realizes effectively cumulative spectrum information, it is this just
Signal accumulation information can be obtained.
For N point sequence x (n), wherein DFT just needs to use at this time N^2 times again during transformation X (k) is carried out
Number multiplication, while also need to use N (N-1) secondary complex addition.If N is very big, in this case, it will have great meter
Calculation amount.The FFT port numbers reached in FPGA simultaneously all less, can generally be realized based on disposable FFT.It looks in the distance from radio
The angle of image frequency spectrometer is analyzed, if thinking, spectral resolution is higher, FFT port numbers are preferably more at this time.And U.S. CASPER
In terms of group FFT port numbers, quantity is simultaneously few, some influences is caused on processing speed, it is necessary to optimize FFT.The existing super large of analysis
If the FFT of points needs to ensure larger operation platform internal memory in this way, in order to solve this it can be appreciated that implementation FFT operations
Problem, the present embodiment considers two dimensional cascade formula FFT, during ultra long FFT is realized, is based primarily upon two small points of cascade
FFT reach.During preparing to realize million channels (2^22) FFT, Cooley-Tukey algorithms, base are mainly applied
In large-scale FFT operations, two small point FFT operations are gradually realized.During Cooley-Tukey classic algorithms are realized, DFT
N number of sampled point that processing sampling is obtained, effectively splits it, in this way so as to obtain N=N1*N2, from essential level
From the point of view of be (N1, a N2) matrix, dimension DFT is converted first, in this way so as to obtain two-dimentional DFT.First small FFT is come
It says, it is identical with the direction of N2, in this way so as to implement the FFT of N1 points, the result obtained and rotation fac-tor are turned
Processing is put, is obtained with (N2, N1) in this way, after the completion, implements N2 points FFT operations.
To realize, actual signal restores original size at frequency point, needs to use Matlab programs.To two level FFT operation lists
First implementation processing, since neighbouring N1 integral multiple frequency points, determines the frequency corresponding to the 0th, 20,32 circulation area.To energy
The related frequency point of amount leakage is determined, and thus can clearly be superimposed port number；Superposition spectral line, the constant termination of frequency energy, this
Sample signal energy is restored.For theoretic, if it is specially 32 that channel, which deviates, the amplification of theoretic is 3dB, this
40 bars channel values are superimposed, such release model restores substantially.If channel deviation has been more than 32, transported with two level FFT later
It calculates unit integer frequency point relatively, symmetrical attribute is just shown in this case, to hereafter frequency point, real signal path energy
There are many amount leakage.
Based on above-described embodiment, another embodiment of the present invention discloses a kind of telescope digital operation plate.Fig. 3 is the present invention
A kind of structure diagram of telescope digital operation plate in embodiment, including multiple FPGA motherboards, AD daughter boards and tailgate；One institute
FPGA motherboards are stated as the FPGA board described in an any of the above-described embodiment.The multiple FPGA motherboards are preferably two.Institute
Tailgate is stated as high speed protocol tailgate.
Based on above-described embodiment, the FPGA motherboards are 6U standard sizes.
Based on above-described embodiment, the AD daughter boards are 57.1 standard AD daughter boards of FMC VITA.
Based on above-described embodiment, the tailgate includes at least 12 ten thousand mbit ethernet mouths.
On technical parameter.Telescope digital operation plate FDB has been designed to 2 V6FPGA compositions, brings more meters
Calculation ability, for that in the high-precision spectral line of ultra wide band, can be combined by 2 FPGA, realize the FFT of bigger points.It is more important
, FDB can be as needed, the quantity of flexible configuration QDR, DDR, 10G network interface.And cost is controllable.
The technology of the ROACH2 operation platforms of CASPER exploitations is using highly developed, so each large telescope is all selected at present
It is as rear end frequency spectrograph, with its matched ADC performance up to 3Gsps-8bit, 550Msps-12bit, and as FDB can be with
Two high-precision of configuration 3.2Gsps-12bit and 5Gsps-10bit, high bandwidth ADC are a whole set of digital back-end system to total evidence
Processing capacity lay the foundation.And the external transmission bandwidths of ROACH2 compare it is relatively low, if data used it is high-precision more than 8bit
Degree pattern, but real-time Transmission can not still be realized.FDB has three parts using general frame, and a part is 6U standard sizes
FPGA motherboards, a part of 57.1 standard AD daughter boards of FMC VITA, some is high speed protocol tailgate.Operation board is in master control
Virtex-5 cores have mainly been selected in terms of chip, quantity is 1, in terms of operation chip, needs to have selected Virtex-6 chips,
Quantity is 2, and for the port number after two panels operation chip cascade up to as many as million, good spectral resolution can be fine to spectral line
Structure is analyzed.It for Virtex-6, is connect with 2GBDDR3SDRAM memory modules, while and 9MBQDRII
SRAM memory modules connect.In terms of tailgate is transmitted, the support of minimum 12 mouthful of ten thousand mbit ethernet is realized, than the 8 of ROACH 2
A ten thousand mbit ethernets mouth higher.Its system architecture diagram is shown in Fig. 3.
Further, below to by FPGA board proposed by the present invention, analog-to-digital conversion circuit system and front-end circuit
System carries out timestamp acquisition and system synchronization is made and explanation is further explained.
Timestamp is configured to GPS receiver etc., based on GPS receiver so as to obtain 1PPS signals, the 1PPS of GPS outputs
(pulse per second (PPS)) precision is 20ns or so, is transferred to Frequency Standard instruments, pulse is adjusted, thus
Rising edge of a pulse can be obtained, the linux system in FPGA obtains accurate network time so that timestamp program in FPGA
It is formal to start.After data output, it is obtained with good timestamp in this way and is packaged.It is imitated based on the realization of Simulink softwares
Very, the Unix times are specially in the present embodiment real-time time, are obtained based on linux system with latticed form, Unix
Timestamp starts from January 1st, 1970.GPS sends out 1PPS, and such FPGA is based on network and obtains Unix Timestamp, simultaneously
Small several seconds counter is allowed formally to start.The latter calculates the FPGA time cycles, for example FPGA working frequencies are in this subject
It is specially 200MHz in research, the corresponding clock cycle is specially 5ns in this subject study, if clock cycle counter meter
Number is specially 1s, and for integer second counter, it will add 1 at this time, and reset processing is carried out to small several seconds counter.The small several seconds
Count value carries out summation process particularly as being integer second Counter Value superposition Unix Timestamp number of seconds with the integer second, so as to
Obtain nsec stamp.FPGA clocks are effectively obtained based on ADC, and such ADC can be effectively synchronous with FPGA.
In self-defined pattern, chronometer data has higher readability, and chronometer data is presented in analysis receiver processing
Go out feature, during packaged data, add timestamp and data head wherein, thus have absolute time letter
Breath.Data head embodiments in this subject study start for data packet, realize the differentiation to data packet, consist of high knowledge
Other character string.The process need to use MATALAB/Simulink softwares, select CASPER in the present embodiment in terms of database
With the product of Xilinx, simulation process, data packet bit wide sets specific as follows：Data head 16, timestamp 16, data 50
Position, a total of 82 of useful signal, a data packet length setting are total up to 256, other are entirely non-effective signal, are beaten
Packet portion is as data transmission important composition.After data processing, effectively transmitted based on 10G high speed Ethernets, udp protocol
Transmission.Entire data transmission system is emulated using MATLAB/Simulink.
A kind of FPGA board and telescope digital operation plate provided by the invention, by set Fourier transform module and
Multiphase filtering module is combined using multistage DDC, PFB, FFT and FIR, realizes frequency resolution best on same level FPGA.
With higher bandwidth.Delivery module is packaged by setting, data can be carried out to be packaged transmission in real time.
Finally, method of the invention is only preferable embodiment, is not intended to limit the scope of the present invention.It is all
Within the spirit and principles in the present invention, any modification, equivalent replacement, improvement and so on should be included in the protection of the present invention
Within the scope of.
Claims (8)
1. a kind of FPGA board, which is characterized in that including：
The FPGA board includes multiphase filtering module, Fourier transform module, power detection module and cache module；
The multiphase filtering module is used to carry out the signal from analog-to-digital conversion circuit system the parallel filtering of multi channel signals；
The Fourier transform module is used to carry out fast Fourier transform to the signal after parallel filtering；
The power detection module is used to carry out signal power detection to the signal after fast Fourier transform；
The cache module is used to cache the signal after signal power detection.
2. FPGA board according to claim 1, which is characterized in that the FPGA board further includes packing transmission mould
Block, the packing and transmission for being packaged delivery module and being used to carry out the signal after caching UDP and TCP data form.
3. FPGA board according to claim 1, which is characterized in that the multiphase filtering module turns with the Fourier
The port number for changing the mold block is identical.
4. FPGA board according to claim 1, which is characterized in that the FPGA board is used to carry out signal more
Multistage DDC, PFB, FFT and FIR parallel filtering of channel signal.
5. a kind of telescope digital operation plate, which is characterized in that including multiple FPGA motherboards, AD daughter boards and tailgate；
One FPGA motherboard is the FPGA board described in any one of claim 1 to 4.
6. telescope digital operation plate according to claim 5, which is characterized in that the FPGA motherboards are 6U gauges
It is very little.
7. telescope digital operation plate according to claim 5, which is characterized in that the AD daughter boards are FMC VITA
57.1 standard AD daughter boards.
8. telescope digital operation plate according to claim 5, which is characterized in that the tailgate includes at least 12 10,000,000,000
Ethernet interface.
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Cited By (1)
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| WO2021134938A1 (en) * | 2019-12-31 | 2021-07-08 | 国微集团(深圳)有限公司 | Simulation data processing method and system |
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