CN108182897B - Method for testing pixel driving circuit - Google Patents
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- CN108182897B CN108182897B CN201711462520.4A CN201711462520A CN108182897B CN 108182897 B CN108182897 B CN 108182897B CN 201711462520 A CN201711462520 A CN 201711462520A CN 108182897 B CN108182897 B CN 108182897B
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention provides a method for testing a pixel driving circuit, which comprises the following steps: storing a voltage for turning on the first transistor in the direct test period in the second capacitor by turning on the second transistor in the indirect test period, the second transistor and the second capacitor being normal if the direct test period is entered from the indirect test period; and turning on the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor and the seventh transistor in a direct test period after the indirect test period, detecting a current between a first terminal of the second transistor and a second terminal of the fourth transistor, and determining that the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor and the seventh transistor are normal if the detected current is within a predetermined current range. The invention can test all transistors and capacitors in the pixel driving circuit, thereby avoiding the detection leakage phenomenon.
Description
Technical Field
The invention belongs to the technical field of circuit testing, and particularly relates to a method for testing a pixel driving circuit.
Background
In recent years, Organic Light-Emitting Diode (OLED) displays have become very popular flat display devices at home and abroad because OLED displays have the characteristics of self-luminescence, wide viewing angle, short reaction time, high luminous efficiency, wide color gamut, low operating voltage, thin thickness, capability of manufacturing large-size and flexible displays, simple manufacturing process and the like, and also have the potential of low cost.
The OLED display can be classified into a passive matrix type OLED display (i.e., a PMOLED display) and an active matrix type OLED display (i.e., an AMOLED display) according to a driving manner.
The AMOLED is a current-driven device, and when a current flows through an organic light emitting diode, the organic light emitting diode emits light, and the luminance is determined by the current flowing through the organic light emitting diode itself. Most of the existing Integrated Circuits (ICs) only transmit voltage signals, so the pixel driving circuit of the AMOLED needs to complete the task of converting the voltage signals into current signals. A conventional AMOLED pixel driving circuit is generally 2T1C, i.e. a structure of two transistors plus one capacitor, converting voltage into current, but a conventional 2T1C pixel driving circuit generally has no compensation function. Therefore, it is proposed in the art to employ pixel driving circuits having a compensation function such as 7T1C, 6T1C, 6T2C, and the like.
However, in these pixel driving circuits with compensation function, when testing each transistor and each capacitor of the pixel driving circuit, some transistors and/or some capacitors cannot be tested, so that a leak detection phenomenon occurs.
Disclosure of Invention
In order to solve the problems of the prior art described above, an object of the present invention is to provide a method of testing a pixel driving circuit capable of detecting all transistors and all capacitors in the pixel driving circuit.
According to an aspect of the present invention, there is provided a method of testing a pixel driving circuit, the pixel driving circuit comprising: a first transistor whose gate electrode is connected to a first node, and whose first terminal is connected to a second node, and whose second terminal is connected to a third node; a second transistor having a gate electrode for receiving a current stage scan signal, a second terminal connected to the second node, and a first terminal for receiving a data voltage; a third transistor having a gate electrode for receiving a current stage scan signal, a second terminal connected to the third node, and a first terminal connected to the first node; a fourth transistor having a gate electrode for receiving a previous-stage scan signal, a first terminal connected to the first node, and a second terminal for receiving a second power supply voltage; a fifth transistor having a gate electrode for receiving an enable signal, a first terminal for receiving a first power supply voltage, and a second terminal connected to the second node; a sixth transistor having a gate electrode for receiving an enable signal and a first terminal connected to the third node; a seventh transistor having a gate electrode for receiving a current stage scan signal, a first terminal connected to the second terminal of the fourth transistor, and a second terminal connected to the second terminal of the sixth transistor; a capacitor having a first terminal connected to the first terminal of the fifth transistor and a second terminal connected to the first node; the method for testing the pixel driving circuit comprises the following steps: storing a voltage for turning on the first transistor in the second capacitor in an indirect test period by turning on the fourth transistor, the fourth transistor and the capacitor being normal if a direct test period is entered from the indirect test period; turning on the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor in a direct test period after the indirect test period, and detecting a current between a first terminal of the second transistor and a second terminal of the fourth transistor, and if the detected current is within a predetermined current range, determining that the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are normal.
Further, each of the first to seventh transistors is a p-channel transistor.
Further, in the indirect test period, the previous-stage scan signal is at a low potential, and the current-stage scan signal and the enable signal are at a high potential.
Further, in the indirect test period, the previous stage scan signal and the enable signal are at a low potential, and the current stage scan signal is at a high potential.
Further, in the direct test period, the previous stage scan signal is at a high potential, and the current stage scan signal and the enable signal are at a low potential.
Further, in a first period before the interval test period, the previous stage scan signal, the current stage scan signal, and the enable signal are all at a high potential.
Further, in a second time period before the interval test time period, the previous-stage scan signal and the enable signal are both at a high potential, and the current-stage scan signal is at a low potential.
Further, in a first time period before the second time period, the current-stage scan signal and the enable signal are both at a high potential, and the previous-stage scan signal is at a low potential.
The invention has the beneficial effects that: the invention can complete the test of each transistor and each capacitor in the pixel driving circuit by changing the time sequence of high and low potential of each driving signal in the test period, thereby avoiding the detection omission phenomenon.
Drawings
The above and other aspects, features and advantages of embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a pixel driving circuit for an OLED display according to an embodiment of the present invention;
FIG. 2 is a timing diagram of signals during normal operation of a pixel driving circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of signals when testing a pixel driving circuit according to an embodiment of the invention;
FIG. 4 is a timing diagram of signals when testing a pixel driving circuit according to another embodiment of the present invention;
FIG. 5 is a timing diagram of signals when testing a pixel driving circuit according to yet another embodiment of the present invention;
fig. 6 is a schematic diagram illustrating the flowing direction of current when testing a pixel driving circuit according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification and drawings.
Fig. 1 is a circuit diagram of a pixel driving circuit for an OLED display according to an embodiment of the present invention.
Referring to fig. 1, a pixel driving circuit for an OLED display according to an embodiment of the present invention has a 7T1C pixel structure. Specifically, the 7T1C pixel structure includes an organic light emitting diode OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
The gate electrode of the first transistor T1 is electrically connected to the first node g, and has a first terminal electrically connected to the second node s and a second terminal connected to the third node d.
The gate electrode of the second transistor T2 is for receiving the Scan signal Scan [ n ] of the current stage, and has a first terminal for receiving the data voltage Vdata and a second terminal connected to the second node s. In the present embodiment, the data voltage Vdata is a high potential (or referred to as a high level).
The gate electrode of the third transistor T3 is for receiving the current-stage Scan signal Scan [ n ], and has a first terminal electrically connected to the first node g and a second terminal electrically connected to the third node d.
The fourth transistor T4 has a gate electrode for receiving the Scan signal Scan [ n-1] of the previous stage, and a first terminal connected to the first node g and a second terminal for receiving the second power supply voltage Vi. In this embodiment, the second power voltage Vi is low.
The fifth transistor T5 has a gate electrode for receiving the enable signal Em, a first terminal for receiving the first power supply voltage Vdd, and a second terminal connected to the second node s. In the present embodiment, the first power supply voltage Vdd is high.
The sixth transistor T6 has a gate electrode for receiving the enable signal Em, and a first terminal connected to the third node d and a second terminal connected to the anode electrode of the organic light emitting diode OLED.
The seventh transistor T7 has a gate electrode for receiving the current-stage Scan signal Scan [ n ], and a first terminal connected to the second terminal of the fourth transistor T4 and a second terminal connected to the second terminal of the sixth transistor T6.
The first terminal of the capacitor C is connected to the first terminal of the fifth transistor T5, and the second terminal thereof is electrically connected to the first node g.
The cathode of the organic light emitting diode OLED is electrically grounded.
In the present embodiment, the first transistor T1 functions as a driving transistor.
Here, the first terminal of each of the first to seventh transistors T1 to T7 may be a source electrode or a drain electrode, and the second terminal of each of the first to seventh transistors T1 to T7 may be an electrode different from the first terminal.
For example, when the first terminal is a drain electrode, the second terminal is a source electrode; and when the first terminal is a source electrode, the second terminal is a drain electrode.
Each of the first to seventh transistors T1 to T7 may have the same channel shape.
For example, each of the first to seventh transistors T1 to T7 may have a p-channel shape.
Accordingly, each of the first to seventh transistors T1 to T7 may be implemented using a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or an oxide thin film transistor.
In addition, the previous stage Scan signal Scan [ n-1] and the current stage Scan signal Scan [ n ] are typically stage transfer Scan signals generated by a GOA driving circuit (not shown) in the OLED display, which are transferred one stage at a time along the Scan lines.
The operating principle of the pixel driving circuit according to an embodiment of the present invention will be described in detail below. Fig. 2 is a timing chart of signals when the pixel driving circuit according to the embodiment of the present invention performs a normal operation (i.e., drives the OLED to emit light for normal display).
Referring to fig. 1 and 2, in the first period T1, the previous stage Scan signal Scan [ n-1] is maintained at a low potential, and the current stage Scan signal Scan [ n ] and the enable signal EM are both at a high potential.
At this time, the fourth transistor T4 is turned on, so that the second power supply voltage Vi pulls down the potential of the first node g (i.e., the second terminal of the capacitor C), and the first power supply voltage Vdd charges the capacitor C.
In the second period T2, the previous stage Scan signal Scan [ n-1] and the enable signal EM are both high, and the current stage Scan signal Scan [ n ] is low.
At this time, the second transistor T2 is turned on to supply the data voltage Vdata to the second node s (i.e., the first terminal of the first transistor T1), the third transistor T3 is turned on, the first terminal and the second terminal of the first transistor T1 are shorted, and the voltage | Vg | > | Vth | of the first node g, the first transistor T1 becomes a diode, the first transistor T1 is turned on, until the first transistor T1 is turned off when the voltage Vg of the first node g is Vdata- | Vth |, and the seventh transistor T7 is turned on, thereby resetting the organic light emitting diode OLED. Here, Vth is a threshold voltage of the first transistor T1.
In the third period T3, the enable signal Em maintains a low potential, while the previous stage Scan signal Scan [ n-1] and the current stage Scan signal Scan [ n ] maintain a high potential, the fifth transistor T5 is turned on to supply the first power voltage Vdd to the second node s (i.e., the first terminal of the first transistor T1) whose voltage Vs is Vdd; at this time, the voltage Vg of the first node g is Vdata- | Vth |, and the voltage difference Vsg between the first node g and the second node s of the first transistor T1 is Vdd-Vdata + | Vth |.
The current I through the first transistor T1 is represented as:
I＝(1/2)k(Vsg-|Vth|)2＝(1/2)k(Vdd-Vdata+|Vth|-|Vth|)2＝(1/2)k(Vdd-Vdata)2
where k denotes an intrinsic conductivity factor of the first transistor T1, which is determined by the characteristics of the first transistor T1 itself.
The sixth transistor T6 is turned on to allow the current I to flow to the organic light emitting diode OLED so that the organic light emitting diode OLED emits light normally.
Therefore, in the expression of the current I flowing through the organic light emitting diode OLED, the current I is independent of the threshold voltage Vth of the first transistor T1, so that a picture display failure phenomenon caused by the shift of the threshold voltage Vth of the first transistor T1 can be eliminated.
In the conventional method for testing the pixel driving circuit, in the third stage T3, the state of current is usually tested between the first terminal of the second transistor T2 and the first terminal of the fifth transistor T5 to determine whether the transistors are normal or not, and in the third stage T3, the current I flows in the direction of the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the organic light emitting diode OLED, so that the current I is not detected when being tested in the conventional testing method, which may result in the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 being missed. In order to solve this problem, the present invention proposes a test method to enable full detection of the first to seventh transistors T1 to T7 and the capacitor C, avoiding missed detection.
Fig. 3 is a timing diagram of signals when testing a pixel driving circuit according to an embodiment of the present invention. In testing the pixel driving circuit, each signal is supplied from a tester.
Referring to fig. 3, in the first period T1, the previous stage Scan signal Scan [ n-1], the current stage Scan signal Scan [ n ], and the enable signal Em are all high, and the first to seventh transistors T1 to T7 are all turned off.
In a second period T2, that is, an indirect test period, the previous stage Scan signal Scan [ n-1] is at a low potential, and the current stage Scan signal Scan [ n ] and the enable signal Em are at a high potential; at this time, the fourth transistor T4 is turned on, changing the potential of the first node g to a low potential while storing the low potential in the capacitor C to turn on the voltage of the first transistor T1 as the third period T3, so that it is possible to indirectly detect whether the fourth transistor T4 and the capacitor C are functioning normally or not. Here, the indirect detection means: if abnormality occurs in the fourth transistor T4 and/or the capacitor C in the second period T2, the following third period T3 cannot be entered. Therefore, if the third period T3 is normally entered, it indicates that the fourth transistor T4 and the capacitor C are normally functioning.
In the third period T3, i.e., the direct test period, the previous stage Scan signal Scan [ n-1] is at a high potential, and the current stage Scan signal Scan [ n ] and the enable signal Em are at a low potential. At this time, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned on, and the first transistor T1 is also turned on according to the voltage stored by the capacitor C during the second period T2, and whether the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are normal is determined by detecting a current between the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4. If it is detected that the current between the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4 is within a predetermined current range, it indicates that the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are normal. Here, the dotted arrow in the pixel driving circuit shown in fig. 6 indicates the flowing direction of the current in the third period T3 when the pixel driving circuit is tested. It should be noted that the predetermined current range refers to a reasonable current range determined during long-term detection and suitable for detecting the pixel driving circuit.
Fig. 4 is a timing diagram of signals when testing a pixel driving circuit according to another embodiment of the present invention. In testing the pixel driving circuit, each signal is supplied from a tester.
In the first period T1, the previous Scan signal Scan [ n-1] is at a low potential, and the current Scan signal Scan [ n ] and the enable signal Em are both at a high potential. The pixel driving circuit is not substantially tested in the first period T1, and the high or low potential of each signal in the first period T1 is only the buffer band when the tester supplies it.
In the second period T2, the previous stage Scan signal Scan [ n-1] and the enable signal Em are at a high potential, and the current stage Scan signal Scan [ n ] is at a low potential. The pixel driving circuit is not substantially tested in the second period T2, and the high potential or the low potential of each signal in the second period T2 is only a buffer band when the tester supplies.
In a third period T3, that is, an indirect test period, the previous stage Scan signal Scan [ n-1] and the enable signal Em are at a low potential, and the current stage Scan signal Scan [ n ] is at a high potential; at this time, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on, and the potential of the first node g becomes a low potential, and the low potential is stored in the capacitor C as a voltage of the fourth period T4 to turn on the first transistor T1, so that it is possible to indirectly detect whether the fourth transistor T4 and the capacitor C function normally or not. Here, the indirect detection means: if abnormality occurs in the fourth transistor T4 and/or the capacitor C in the third period T3, the following fourth period T4 cannot be entered. Therefore, if the fourth period T4 is normally entered, it indicates that the fourth transistor T4 and the capacitor C are normally functioning.
In a fourth period T4, i.e., the direct test period, the previous stage Scan signal Scan [ n-1] is at a high potential, and both the current stage Scan signal Scan [ n ] and the enable signal Em are at a low potential. At this time, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned on, and the first transistor T1 is also turned on according to the voltage stored by the capacitor C during the third period T3, and whether the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are normal is determined by detecting a current between the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4. If it is detected that the current between the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4 is within a predetermined current range, it indicates that the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are normal. Here, the dotted arrow in the pixel driving circuit shown in fig. 6 indicates the flowing direction of the current in the fourth period T4 when the pixel driving circuit is tested. It should be noted that the predetermined current range refers to a reasonable current range determined during long-term detection and suitable for detecting the pixel driving circuit.
Fig. 5 is a timing diagram of signals when testing a pixel driving circuit according to still another embodiment of the present invention. In testing the pixel driving circuit, each signal is supplied from a tester.
In the first period T1, the previous Scan signal Scan [ n-1] is at a low potential, and the current Scan signal Scan [ n ] and the enable signal Em are both at a high potential. The pixel driving circuit is not substantially tested in the first period T1, and the high or low potential of each signal in the first period T1 is only the buffer band when the tester supplies it.
In the second period T2, the previous stage Scan signal Scan [ n-1] and the enable signal Em are at a high potential, and the current stage Scan signal Scan [ n ] is at a low potential. The pixel driving circuit is not substantially tested in the second period T2, and the high potential or the low potential of each signal in the second period T2 is only a buffer band when the tester supplies.
In a third period T3, that is, an indirect test period, the previous stage Scan signal Scan [ n-1] is at a low potential, and the current stage Scan signal Scan [ n ] and the enable signal Em are at a high potential; at this time, the fourth transistor T4 is turned on, the potential of the first node g becomes a low potential, and the low potential is stored in the capacitor C as the voltage of the fourth period T4 to turn on the first transistor T1, so that it is possible to indirectly detect whether the fourth transistor T4 and the capacitor C function normally or not. Here, the indirect detection means: if abnormality occurs in the fourth transistor T4 and/or the capacitor C in the third period T3, the following fourth period T4 cannot be entered. Therefore, if the fourth period T4 is normally entered, it indicates that the fourth transistor T4 and the capacitor C are normally functioning.
In a fourth period T4, i.e., the direct test period, the previous stage Scan signal Scan [ n-1] is at a high potential, and both the current stage Scan signal Scan [ n ] and the enable signal Em are at a low potential. At this time, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned on, and the first transistor T1 is also turned on according to the voltage stored by the capacitor C during the third period T3, and whether the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are normal is determined by detecting a current between the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4. If it is detected that the current between the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4 is within a predetermined current range, it indicates that the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are normal. Here, the dotted arrow in the pixel driving circuit shown in fig. 6 indicates the flowing direction of the current in the fourth period T4 when the pixel driving circuit is tested. It should be noted that the predetermined current range refers to a reasonable current range determined during long-term detection and suitable for detecting the pixel driving circuit.
In addition, it should be noted that, when the pixel driving circuit is tested, the organic light emitting diode OLED may not be needed, but the present invention is not limited thereto.
In summary, according to the embodiments of the invention, the timing of the high and low voltages of each driving signal is changed during the testing period, so as to complete the testing of each transistor and each capacitor in the pixel driving circuit, and further, the missing detection phenomenon is not occurred.
While the invention has been shown and described with reference to certain embodiments, those skilled in the art will understand that: various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (8)
1. A method of testing a pixel driving circuit, the pixel driving circuit comprising:
a first transistor whose gate electrode is connected to a first node, and whose first terminal is connected to a second node, and whose second terminal is connected to a third node;
a second transistor having a gate electrode for receiving a current stage scan signal, a second terminal connected to the second node, and a first terminal for receiving a data voltage;
a third transistor having a gate electrode for receiving a current stage scan signal, a second terminal connected to the third node, and a first terminal connected to the first node;
a fourth transistor having a gate electrode for receiving a previous-stage scan signal, a first terminal connected to the first node, and a second terminal for receiving a second power supply voltage;
a fifth transistor having a gate electrode for receiving an enable signal, a first terminal for receiving a first power supply voltage, and a second terminal connected to the second node;
a sixth transistor having a gate electrode for receiving an enable signal and a first terminal connected to the third node;
a seventh transistor having a gate electrode for receiving a current stage scan signal, a first terminal connected to the second terminal of the fourth transistor, and a second terminal connected to the second terminal of the sixth transistor;
a capacitor having a first terminal connected to the first terminal of the fifth transistor and a second terminal connected to the first node;
the method for testing the pixel driving circuit comprises the following steps:
storing a voltage for turning on the first transistor in the capacitor in a direct test period by turning on the fourth transistor in an indirect test period, the fourth transistor and the capacitor being normal if a direct test period is entered from the indirect test period;
turning on the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor in a direct test period after the indirect test period, and detecting a current between a first terminal of the second transistor and a second terminal of the fourth transistor, and if the detected current is within a predetermined current range, determining that the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are normal.
2. The method according to claim 1, wherein each of the first to seventh transistors is a p-channel transistor.
3. The method according to claim 2, wherein in the indirect test period, the previous stage scan signal is at a low potential, and the current stage scan signal and the enable signal are at a high potential.
4. The method according to claim 2, wherein in the indirect test period, the previous stage scan signal and the enable signal are at a low potential, and the current stage scan signal is at a high potential.
5. The method according to claim 3 or 4, wherein in the direct test period, the previous stage scan signal is at a high level, and the current stage scan signal and the enable signal are at a low level.
6. The method according to claim 3, wherein in a first period before the interval test period, the previous stage scan signal, the current stage scan signal, and the enable signal are all high.
7. The method according to claim 3 or 4, wherein in a second period before the interval test period, the previous stage scan signal and the enable signal are both high, and the current stage scan signal is low.
8. The method according to claim 7, wherein in a first period before the second period, the current stage scan signal and the enable signal are both high, and the previous stage scan signal is low.
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| PCT/CN2018/074033 WO2019127791A1 (en) | 2017-12-28 | 2018-01-24 | Method for testing pixel driving circuit |
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| CN109410836A (en) * | 2018-12-05 | 2019-03-01 | 武汉华星光电半导体显示技术有限公司 | OLED pixel driving circuit and display panel |
| CN110827730B (en) * | 2019-11-28 | 2022-12-13 | 京东方科技集团股份有限公司 | Circuit and method for detecting characteristics of transistors in pixel region of LTPSAMOLED display substrate |
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| CN101206318B (en) * | 2006-12-22 | 2010-05-19 | 群康科技(深圳)有限公司 | Shifting register and LCD device |
| KR100873076B1 (en) * | 2007-03-14 | 2008-12-09 | 삼성모바일디스플레이주식회사 | Pixel, Organic Light Emitting Display Device and Driving Method Thereof |
| KR100873078B1 (en) * | 2007-04-10 | 2008-12-09 | 삼성모바일디스플레이주식회사 | Pixel, Organic Light Emitting Display Device and Driving Method Thereof |
| CN100592425C (en) * | 2007-04-27 | 2010-02-24 | 群康科技(深圳)有限公司 | Shifting register and LCD |
| KR101199106B1 (en) * | 2010-03-17 | 2012-11-09 | 삼성디스플레이 주식회사 | Organic Light Emitting Display Device |
| KR20140079685A (en) * | 2012-12-19 | 2014-06-27 | 엘지디스플레이 주식회사 | Organic light emitting diode display device and method for driving the same |
| KR101987434B1 (en) * | 2013-01-15 | 2019-10-01 | 삼성디스플레이 주식회사 | Organic light emitting diode display device and test method thereof |
| KR102141238B1 (en) * | 2013-05-22 | 2020-08-06 | 삼성디스플레이 주식회사 | Pixel and Organic Light Emitting Display Device |
| CN103996379B (en) * | 2014-06-16 | 2016-05-04 | 深圳市华星光电技术有限公司 | The pixel-driving circuit of Organic Light Emitting Diode and image element driving method |
| CN105719595B (en) * | 2014-12-05 | 2018-08-24 | 昆山工研院新型平板显示技术中心有限公司 | Pixel-driving circuit, organic light emitting display and its driving method |
| CN104464587B (en) * | 2014-12-31 | 2017-04-19 | 深圳市华星光电技术有限公司 | Array substrate and detection circuit thereof |
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2017
- 2017-12-28 CN CN201711462520.4A patent/CN108182897B/en active Active
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2018
- 2018-01-24 WO PCT/CN2018/074033 patent/WO2019127791A1/en active Application Filing
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| Publication number | Publication date |
|---|---|
| CN108182897A (en) | 2018-06-19 |
| WO2019127791A1 (en) | 2019-07-04 |
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