CN108182153A - A kind of pseudo- least recently used data replacement method of improved cache - Google Patents
A kind of pseudo- least recently used data replacement method of improved cache Download PDFInfo
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- CN108182153A CN108182153A CN201711210107.9A CN201711210107A CN108182153A CN 108182153 A CN108182153 A CN 108182153A CN 201711210107 A CN201711210107 A CN 201711210107A CN 108182153 A CN108182153 A CN 108182153A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
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Abstract
Be connected the improvement of the least recently used replacement method of puppet of cache memory architectures the present invention relates to multichannel group.Improve the least recently used replacement method of puppet of cache using the register number and mark bits number of additional negligible amounts, be allowed to the least recently used replacement method of more approaching to reality.With the increase of way, for the node of the least recently used control tree of puppet close to root node, it can suitably loosen and assist it requirement of shift register record value to carry out conjecture selection when selecting replacement data.
Description
Technical field
Replacement method when component and miss is replaced the present invention relates to processor cache.And particularly N
Road group be connected (N >=4) framework and using pseudo- least recently used (LRU) replacement policy cached data replace component and
Replacement method.
Background technology
Usually using cache (cache) as the backup of internal storage data, processor carries out modern processor architectures
During digital independent, usually first it is read out in the faster cache of reading speed, to shorten the period of data acquisition, so as to
Accelerate the processor speed of service.As the backup place of internal storage data, the mapping between cache and memory can usually divide
For full associative mapping, directly it is connected mapping and group is connected mapping.Compared to complete be connected mapping and the mapping that is directly connected, group, which is connected, reflects
Better performance can be provided in the especially multiple processor structure of most of application scenarios by penetrating, therefore be typically used for modern place
Manage the mapping mode between device cache and memory.It, can according to the difference of the quantity N of contained road (way) in a group (set)
Cache is referred to as N roads group connection mapping cache, abbreviation N-way set associative cache.Typically, N is 2 k time
Side (k >=1, and k is integer).For example, N is equal to 2,4,8,16 etc..
When processor accesses cache, in case of data miss, at this time if cache also possess not by
New data then from memory is taken out and is put into cache by the usable unit used；And at this time if in cache can
It is all occupied using unit, then it must select a data and take out it from cache, so as to discharge storage unit
Store the miss data taken out from memory.For latter situation, cache replacement component is needed according to certain way
To determine to take out any data, that is, the data replacement method of cache.
For N roads, group is connected for cache, and least recently used replacement method follows temporal locality original due to it
Preferable effect is then generated, is the most commonly used replacement method.Least recently used replacement method needs to preserve the elder generation of data
Order is accessed afterwards to be kicked out of so as to find out least recently used data.In N=2, because of only two ways in each group
According to simply most recently used road can be identified with 1 so as to fulfill least recently used replacement very.However as N ＞ 2,
The access sequencing stack of data is kept, expense just becomes especially big for digital logic hardware, i.e., to complete to operate,
Information is stored again.Common practice is, using can the puppet of approximate least recently used replacement method least recently used replace
Mode is changed to achieve the goal.It can be typically the control unit of a tree data structure.For N-way set associative at a high speed
Caching usually additionally carries out pseudo- least recently used replacement method containing N-1 control bit, that is, N-1 register and realizes.Example
Structure is managed as Fig. 1 illustrates the 4 tunnel groups tree-shaped on 4 tunnels in a group that is connected.In Fig. 1, the nonleaf node of tree is to control
Position processed, one shares 3 control bits." X " represents the value of each control bit, can be 0 or 1, it is impossible to be other values.One
As for, it is the register of 1 bit.A to c is the alias of each control bit, as a represents the root section of this tree
Point, b represent the left child node of a, and so on.4 leaf nodes represent the 1st to the 4th tunnel in the group respectively, in figure respectively
For way1 to way4.
A certain certain 4 tunnel group of moment (" X " of each node can't impact analysis in this moment tree)
Tree a certain group connected is as shown in Figure 1.If subsequent time needs to access way3 (the 3rd tunnel), analyzed from root node, by
In way3 in " X " set 1 of the right subtree, then a of root node, analysis node goes to its right child node c from root node, and due to
Way3 is in " X " set 0 of the left subtree, then node where c of c.The update of other nodes is also the same, if in analysis node
Left subtree, then by the value set " 0 " of analysis node, if on the right side of analysis node, by the value set of analysis node
“1”.After all storing data on a certain group of all roads, when the road replaced is found in the arrival of new data, need according to accessing phase
Anti- sequence carries out.After way3 has been accessed, if to select to be replaced all the way at this time, first by analysis node set root section
Point a, a are " 1 ", then the left subtree for being put into a is replaced selection, the left child node b of analysis node set a, at this time root again
It is replaced according to the value of b, if the value of b is " 1 ", replaces way1, if the value of b is 0, replace way2.
Above-mentioned is the least recently used replacement method of common puppet and its realization, according to above-mentioned node updates and replaces section
The selection method of point, at a time, accesses way3 successively, way1, way2, after way4, in tree the value of each node for a, b and
C is " 1 ".At this point, if new data arrive, need to select if certain is replaced all the way, according to original rule, it should
Way1 (value of a is 1, selects left subtree, the value of b is 1, selects left subtree, i.e. way1) is replaced, and in fact, according to LRU replacement
Method, way3 are only the object being replaced, and this introduces mistakes.
Invention content
The present invention is directed to improve the generation of this mistake under the additional hardware demand of very little, it is allowed to more replace close to LRU
Change method.Due to way N be 2 when, can with simple 1 bit come identification access order so as to complete least recently used replace
It changes, therefore the present invention only considers the improvement in the case where way N >=4 and N are the cache of 2 k power (k is integer).
At way N >=4 (and N is 2 integral number power), using root node as the 1st layer, tree-shaped control structure has M (M=
LogN, wherein logN are bottom with 2) layer.The wherein M layers generation that can't introduce mistake.But from the 1st layer to M-1 layers
All control nodes due to the influence of access order, can generate the instruction for being kicked out of data place road of mistake.Introduce (N/2-
1) group shift register is total to ((N*logN)/2-1) a register to carry out auxiliary record (logN is with 2 bottoms), while introduce (2*
N-4) a flag bit is marked.There are one each control node (the 1st to M-1 layer of all nodes) of introducing mistake contains
Shift register.With the help of these auxiliary shift registers and flag bit, pseudo- least recently used replacement method can be made
More close to least recently used replacement method, so as to improve processor performance.
Cache replacement component no longer only completes to be replaced the selection of data with tree, but according to tree-shaped section
The selection recorded to complete to be replaced data of the record and auxiliary shift register of point.And shift register is assisted to provide
Instruction priority be higher than instruction given by tree-shaped nodes records.If some mistake introduces node, its auxiliary shifts
Register record value contains only 10 or contains only 11, then no matter value of the node in tree is how many,
When being replaced data selection, root node is as next analysis node where all selecting its left subtree and right subtree respectively.
When degree of association is higher, positioned at upper strata (closer to root node) mistake introduce node it auxiliary shift register in value by
In the irregularities of access, it is extremely difficult to the situation of only 10 or only 11.In such a case, it is possible to loosen this
Part is to there is 20 or 21 can select the root node of left subtree or right subtree respectively as next analysis node.
Description of the drawings
Fig. 1 is that a certain 4 tunnel group of moment is connected the tree-shaped control structure of a certain group of cache.Circular is control section
Point, the rectangular representative first via (way1) to the 4th tunnel (way4).
Fig. 2 is that a certain 4 tunnel group of moment is connected the tree-shaped control structure of a certain group of cache.Ellipse is to introduce mistake
Control node accidentally；Circular is the control node for being not introduced into mistake；The rectangular representative first via (way1) is to the 4th tunnel
(way4), the interior expression flag bit of triangle, four-headed arrow represent flag bit and introduce the correspondence of the control node of mistake.
Fig. 3 is that a certain 8 tunnel group of moment is connected the tree-shaped control structure of a certain group of cache.For different graphic part
The same Fig. 2 of meaning.
Fig. 4 is the common structure of the processor containing two parts of processor core and cache.
Specific embodiment
In a tree-shaped control structure, each leaf node (mark cache is all the way) is containing 1 to 2 marks
Will position, i.e., per all the way there are one or two flag bits.If only 1, the value of flag bit is 0 or 1, if there is two
Position, then the value of the two flag bits is respectively 0 and 1.This is because for the node of different introducing mistakes, flag bit is not
It is certain identical.
Flag bit naming method is as follows：Using the node of introducing mistake analyzed as root node, in all of its left subtree
Road, flag bit is 0 for which, and on all roads of its right subtree, for which, flag bit is all 1.In this way, in addition to road 1
And road N, containing only being respectively other than 0 and 1 there are one flag bit, other roads are containing 2 flag bits 0 and 1, respectively for difference
Mistake introduce node.It may also be saved all the way for other mistakes with this with the flag bit for introducing node for same mistake all the way
The flag bit of point is identical, so as to fulfill mark bit multiplex.Fig. 2 and Fig. 3 is respectively illustrated under 4 tunnels and 8 tunnel group associative structures
Tree-shaped control structure and the flag bit that node is introduced for each mistake.It is wherein, round to represent non-introducing Wrong control node,
Ellipse represents the control node that mistake introduces, rectangular to represent per all the way, per the number in triangle below all the way, represents mark
Position.Four-headed arrow is the correspondence that flag bit and mistake introduce node.
The part-structure block diagram of a common processor is shown in Fig. 4.In figure, 401 be processor core, and 402 be high
Speed caching part.403 be the data storage section of cache, includes indicating bit for consistency protocol etc..Diagram displaying
One multichannel group associative structure (per being identified all the way with serial number 404), the storage of this part relate only to the storage of internal storage data with
And complete the flag bit storage of cache coherence.405 be the data replacement component of cache.405 according to 406 i.e. tree-shaped
Control node storage be replaced the selection of data, and each group of cache have a group mark register i.e. 407
Identify the value of tree-shaped control node.When cached data has been expired and data miss occurs, since root node, successively
The value of each control node is judged to select corresponding road and kick out of its content.The innovative point of this patent is to introduce structure
407 and 408, it is introduced for shift register group, and the mistake in each group (set) of cache introduces node
Contain one group of shift register 409.Meanwhile contain in 407 per the flag bit for introducing node for each mistake all the way.
When being cached data access, other than the tree-shaped control node in update 407, it is also necessary to by 407 per all the way
The flag bit of the node corresponding mistake in 408 is introduced into for each mistake introduces in the register group of node be updated.Into
When row replacement data selects, if the record value in the auxiliary shift register of present analysis node reaches pre-defined
It is required that replace left subtree or right subtree that component needs preferential selection auxiliary shift register to be indicated.
Claims (2)
1. for a group mark register of processor cache system and for recording the one of cache access group of shifting
The control bit that the least recently used replacement method of puppet of tree-shaped management is used is divided into " control bit for introducing mistake " by bit register
" control bit for being not introduced into mistake ", processor, can be by a series of marks when accessing multichannel set associative cache data every time
It is high when being replaced data selection in the shift register of will register shift deposit corresponding " control bit for being introduced into mistake "
It is comprehensive using pseudo- least recently used control bit and the data progress being recorded in itself shift register that speed caching replaces component
It closes and judges, and the priority of the latter is higher than the former.
2. tree-shaped administrative unit according to claim 1 and shift register：Its replacing of being calculated of shift register
Change the selection instruction of data, the adjustment that indicated condition can be appropriate according to the increase of way, it is however generally that, condition is displacement
Register only has 11 or only 10 selects two different subtrees.
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| CN201711210107.9A CN108182153A (en) | 2017-11-28 | 2017-11-28 | A kind of pseudo- least recently used data replacement method of improved cache |
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| CN201711210107.9A CN108182153A (en) | 2017-11-28 | 2017-11-28 | A kind of pseudo- least recently used data replacement method of improved cache |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116737609A (en) * | 2022-03-04 | 2023-09-12 | 格兰菲智能科技有限公司 | Method and device for selecting replacement cache line |
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- 2017-11-28 CN CN201711210107.9A patent/CN108182153A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116737609A (en) * | 2022-03-04 | 2023-09-12 | 格兰菲智能科技有限公司 | Method and device for selecting replacement cache line |
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