CN108174114A - Entropy computing device and entropy computational methods - Google Patents
Entropy computing device and entropy computational methods Download PDFInfo
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- CN108174114A CN108174114A CN201711291988.1A CN201711291988A CN108174114A CN 108174114 A CN108174114 A CN 108174114A CN 201711291988 A CN201711291988 A CN 201711291988A CN 108174114 A CN108174114 A CN 108174114A
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Abstract
The present invention provides a kind of entropy computing device and entropy computational methods, and described device includes standardized module for the number N according to i-th of gray-scale level pixel of image blockiObtain xiAnd mi；The computing module of logarithmic function fitting is used for NiAs the signal value of i-th of clock cycle, according to xiAnd miObtain the fitting of a polynomial output log2Ni；Multiplication module is used for the log2NiFitting output and NiIt is multiplied；Accumulator module is used to calculateAnd subtraction module subtracts the output valve of the accumulator module to obtain the entropy of the image block for calculating p, wherein, p=log2P, P are the sum of all pixels of the image block.Logarithmic function and entropy in method and device optimization entropy calculating provided by the invention calculate.
Description
Technical field
The present invention relates to digital integrated electronic circuit field more particularly to a kind of entropy computing device and entropy computational methods.
Background technology
Currently, the automatic exposure technology based on entropy, can Automatic-searching region-of-interest, and then adjust automatically each subregion
Weights so that the determining time for exposure and gain is more reasonable.
It is the calculation formula to Image entropy E in a region as shown in above-mentioned formula.piOccur for different grey-scale
Probability.Automatic exposure based on entropy calculates, and is inevitably related to the calculating to exponential function.But for digital circuit,
Add, subtract or shifting function is relatively easy, multiplication, index or logarithm operation, the complexity of corresponding circuits will ramp.Therefore,
Consider considering cost, time, it is right under the precise manner for ensureing to calculate in the automatic exposure Technology design based on entropy
The Simplicity in Design of number function is essential.
The existing correspondence Design of Digital Circuit scheme for logarithmic function is broadly divided into four classes：
1) the exponential function computational methods based on look-up table, the computational accuracy of this method are directly controlled by the size of look-up table
System, and with the promotion of computer capacity and computational accuracy, the size exponentially of look-up table rises.
2) Polynomial Approximation Method based on look-up table, this method need larger parameter to store empty in calculating process
Between；Need more complicated mlultiplying circuit；Meanwhile with the raising of precision and widening for computer capacity, parameter and mlultiplying circuit
Complexity exponentially rise.
3) the exponential function computational methods based on Taylor series expansion in certain range, can obtain higher meter
Precision is calculated, but widening with computer capacity is similar to polynomial approximation method, required parameter storage space and mlultiplying circuit
Complexity index rises.
4) CORDIC (Coordinate Rotation Digital Computer, Coordinate Rotation Digital computational methods) is calculated
Method is capable of the contradiction of COMPREHENSIVE CALCULATING precision and circuit complexity, but cordic algorithm system design complexity is higher, the design cycle
It is longer.To required precision, the not high automatic exposure based on entropy calculates, obviously not entirely appropriate using cordic algorithm.
Invention content
The present invention provides a kind of entropy computing device and entropy calculating side to overcome the problems of the above-mentioned prior art
Method is calculated with optimizing logarithmic function and entropy.
According to an aspect of the present invention, a kind of entropy computing device is provided, including：
Standardized module, for the number N according to i-th of gray-scale level pixel of image blockiObtain xiAnd mi, miIt is more
The integer part of item formula input, xiFor the fractional part of multinomial input, NiFor natural number, i is less than or equal to n's more than or equal to 0
Integer, n are the gray scale exponent number of image block；
The computing module of logarithmic function fitting, for by NiAs the signal value of i-th of clock cycle, according to xiAnd miIt obtains
Take the fitting of a polynomial output log2Ni, including：
K+1 computing unit, each computing unit include a sub- summation module and t sub- product modules, and k is institute
The exponent number of polynomial fitting is stated, t is the integer less than or equal to 2 more than or equal to 0, wherein,
In first computing unit to k-th of computing unit, r-th of computing unit is used for the r+1 computing unit
Output
+ 1 computing unit of kth is used to export
Wherein, xiAnd miAccording to formulaIt obtains, miFor integer, r be more than
It is less than or equal to the integer of k, p equal to 10~pkFor multinomial coefficient；
Multiplication module, for by the log2NiFitting output and NiIt is multiplied；
Accumulator module, for calculatingWherein, by the log2NiFitting output conduct
log2Ni；And
Subtraction module subtracts the output valve of the accumulator module to obtain the entropy of the image block for calculating p,
In, p=log2P, P are the sum of all pixels of the image block.
Optionally, under present clock period, signal value NiXiAnd miIt is calculated positioned at r-th of computing unit
Under next clock cycle, new signal value enters the computing module of logarithmic function fitting, signal value Ni+1
Xi+1And mi+1It is calculated positioned at r-th of computing unitAnd signal value NiXiAnd miPositioned at r+1
A computing unit calculatesWherein, i is integer, signal value Ni+1For signal value NiThe latter clock cycle
Under signal value.
Optionally, first computing unit includes a sub- summation module, and first computing unit is by based on second
Calculate unit output mi+p0。
Optionally, second computing unit includes a sub- summation module and a sub- product module, and second calculates list
Member is used to export m to third computing uniti+p0+p1xi, wherein, which is used to calculate p1xi, the sub- summation module
For the m for exporting first computing uniti+p0P is calculated with the subproduct module1xiIt is added.
Optionally, each computing unit includes a sub- summation module in third computing unit to+1 computing unit of kth
With two sub- product modules, in third computing unit to k-th of computing unit, r-th of computing unit is by based on r+1
Calculate unit outputWherein, a sub- product module in two sub- product modules is used to calculate xr-1,
Another subproduct module in two sub- product modules is used for willWith pr-1It is multiplied, which is used for the
What r-1 computing unit exportedWithIt is added.
Optionally, which is characterized in thatWherein, M NiMaximum bit numbers.
Optionally, the fitting exponent number of the polynomial fitting is higher, and the error of described device is lower.
According to another aspect of the invention, a kind of entropy computational methods are also provided,
According to the number N of i-th of gray-scale level pixel of image blockiObtain xiAnd mi, miFor multinomial input integer part,
xiFor the fractional part of multinomial input, NiFor natural number, xiAnd miCoincidence formula
M is positive integer, and i is the integer for being less than or equal to n more than or equal to 0, and n is the gray scale exponent number of image block,；
It calculatesAs log2NiFitting output, wherein, k be the polynomial fitting fitting rank
Number, p0To pkMultinomial coefficient for the polynomial fitting；
By log2NiFitting output as log2Ni, calculateTo obtain the entropy of the image block
Value, wherein, p=log2P, P are the sum of all pixels of the image block.
Optionally, 2m-1<M≤2m, wherein, M NiMaximum bit numbers.
Optionally, the fitting exponent number of the polynomial fitting is higher, and the error of described device is lower.
Compared with prior art, the present invention is based on polynomial approximation methods, comprehensive by being segmented, being migrated to entire computational domain
Close the requirement for considering precision and computational domain, it is proposed that the entropy computational methods and its circuit structure of a kind of optimization.It is advantageous that：
1) can be under the premise of precision be ensured, using simpler formula, less parameter is completed to logarithmic function
Fitting.And traditional polynomial approximation method, polynomial complexity are directly proportional to the size of zoning, i.e., with zoning
Expansion, polynomial parameters quantity and exponent number also expand therewith.But pair based on optimization polynomial approximation method that the present invention uses
Number Function Fitting schemes, by by the data of plurality magnitude, returning as fixed polynomial fitted area, due to the fitted area
Siding-to-siding block length is smaller, can complete to be fitted with less parameter.This feature greatly reduces to consume needed for parameter storage, simultaneously
Since parameter is reduced, the difficulty of fixed point also further reduces.
2) for different accuracy, the logarithmic function operation of different range, there are preferable autgmentabilities.Due to the spy of look-up table
Property, when the calculating for carrying out larger data, inevitably there is step phenomenon, i.e., the signal of adjacent two clock cycle
Value, there are larger data differences for corresponding data output.And logarithmic function computational methods of the present invention, reducing ginseng
While number, the characteristics of polynomial method continuity is preferable is still maintained.
3) it is adapted to the requirement of high speed circuit.Since the multiplication module of assembly line in entire calculating process, can be used,
In the case where the signal value bit wide of clock cycle is larger, adaptation height can be reached by increasing the series of multiplication module pipeline
The demand of fast clock.
4) powerful performance improves ability and autgmentability.Using of the present invention based on optimization fitting of a polynomial scheme
Its quantization of circuit and autgmentability are more stronger.Fitting precision can be effectively improved, and its cost is remote by increasing polynomial exponent number
Less than the scheme based on look-up table.By increasing miBit wide, can effectively extend calculate data range.
Description of the drawings
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature of the invention and advantage will become
It is more obvious.
Fig. 1 shows the flow chart of the entropy computational methods for automatic exposure according to embodiments of the present invention.
Fig. 2 shows the schematic diagrames of the entropy computing device for automatic exposure according to embodiments of the present invention.
Fig. 3 shows the structure diagram of middle logarithmic function fitting according to fig. 2.
Fig. 4 shows the structure diagram for the computing module being fitted according to the logarithmic function of the specific embodiment of the invention.
Fig. 5 shows the curve graph of multistage fitting exponent number and error relationship according to the present invention.
Fig. 6 shows the schematic diagram of the multinomial fixed point parameter according to the specific embodiment of the invention.
Fig. 7 is shown calculates key node result of calculation according to the log2 functions of the specific embodiment of the invention.
Fig. 8 shows the structure entirety key node result of calculation according to the specific embodiment of the invention.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be in any suitable manner incorporated in one or more embodiments.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note represents same or similar part, thus will omit repetition thereof.Attached some block diagrams shown in figure are work(
Can entity, not necessarily must be corresponding with physically or logically independent entity.Software form may be used to realize these work(
Entity or these functional entitys can be realized in one or more hardware modules or integrated circuit or at heterogeneous networks and/or place
These functional entitys are realized in reason device device and/or microcontroller device.
The present invention is based on polynomial approximation methods, by being segmented, being migrated to entire computational domain, consider precision and meter
Calculate the requirement in domain, it is proposed that the computational methods and computing device of entropy in a kind of automatic exposure.
The principle of the present invention is described below.Due to the particularity of digital circuit, all data are all binary representations, and
It is clearly nonsensical that the different truth of a matter is chosen in Image entropy calculating process, therefore the unified truth of a matter of choosing is 2.
Wherein, E is the entropy to be calculated, and n is image block gray scale exponent number, and i represents that i-th of gray-scale level (from 0 open by grayscale
Begin to start), P is the sum of pixel in image block, it is however generally that, P is fixed value, NiFor i-th gray-scale level pixel
Number, herein, piThe ratio of piecemeal sum of all pixels is accounted for for i-th of gray-scale level pixel.
miFor add factor, the integer part after logarithm operation is characterized, andM is NiPosition
Width, xiAs polynomial input, for calculating fractional part.Formula (2) is substituted into formula (1), can be obtained：
Due to xiDomain it is smaller, can be fitted with the polynomial equation of relatively low exponent number, specifically such as formula (4) institute
Show：
Obtain formula (5)
P=log2P (6)
In formula (5), p, p0~pjFor stable parameter, p is calculated by formula (6), p0~pjFor multinomial coefficient,
It can be obtained according to model of fit；xiAnd miAccording to the signal value N of clock cycleiIt obtains.In this way, the calculation optimization to Image entropy
Become the form of the sum of relatively simple product.It is as shown in Figure 1 to calculate basic procedure.
Fig. 1 shows the flow chart of the entropy computational methods for automatic exposure according to embodiments of the present invention.Fig. 1 shows altogether
5 steps are gone out：
It is step S110 first：According to the number N of i-th of gray-scale level pixel of image blockiObtain xiAnd mi, miIt is more
The integer part of item formula input, xiFor the fractional part of multinomial input, NiFor natural number.
Specifically, xiIt can be according to NiFixed point processing obtain.Wherein, M NiMaximum
Bit numbers.In step S110, dichotomy can be utilized according to NiMaximum bit numbers M calculate miValue.xiAnd miCoincidence formulaN、miFor positive integer；
Step S120：According to xiAnd miObtain the fitting of a polynomial output log2Ni。
Specifically,
Polynomial fitting can be expressed as：
Wherein, fitting exponent numbers of the k for polynomial fitting, p0~pkFor multinomial coefficient, according to log2(1+xi) fitting mould
Type obtains.
Step S130：It calculates
Specifically, step S130 can be realized by three steps：
Step S131：By log2NiFitting output and NiIt is multiplied.
Step S132：It calculatesN is the gray scale exponent number of image block.
Step S133：It calculatesTo obtain the entropy of the image block, wherein, p=
log2P, P are the sum of all pixels of the image block.
Entropy computing device provided by the invention is described below in conjunction with Fig. 2.Fig. 2 shows according to embodiments of the present invention
The schematic diagram of the computing device of entropy in automatic exposure.Entropy computing device can be realized by circuit structure.
Computing device 200 includes standardized module 201, the computing module 202 that logarithmic function is fitted, multiplication module 203, tires out
Add module 204, subtraction module 205.Optionally, entropy computing device 200 further includes Postponement module 206.
Standardized module 201 is used for the number N according to i-th of gray-scale level pixel of image blockiObtain xiAnd mi, miFor
The integer part of multinomial input, xiFor the fractional part of multinomial input, NiFor natural number.In the embodiment shown in Figure 2,
Standardized module 202 completes the data conversion to Ni signals and delay output according to valid (effective) signal.Clock cycle
Signal value NiFor a natural number, bit wide and size are depending on detailed programs.xiAnd miLogistic fit module 201 is corresponded to respectively
Fractional part fitting input and integer part, define it is identical with the data definition in formula (2).In some specific embodiments
In, the considerations of for digital circuit, xiIt needs to carry out fixed point processing.miCalculating by judging the bit numbers of data maximum
M and determine, for larger data, the realization that dichotomy accelerates the function can be used.
Logistic fit module 202 is used for according to xiAnd miObtain the fitting of a polynomial output log2Ni.Since data exist
It has completed to convert in standardized module 201, the range of fitting of a polynomial has been mapped to [0,1) in data area, it therefore, can be with
It is fitted by unified calculation formula.The precision and postpone by polynomial exponent number, parameter fixed point bit wide that data calculate
And xiFixed point bit wide codetermines.It is obtained by simulation calculation：The error of second order polynomial fit is less than 9 ‰, and three ranks are multinomial
The error of formula fitting is less than 1.3 ‰, and the error of fourth order polynomial fitting is less than 0.2 ‰.Fitting exponent number is higher, and error is smaller.And
Since data are by mapping, error is stablized in each subregion, can't increase as data increase.Preferably, it can be used
Three ranks are fitted, and error can be met the requirements.
Multiplication module 203 is used for the log2NiFitting output and NiIt is multiplied.Specifically, in the present embodiment, phase
Multiply module 203 for completing D1_Ni (NiPostpone for the first time) and enable signal val_d1 (valid useful signals are delayed for the first time)
Delay, depending on the clk numbers (clock periodicity) of delay are by logistic fit module 202, ensure the data D2_Ni (N of outputiThe
Secondary delay), the output of enable signal val_d2 (valid useful signals second be delayed) and logistic fit module 202 simultaneously
Reach multiplication module 203.Multiplication module 203 is used for log2(Ni) and D2_Ni (NiSecond of delay) in val_d2, (valid has
Effect signal second is delayed) control under be multiplied.Pipelining can be used in multiplication module 203, pipelining
Series is by NiBit wide determine, ensure corresponding timing requirements.
Accumulator module 204 is used to calculateN is the gray scale exponent number of image block.It is specific and
Speech, in the present embodiment, accumulator module 204 is by the output of multiplication module 203 In val_d3
It adds up under the control of (valid useful signals third time is delayed), considers the factors such as speed, it may be necessary to multistage flowing water.It is tired
The number added determines (number that n is image block gray-scale level) by n, and after n times add up, making cumulative data divided by P, (pixel is total
Number), and export result of calculation and data indication signal (valid).
Subtraction module 205 is used to calculateTo obtain the entropy of the image block,
In, p=log2P, P are the sum of all pixels of the image block.
Postponement module 206 is used for the input of delayed data and useful signal (data indication signal valid).
Referring to Fig. 3, Fig. 3 shows the structure diagram of the computing module 202 of middle logarithmic function fitting according to fig. 2.
As shown in figure 3, the computing module 202 of logarithmic function fitting includes k+1 computing unit (311 to 31k+1).Each
The computing unit includes a sub- summation module and t sub- product modules.K is the exponent number of the polynomial fitting.T be more than
It is less than or equal to 2 integer equal to 0.
In first computing unit to k-th of computing unit, r-th of computing unit is used for the r+1 computing unit
Output+ 1 computing unit of kth is used to exportWherein, x and m is according to formula N=
2m(1+x), 0≤x<1 obtains, and m is integer, and r is the integer less than or equal to k, p more than or equal to 10~pkFor multinomial coefficient.
Wherein, first computing unit 311 includes a sub- summation module 301, and first computing unit 311 is used for the
Two computing units 312 export m+p0。
Second computing unit 312 includes a sub- summation module 301 and a sub- product module 302, second calculating
Unit 312 is used to export m+p to third computing unit 3130+p1X, wherein, which is used to calculate p1X, should
Sub- summation module 301 is used for the m+p for exporting first computing unit 3110P is calculated with the subproduct module 3021X is added.
Each computing unit includes a son summation in third computing unit to+1 computing unit of kth (313 to 31k+1)
Module 301 and two sub- product modules 302 and 303, in third computing unit to k-th of computing unit (313 to 31k+1),
R-th of computing unit is used to export to the r+1 computing unitWherein, in two sub- product modules
A sub- product module 303 for calculating xr-1, another subproduct module 302 in two sub- product modules is used for will
xr-1With pr-1It is multiplied, which is used for export the r-1 computing unitWith pr-1xr-1
It is added.
The computing module 202 of logarithmic function fitting is applicable in pipelining, specifically, under present clock period, letter
Number value NiXiAnd miIt is calculated positioned at r-th of computing unitUnder next clock cycle, new signal
Value enters the computing device, signal value Ni+1Xi+1And mi+1It is calculated positioned at r-th of computing unit
And signal value NiXiAnd miIt is calculated positioned at the r+1 computing unitWherein, i is integer, signal value Ni+1
For signal value NiThe latter clock cycle under signal value.
Each module can be circuit module, for example, each subproduct module 302 and subproduct module 303 are multiplier, each son is asked
It is adder with module 301.
Specifically, in embodiments, the fitting exponent number of the polynomial fitting is higher, the logistic fit module
Error is lower.Further, the computing module 202 of logarithmic function fitting ensures to reach simultaneously in each node data, and count
Calculate accordingly result.Heavy line indicates data path.First subproduct module 303 is in addition to according to previous subproduct module 303
Result and xiIt also needs to carry out data cut position outside being multiplied.
A specific embodiment provided by the invention is described with reference to Fig. 4 to Fig. 8.Fig. 4 is shown to be had according to the present invention
The structure diagram of the computing module of the logarithmic function fitting of body embodiment.Fig. 5 shows multistage fitting rank according to the present invention
The curve graph of number and error relationship.Fig. 6 shows the schematic diagram of the multinomial fixed point parameter according to the specific embodiment of the invention.
Fig. 7 is shown calculates key node result of calculation according to the log2 functions of the specific embodiment of the invention.Fig. 8 is shown according to this hair
The structure entirety key node result of calculation of bright specific embodiment.Data E04 represents 10 4 powers in Fig. 6 to Fig. 8, and E08 is represented
10 8 powers.
In this embodiment it is assumed that result of calculation progress does not require excessively, (error is less than the fitting of a polynomial of 3 ranks of selection
‰) 1.3 meet the requirement of data.
15bit fixed points are carried out for multinomial coefficient fractional part, then its coefficient is as shown in Figure 6.
Input picture has carried out gray scale Data-Statistics, pixel number and each step result of calculation such as Fig. 7 in each gray-scale level
It is shown.
By N each in Fig. 7iAs the signal value of i-th of clock cycle, it is input in computing device shown in Fig. 2, works as Ni
After inputting standardized module, corresponding m is asked for by dichotomyiAnd xi.Wherein, miData output expand 2 15 powers
Times, the data fixed point of corresponding polynomial parameters 15bit.xiThe corresponding 16bit of data output data fixed point, correspondence is multinomial
The formula approximating function domain [0,1) value in.Corresponding output such as m in Fig. 7iAnd xiIt is shown.
Since multinomial selects function of third order to approach, the computing module 202 of corresponding logarithmic function fitting is (including 2 first
313,3 the second subproduct modules 312 of subproduct module and 4 sub- summation modules 311) it changes into as shown in Figure 4, for each
The result of calculation of each data shows corresponding position in the figure 7 in step.
Accumulator module carries out the value of input cumulative and carries out division arithmetic according to the val_d2 signals of input.It is general and
Speech, the total pixel number of statistical regions of selection is 2 power times, ensures that by simple shift operation division can be completed
Division arithmetic can be completed by simple shifter-adder mode in operation.Specifically implementation according to project depending on, no
One and foot.As shown in figure 8, list the output result that logarithm module output result corresponds to output with the module that is multiplied.It is tired out
Division arithmetic is summed it up, the output for obtaining accumulator module is 306888.
Due to p=367946 (when project determines, value determines), according to the output 306888 of accumulator module, easily acquire
The entropy of image entirety is 61068, which corresponds to the decimal fixed point of 15bit.
The considerations of in terms of analytical error, using this example as source, 2 rank multinomials, 3 rank multinomials and 4 are analyzed respectively
Rank multinomial log2 (x) functions result of calculation and actual value deviation, (4 rank curves are integrally close to error as shown in Figure 5 for bias contribution
It is 0,3 rank curves for lighter curve, 2 rank curves be the curve of maximum of rising and falling).Obviously fitting exponent number is higher, and accuracy is higher.When
Exponent number is raised to quadravalence from second order, and global error maximum value is reduced to 7 from 300, calculates error and is obviously reduced.
Above is only schematically to describe one or more embodiments of the invention, without prejudice to before present inventive concept
It puts, different change case is all within protection scope of the present invention.
In conclusion the shortcomings that present invention is mainly overcome in existing several Fuzzy Calculation schemes to Image entropy, relative to
Loop up table improves computer capacity, enhances scalability；Relative to traditional approximation by polynomi-als and Taylor series expansion
Method reduces the size of parameter space, extends computer capacity, simplifies approximating polynomial complexity；It is calculated relative to cordic
Method in relatively easy circuit logic, obtains computational accuracy and calculating speed very nearly the same.
The present invention has carried out Multiple Optimization, and synthesis is examined on the basis of polynomial approximation method, in algorithm and circuit level
The contradiction of hardware consumption and calculating speed is considered.
In algorithm level：Using the signal value of different clock cycle is mapped to [1,2) scheme in section, ensure it is more
Under the premise of item formula exponent number is limited and relatively low, the zoning of polynomial approximation method is effectively extended, and reduces unnecessary coefficient
Memory space.By will [1,2) result of calculation in section be mapped to [0,1) on section, eliminate because negative intercept is excessive and
The problem of caused decimal fixed point and calculating bit wide expand, meanwhile, ensure in data calculation process, the multistage clock cycle
The bit wide reduction of signal value can be carried out directly by cut position, greatly reduce the design difficulty of circuit.It is further to adopt
It is possibly realized with unified numerical procedure.Using traditional fitting of a polynomial scheme, the multinomial coefficient of smaller exponent number is obtained.
During calculating add factor and fractional part input, the thinking of dichotomy can be used, it can be in the signal value of clock cycle
Under the premise of bit wide is larger, obtain as early as possible needed for as a result, and carrying out fixed point, Reduction Computation flow in advance.
In terms of device circuit：Using assembly line thinking, the calculating of multiplication and addition is dispersed in calculation process, is ensured
The harmony of calculating so that timing strategy reaches opposite optimization.
Compared to the optimization logarithmic function numerical procedure based on look-up table that inventor proposes, the side proposed in of the invention
Case is obviously improved in terms of the promotion threshold degree of data computational accuracy, only need to accordingly be promoted polynomial exponent number, is counted
Calculating precision will be obviously improved.Meanwhile with the increase for calculating data area, entire function curve be it is gradual, will not
There is apparent alias, ensure the stability of data.
Compared with prior art, the present invention is based on polynomial approximation methods, comprehensive by being segmented, being migrated to entire computational domain
Close the requirement for considering precision and computational domain, it is proposed that the entropy computational methods and its circuit structure of a kind of optimization.It is advantageous that：
1) can be under the premise of precision be ensured, using simpler formula, less parameter is completed to logarithmic function
Fitting.And traditional polynomial approximation method, polynomial complexity are directly proportional to the size of zoning, i.e., with zoning
Expansion, polynomial parameters quantity and exponent number also expand therewith.But pair based on optimization polynomial approximation method that the present invention uses
Number Function Fitting schemes, by by the data of plurality magnitude, returning as fixed polynomial fitted area, due to the fitted area
Siding-to-siding block length is smaller, can complete to be fitted with less parameter.This feature greatly reduces to consume needed for parameter storage, simultaneously
Since parameter is reduced, the difficulty of fixed point also further reduces.
2) for different accuracy, the logarithmic function operation of different range, there are preferable autgmentabilities.Due to the spy of look-up table
Property, when the calculating for carrying out larger data, inevitably there is step phenomenon, i.e., the signal of adjacent two clock cycle
Value, there are larger data differences for corresponding data output.And logarithmic function computational methods of the present invention, reducing ginseng
While number, the characteristics of polynomial method continuity is preferable is still maintained.
3) it is adapted to the requirement of high speed circuit.Since the multiplication module of assembly line in entire calculating process, can be used,
In the case where the signal value bit wide of clock cycle is larger, adaptation height can be reached by increasing the series of multiplication module pipeline
The demand of fast clock.
4) powerful performance improves ability and autgmentability.Using of the present invention based on optimization fitting of a polynomial scheme
Its quantization of circuit and autgmentability are more stronger.Fitting precision can be effectively improved, and its cost is remote by increasing polynomial exponent number
Less than the scheme based on look-up table.By increasing miBit wide, can effectively extend calculate data range.
Those skilled in the art will readily occur to the disclosure its after considering specification and putting into practice invention disclosed herein
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principle of the disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as illustratively, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (10)
1. a kind of entropy computing device, which is characterized in that including：
Standardized module, for the number N according to i-th of gray-scale level pixel of image blockiObtain xiAnd mi, miIt is defeated for multinomial
The integer part entered, xiFor the fractional part of multinomial input, NiFor natural number, i is the integer less than or equal to n, n more than or equal to 0
Gray scale exponent number for image block；
The computing module of logarithmic function fitting, for by NiAs the signal value of i-th of clock cycle, according to xiAnd miObtain institute
State fitting of a polynomial output log2Ni, including：
K+1 computing unit, each computing unit include a sub- summation module and t sub- product modules, and k is the plan
Polynomial exponent number is closed, t is the integer less than or equal to 2 more than or equal to 0, wherein,
In first computing unit to k-th of computing unit, r-th of computing unit is used to export to the r+1 computing unit
+ 1 computing unit of kth is used to export
Wherein, xiAnd miAccording to formulaIt obtains, miFor integer, r be more than or equal to
1 is less than or equal to the integer of k, p0~pkFor multinomial coefficient；
Multiplication module, for by the log2NiFitting output and NiIt is multiplied；
Accumulator module, for calculatingWherein, by the log2NiFitting output conduct
log2Ni；And
Subtraction module subtracts the output valve of the accumulator module to obtain the entropy of the image block for calculating p, wherein, p=
log2P, P are the sum of all pixels of the image block.
2. entropy computing device as described in claim 1, which is characterized in that
Under present clock period, signal value NiXiAnd miIt is calculated positioned at r-th of computing unit
Under next clock cycle, new signal value enters the computing module of logarithmic function fitting, signal value Ni+1's
xi+1And mi+1It is calculated positioned at r-th of computing unitAnd signal value NiXiAnd miPositioned at r+1
Computing unit calculatesWherein, i is integer, signal value Ni+1For signal value NiThe latter clock cycle under
Signal value.
3. entropy computing device as described in claim 1, which is characterized in that first computing unit includes a son summation mould
Block, first computing unit are used to export m to second computing uniti+p0。
4. entropy computing device as claimed in claim 3, which is characterized in that second computing unit includes a son summation mould
Block and a sub- product module, second computing unit are used to export m to third computing uniti+p0+p1xi, wherein, the son
Product module is used to calculate p1xi, which is used for the m of first computing unit outputi+p0With the subproduct module
Calculate p1xiIt is added.
5. entropy computing device as claimed in claim 4, which is characterized in that third computing unit calculates list for+1 to kth
Each computing unit includes a sub- summation module and two sub- product modules in member, and third computing unit calculates single to k-th
In member, r-th of computing unit is used to export to the r+1 computing unitWherein, two subproducts
A mould product module in the block is used to calculate xr-1, another subproduct module in two sub- product modules is used for willWith pr-1It is multiplied, which is used for export the r-1 computing unitWithIt is added.
6. such as meter entropy computing device described in any one of claim 1 to 5, which is characterized in that it is characterized in that,Wherein, M is the maximum bit numbers of N.
7. such as entropy computing device described in any one of claim 1 to 5, which is characterized in that the fitting of the polynomial fitting
Exponent number is higher, and the error of described device is lower.
8. a kind of entropy computational methods, which is characterized in that
According to the number N of i-th of gray-scale level pixel of image blockiObtain xiAnd mi, miFor the integer part of multinomial input, xi
For the fractional part of multinomial input, NiFor natural number, xiAnd miCoincidence formula
M is positive integer, and i is the integer for being less than or equal to n more than or equal to 0, and n is the gray scale exponent number of image block,；
It calculatesAs log2NiFitting output, wherein, k be the polynomial fitting fitting exponent number, p0
To pkMultinomial coefficient for the polynomial fitting；
By log2NiFitting output as log2Ni, calculateTo obtain the entropy of the image block,
In, p=log2P, P are the sum of all pixels of the image block.
9. entropy computational methods as claimed in claim 8, which is characterized in that it is characterized in that, 2m-1<M≤2m, wherein, M N
Maximum bit numbers.
10. entropy computational methods as claimed in claim 8, which is characterized in that the fitting exponent number of the polynomial fitting is higher,
The error of described device is lower.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111380650A (en) * | 2020-06-01 | 2020-07-07 | 深圳市千分一智能技术有限公司 | Pressure curve calibration method, device, equipment and readable storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090303347A1 (en) * | 2008-06-09 | 2009-12-10 | Jae-Hyun Kwon | Method and apparatus for obtaining image using entropy |
| CN102903084A (en) * | 2012-09-25 | 2013-01-30 | 哈尔滨工程大学 | Estimation method of wavelet domain image noise variance under alpha stable model |
| CN103942807A (en) * | 2014-05-09 | 2014-07-23 | 北京交通大学 | Real-time processing fast image block fusion system and fusion method |
| US20140369568A1 (en) * | 2013-06-13 | 2014-12-18 | The Charles Stark Draper Laboratory, Inc. | Detecting Species Diversity by Image Texture Analysis |
| CN105635597A (en) * | 2015-12-21 | 2016-06-01 | 湖北工业大学 | Auto-exposure method and system for vehicle-mounted camera |
| CN106506983A (en) * | 2016-12-12 | 2017-03-15 | 天津大学 | A kind of HDR video generation methods suitable for LDR videos |
| CN106657803A (en) * | 2016-12-26 | 2017-05-10 | 中国科学院长春光学精密机械与物理研究所 | Automatic exposure method for high-speed camera applied to electro-optic theodolite |
-
2017
- 2017-12-08 CN CN201711291988.1A patent/CN108174114B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090303347A1 (en) * | 2008-06-09 | 2009-12-10 | Jae-Hyun Kwon | Method and apparatus for obtaining image using entropy |
| CN102903084A (en) * | 2012-09-25 | 2013-01-30 | 哈尔滨工程大学 | Estimation method of wavelet domain image noise variance under alpha stable model |
| US20140369568A1 (en) * | 2013-06-13 | 2014-12-18 | The Charles Stark Draper Laboratory, Inc. | Detecting Species Diversity by Image Texture Analysis |
| CN103942807A (en) * | 2014-05-09 | 2014-07-23 | 北京交通大学 | Real-time processing fast image block fusion system and fusion method |
| CN105635597A (en) * | 2015-12-21 | 2016-06-01 | 湖北工业大学 | Auto-exposure method and system for vehicle-mounted camera |
| CN106506983A (en) * | 2016-12-12 | 2017-03-15 | 天津大学 | A kind of HDR video generation methods suitable for LDR videos |
| CN106657803A (en) * | 2016-12-26 | 2017-05-10 | 中国科学院长春光学精密机械与物理研究所 | Automatic exposure method for high-speed camera applied to electro-optic theodolite |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111380650A (en) * | 2020-06-01 | 2020-07-07 | 深圳市千分一智能技术有限公司 | Pressure curve calibration method, device, equipment and readable storage medium |
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