CN108173623B - User-defined baseband frame packaging method based on sliding CRC - Google Patents
User-defined baseband frame packaging method based on sliding CRC Download PDFInfo
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- CN108173623B CN108173623B CN201810037908.8A CN201810037908A CN108173623B CN 108173623 B CN108173623 B CN 108173623B CN 201810037908 A CN201810037908 A CN 201810037908A CN 108173623 B CN108173623 B CN 108173623B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
Abstract
The invention discloses a self-defined baseband frame packaging method based on sliding CRC, which adopts the following steps when the self-defined baseband frame packaging data is sent: performing head CRC calculation on the 8-bit parallel data by adopting a head CRC calculation module; adding a header CRC by adopting a header CRC adding module; adding information data by adopting a data insertion module; and a data bit width conversion module is adopted to convert the 8-bit parallel data into 4-bit parallel data. The following steps are adopted when the user-defined baseband frame decapsulated data is received: converting 4-bit parallel data into 8-bit parallel data by adopting a data bit width conversion module; a sliding CRC frame header synchronization module is adopted to carry out sliding CRC frame header synchronization, and frame header flags sof and eof are output; and extracting the information data through an information data extraction module according to the sof. The occupancy rate of the information field is improved by adding 4 bytes of redundant information; the synchronous of the encapsulation packets is realized by adopting the sliding CRC, so that the redundant information can be reduced to the maximum extent, and the code design difficulty is reduced.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a baseband frame synchronization method of wireless communication equipment.
Background
The widely used baseband frame encapsulation protocols in the industry at present are GSE and HDLC, but the efficiency of both types of encapsulation is not very high. In the satellite communication field, the bit information of 1 baseband frame is mapped into symbols of a plurality of physical frames, and the channel bandwidth determines the transmission rate of the physical frames, so the encapsulation efficiency of the baseband frames is very important. A low efficiency encapsulation method will bring a considerable transmission delay, while a high efficiency encapsulation method can guarantee a low delay of information, thereby making the service signals of video, voice, etc. more smooth.
The GSE protocol is a data encapsulation protocol widely used in satellite devices. The GSE data is mainly composed of a GSE header and a PDU (packet data unit). The PDU value needs to be encapsulated in data unit, which may be network layer protocol data, and may also use ETH protocol data, etc.
The GSE header format is as follows:
the GSE packetization format is as follows:
the existing HDLC encapsulation method divides the data frame into 5 fields: a mark field, an address field, a control field, an information field and a check field; using transparent transmission, the fields except the flag field are inserted with "0 bit" so that the flag field is not present, and the data packet is recovered when being decapsulated.
The specific packaging format is as follows:
sign field | Address field | Control field | Information field | Check field | Sign field |
8bit(0x7E) | 8bit | 8bit/16bit | 8nbit | 16bit(CRC16) | 8bit(0x7E) |
Disclosure of Invention
The invention provides a self-defined baseband frame packaging method based on sliding CRC (cyclic redundancy check), which is used for solving the defects of the prior art and solving the problem of packaging efficiency of a baseband frame in a wireless communication process.
In order to achieve the purpose of the invention, the following technology is adopted:
a self-defined baseband frame encapsulation method based on sliding CRC is characterized in that the encapsulation format of baseband frame encapsulation is as follows:
head part | Head verification | Information field |
16bit | 16bit(CRC16) | 8nbit |
The custom baseband frame encapsulation method comprises custom baseband frame encapsulation data sending and custom baseband frame decapsulation data receiving.
The following steps are adopted when the user-defined baseband frame encapsulation data is sent:
step 1): performing head CRC calculation on the 8-bit parallel data by adopting a head CRC calculation module;
step 2): adding a header CRC by adopting a header CRC adding module;
step 3): adding information data by adopting a data insertion module;
step 4): and a data bit width conversion module is adopted to convert the 8-bit parallel data into 4-bit parallel data.
The following steps are adopted when the user-defined baseband frame decapsulated data is received:
step 1): converting 4-bit parallel data into 8-bit parallel data by adopting a data bit width conversion module;
step 2): a sliding CRC frame header synchronization module is adopted to carry out sliding CRC frame header synchronization, and frame header flags sof and eof are output;
step 3): and extracting the information data through an information data extraction module according to soft.
The sliding CRC frame header synchronization module consists of 1 4-byte shift register, a parallel CRC16 calculator 1, a CRC16 calculator 2 and a frame header synchronization decision device;
CRC16 calculator 1 and CRC16 calculator 2 are both 8bit CRC16 calculators;
the 4-byte shift register is respectively connected with a CRC16 calculator 1 and a CRC16 calculator 2, the CRC16 calculator 1 and the CRC16 calculator 2 are circularly restarted by adopting a restart signal after being connected in parallel, and the CRC16 calculator 1 and the CRC16 calculator 2 are connected to the frame header synchronization decider in parallel.
The technical scheme has the advantages that:
1. the invention increases the occupancy rate of the information field by adding the redundant information of 4 bytes.
2. The invention realizes the synchronization of the encapsulation packet by adopting the sliding CRC, can reduce redundant information to the maximum extent and reduce the code design difficulty.
Drawings
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings. Wherein:
fig. 1 shows a flow chart of custom baseband frame encapsulation data transmission in the present invention.
Fig. 2 shows a flow chart of receiving custom baseband frame decapsulated data in the present invention.
Fig. 3 shows a schematic structural diagram of a frame header synchronization decision device in the present invention.
Detailed Description
As shown in fig. 1 to fig. 3, a self-defined baseband frame encapsulation method based on sliding CRC, the encapsulation format of the baseband frame encapsulation is:
head part | Head verification | Information field |
16bit | 16bit(CRC16) | 8nbit |
The custom baseband frame encapsulation method comprises custom baseband frame encapsulation and custom baseband frame decapsulation.
The following steps are adopted when the user-defined baseband frame encapsulation data is sent:
step 1): performing head CRC calculation on the 8-bit parallel data by adopting a head CRC calculation module;
step 2): adding a header CRC by adopting a header CRC adding module;
step 3): adding information data by adopting a data insertion module;
step 4): and a data bit width conversion module is adopted to convert the 8-bit parallel data into 4-bit parallel data.
The following steps are adopted when the user-defined baseband frame decapsulated data is received:
step 1): converting 4-bit parallel data into 8-bit parallel data by adopting a data bit width conversion module;
step 2): a sliding CRC frame header synchronization module is adopted to carry out sliding CRC frame header synchronization, and frame header flags sof and eof are output;
step 3): and extracting the information data through an information data extraction module according to soft.
The sliding CRC frame header synchronization module consists of 1 4-byte shift register, a parallel CRC16 calculator 1, a CRC16 calculator 2 and a frame header synchronization decision device;
CRC16 calculator 1 and CRC16 calculator 2 are both 8bit CRC16 calculators;
the 4-byte shift register is respectively connected with a CRC16 calculator 1 and a CRC16 calculator 2, the CRC16 calculator 1 and the CRC16 calculator 2 are circularly restarted by adopting a restart signal after being connected in parallel, and the CRC16 calculator 1 and the CRC16 calculator 2 are connected to the frame header synchronization decider in parallel.
Compared with the prior art, the invention improves the occupancy rate of the information field by adding 4 bytes of redundant information; the synchronous of the encapsulation packets is realized by adopting the sliding CRC, so that the redundant information can be reduced to the maximum extent, and the code design difficulty is reduced.
The above is only a preferred embodiment of the present invention and is not intended to limit the present invention, and it is apparent that those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (1)
1. A self-defined baseband frame encapsulation method based on sliding CRC is characterized in that the encapsulation format of the baseband frame encapsulation is as follows:
The user-defined baseband frame encapsulation method comprises user-defined baseband frame encapsulation data sending and user-defined baseband frame de-encapsulation data receiving;
the method comprises the following steps of sending custom baseband frame encapsulation data:
step 1): performing head CRC calculation on the 8-bit parallel data by adopting a head CRC calculation module;
step 2): adding a header CRC by adopting a header CRC adding module;
step 3): adding information data by adopting a data insertion module;
step 4): a data bit width conversion module is adopted to convert the 8-bit parallel data into 4-bit parallel data;
the user-defined baseband frame de-encapsulation data receiving method comprises the following steps:
step 1): converting 4-bit parallel data into 8-bit parallel data by adopting a data bit width conversion module;
step 2): a sliding CRC frame header synchronization module is adopted to carry out sliding CRC frame header synchronization, and frame header flags sof and eof are output;
step 3): extracting information data through an information data extraction module according to the sof;
the sliding CRC frame header synchronization module consists of 1 4-byte shift register, a parallel CRC16 calculator 1, a CRC16 calculator 2 and a frame header synchronization decision device;
the CRC16 calculator 1 and the CRC16 calculator 2 are both 8-bit CRC16 calculators;
the 4-byte shift register is respectively connected with a CRC16 calculator 1 and a CRC16 calculator 2, the CRC16 calculator 1 and the CRC16 calculator 2 are circularly restarted by adopting a restart signal after being connected in parallel, and the CRC16 calculator 1 and the CRC16 calculator 2 are connected to a frame header synchronization decision device in parallel.
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