Invention content
In order to solve the above technical problem, the present invention provides the control circuit and method of a kind of photovoltaic generating system, energy
Enough two-way extensions for realizing switch, control frequency and control algolithm size of code.
In order to reach the object of the invention, what the technical solution of the embodiment of the present invention was realized in:
An embodiment of the present invention provides a kind of control circuit of photovoltaic generating system, including first processor and second processing
Device, wherein:
For generating fractional frequency signal, fractional frequency signal is exported to second processor for first processor;Receive second processor
Sampled data and Voltage loop control result of calculation, according to sampled data and Voltage loop control result of calculation realize current loop control
The calculating of algorithm generates the control signal of photovoltaic generating system according to current loop control result of calculation;
Second processor, for receiving fractional frequency signal, triggering generates sampled data;Based on first frequency by sampled data
It exports to first processor;The calculating of Voltage loop control algolithm is realized based on second frequency and sampled data, Voltage loop is controlled
Result of calculation is exported to first processor, and first frequency is more than second frequency.
Further, the first processor is on-site programmable gate array FPGA processor.
Further, the second processor is Digital Signal Processing dsp processor, advanced reduced instruction set machine ARM
Processor or microcontroller.
Further, the first processor includes system clock unit, control algolithm unit and data interactive unit, institute
It states second processor and includes sampling unit and interrupt location, wherein:
For generating fractional frequency signal, fractional frequency signal is exported to sampling unit for system clock unit;
Sampling unit, for receiving the fractional frequency signal of system clock unit output, triggering generates sampled data;Based on first
Frequency exports sampled data to control algolithm unit, is exported sampled data to interrupt location, and first based on second frequency
Frequency is more than second frequency;
Control algolithm unit for receiving sampled data, reads the Voltage loop control result of calculation of data interaction unit, root
The calculating of current loop control algorithm is realized according to sampled data and Voltage loop control result of calculation, according to current loop control result of calculation
Generate the control signal of photovoltaic generating system;
Interrupt location for receiving sampled data, the calculating of Voltage loop control algolithm is realized according to sampled data, by voltage
Ring control result of calculation is exported to data interaction unit;
Data interaction unit, for storing Voltage loop control result of calculation.
Further, the second processor further includes external clock unit, wherein:
External clock unit for generating clock pulse signal, and passes through input and output I/O interface by the clock arteries and veins of generation
Signal is rushed to export to the system clock unit.
Further, the control algolithm unit is additionally operable to, and the current loop control result of calculation is stored to the number
According to interactive unit;
The interrupt location is additionally operable to, and the electric current loop of the data interaction unit is read by external memory connecting interface
Control result of calculation;
The data interaction unit is additionally operable to, and stores the current loop control result of calculation.
Further, the system clock unit is additionally operable to, and generates pulse width modulation (PWM) carrier signal, and PWM is carried
Wave signal is exported to control algolithm unit;
The control signal that photovoltaic generating system is generated according to current loop control result of calculation of the control algolithm unit, tool
Body includes:
PWM carrier signals are modulated according to the current loop control result of calculation, generate the photovoltaic generating system
Control signal.
Further, the sampling unit is exported the sampled data to described by external memory connecting interface
Control algolithm unit;
The interrupt location is exported Voltage loop control result of calculation to described by external memory connecting interface
Data interaction unit.
Further, the photovoltaic generating system includes sequentially connected photovoltaic array, DC boosting unit, three-phase inversion
Unit, LC filter units;
The control signal of the photovoltaic generating system includes the DC control pulse signal for controlling DC boosting unit
With for controlling the inversion control pulse signal of three-phase inversion unit.
Further, the Voltage loop control algolithm includes:It is the maximum power point tracking algorithm of the photovoltaic array, described
The nominal input voltage of three-phase inversion unit adjusts the DC voltage regulation algorithm of algorithm and the DC boosting unit.
Further, the current loop control algorithm includes:The DC current of the DC boosting unit adjusts algorithm, institute
State the D axial vector current regulation algorithms of three-phase inversion unit and the Q axial vector current regulation algorithms of the three-phase inversion unit.
The embodiment of the present invention additionally provides a kind of control method of photovoltaic generating system, including:
First processor generates fractional frequency signal, and fractional frequency signal is exported to second processor;
Second processor receives fractional frequency signal, and triggering is generated sampled data, exported sampled data based on first frequency
To first processor;The calculating of Voltage loop control algolithm is realized based on second frequency and according to sampled data, and by Voltage loop control
Result of calculation processed is exported to first processor, and first frequency is more than second frequency;
First processor receives sampled data and Voltage loop control result of calculation, according to sampled data and Voltage loop control meter
The calculating that result realizes current loop control algorithm is calculated, the control that photovoltaic generating system is generated according to current loop control result of calculation is believed
Number.
Technical scheme of the present invention has the advantages that:
The control circuit and method of photovoltaic generating system provided by the invention, by sharing second processing by first processor
The sampled data of device and the calculating that electric current loop algorithm is realized in first processor, realize switch, control frequency and control
The two-way extension of algorithmic code amount enhances the control system bandwidth and system stability of inverter.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature mutually can arbitrarily combine.
As shown in Fig. 2, a kind of control circuit of photovoltaic generating system according to the present invention, including 201 He of first processor
Second processor 202, wherein:
For generating fractional frequency signal, fractional frequency signal is exported to second processor 202 for first processor 201;Receive second
Sampled data and Voltage loop the control result of calculation of processor 202, are realized according to sampled data and Voltage loop control result of calculation
The calculating of current loop control algorithm generates the control signal of photovoltaic generating system according to current loop control result of calculation;
Second processor 202, for receiving fractional frequency signal, triggering generates sampled data;It will be sampled based on first frequency
Data are exported to first processor 201;The calculating of Voltage loop control algolithm is realized based on second frequency and sampled data, by voltage
Ring control result of calculation is exported to first processor 201, and first frequency is more than second frequency.
It should be noted that photovoltaic generating system of the present invention can be grid-connected photovoltaic system, or
Photovoltaic stand alone type electricity generation system;Sampled data of the present invention includes photovoltaic array voltage sample value, photovoltaic array electric current is adopted
The sampling of the voltage sample value of capacitance, the sampled value of three-phase mains phase voltage, three-phase mains line current above and below sample value, dc bus
Value, DC bus-bar voltage sampled value etc..The first processor 201 and second processor 202 of the present invention shares second processor 202
AD sampling modules, save for first processor 201 be configured great number cost AD sampling A/D chips, greatly reduce control circuit
Cost.
Further, the first processor 201 can be field programmable gate array (Field Programmable
Gate Array, FPGA) processor or the future may appear ratio FPGA processors with better function, the present invention do not do this
Limitation.
Further, the second processor 202 can be dsp processor, advanced reduced instruction set machine (Advanced
RISC Machine, ARM) processor or microcontroller etc..
Further, as shown in figure 3, first processor 201 includes system clock unit 2011, control algolithm unit 2012
With data interactive unit 2013;Second processor 202 includes sampling unit 2021 and interrupt location 2022, wherein:
For generating fractional frequency signal, fractional frequency signal is exported to sampling unit 2021 for system clock unit 2011;
Sampling unit 2021, for receiving the fractional frequency signal of the output of system clock unit 2011, triggering generates sampled data;
Sampled data is exported to control algolithm unit 2012 based on first frequency, is exported sampled data to interruption based on second frequency
Unit 2022, and first frequency is more than second frequency;
Control algolithm unit 2012 for receiving sampled data, reads the Voltage loop control meter of data interaction unit 2013
It calculates as a result, the calculating of current loop control algorithm is realized according to sampled data and Voltage loop control result of calculation, according to electric current loop control
The control signal of result of calculation generation photovoltaic generating system processed;
For receiving sampled data, the calculating of Voltage loop control algolithm is realized according to sampled data for interrupt location 2022, will
Voltage loop control result of calculation is exported to data interaction unit 2013;
Data interaction unit 2013, for storing Voltage loop control result of calculation.
Further, second processor 202 further includes external clock unit, wherein:
External clock unit for generating clock pulse signal, and passes through input and output I/O interface by the clock arteries and veins of generation
Signal is rushed to export to system clock unit 2011.
Further, control algolithm unit 2012 is additionally operable to, and current loop control result of calculation is stored to data interaction list
Member 2013;
Interrupt location 2022 is additionally operable to, by external memory connecting interface (External Memory Interface,
EMIF the current loop control result of calculation of data interaction unit 2013) is read;
Data interaction unit 2013 is additionally operable to, and stores current loop control result of calculation.
Further, system clock unit 2011 is additionally operable to, generation pulse width modulation (Pulse Width
Modulation, PWM) carrier signal, and PWM carrier signals are exported to control algolithm unit 2012;
The control signal that photovoltaic generating system is generated according to current loop control result of calculation of control algolithm unit 2012, tool
Body includes:
PWM carrier signals are modulated according to the current loop control result of calculation, generate the control of photovoltaic generating system
Signal processed.
Further, sampling unit 2021 is exported sampled data to control algolithm unit 2012 by EMIF interfaces;
Interrupt location 2022 is exported Voltage loop control result of calculation to data interaction unit 2013 by EMIF interfaces.
Further, photovoltaic generating system includes sequentially connected photovoltaic array, DC boosting unit, three-phase inversion list
Member, LC filter units;
The control signal of photovoltaic generating system includes the DC control pulse signal of control DC boosting unit and control three
The inversion control pulse signal of phase inversion unit.
Further, Voltage loop control algolithm includes:Maximum power point tracking algorithm, the three-phase inversion unit of photovoltaic array
Nominal input voltage adjust the DC voltage regulation algorithm of algorithm and DC boosting unit.
Further, current loop control algorithm includes:The DC current of DC boosting unit adjusts algorithm, three-phase inversion list
The D axial vector current regulation algorithms of member and the Q axial vector current regulation algorithms of three-phase inversion unit.
It should be noted that the present invention is utilized using the software control framework of DSP+FPGA structure photovoltaic generating systems
Data processing advantage fast parallel FPGA completes power grid phaselocked loop, the control of inverter current ring, DC boosting (Boost) electric current loop
Control and PWM modulation calculate the operation of each unit, so as to fulfill switch, the high-frequency therapeutic treatment of control frequency, and then improve inversion electricity
The control bandwidth of ring, Boost electric current loops is flowed, reduces inversion inductor inductance value, FPGA parallel datas treatment mechanism can be completed each time
Harmonic wave individually control and compensation.Power grid phaselocked loop, electric current loop, PWM modulation operation program are stripped out from DSP simultaneously, also can
The space of bigger is brought to DSP controlling cycles, increases more control algolithms.
As shown in figure 4, the embodiment of the present invention additionally provides a kind of control method of photovoltaic generating system, including walking as follows
Suddenly:
Step 401:First processor generates fractional frequency signal, and fractional frequency signal is exported to second processor;
Step 402:Second processor receives fractional frequency signal, and triggering generates sampled data, will be sampled based on first frequency
Data are exported to first processor;The calculating of Voltage loop control algolithm is realized based on second frequency and according to sampled data, and will
Voltage loop control result of calculation is exported to first processor, and first frequency is more than second frequency;
Step 403:First processor receives sampled data and Voltage loop control result of calculation, according to sampled data and voltage
Ring control result of calculation realizes the calculating of current loop control algorithm, and photovoltaic generating system is generated according to current loop control result of calculation
Control signal.
It should be noted that photovoltaic generating system of the present invention can be grid-connected photovoltaic system, or
Photovoltaic stand alone type electricity generation system;Sampled data of the present invention includes photovoltaic array voltage sample value, photovoltaic array electric current is adopted
The sampling of the voltage sample value of capacitance, the sampled value of three-phase mains phase voltage, three-phase mains line current above and below sample value, dc bus
Value, DC bus-bar voltage sampled value etc..
Further, the first processor 201 can be FPGA processor or the future may appear than FPGA function
More powerful processor, the present invention are without limitation.
Further, the second processor 202 can be dsp processor, arm processor or microcontroller etc..
Further, it is further included before the method:
Second processor generates clock pulse signal, and passes through I/O interface and export the clock pulse signal of generation to first
Processor.
Further, the control signal that photovoltaic generating system is generated according to current loop control result of calculation, including:
First processor generates PWM carrier signals;
First processor is modulated PWM carrier signals according to current loop control result of calculation, generation photovoltaic generation system
The control signal of system.
Further, second processor is exported sampled data to first processor by EMIF interfaces;
Second processor is exported Voltage loop control result of calculation to first processor by EMIF interfaces.
Further, photovoltaic generating system includes sequentially connected photovoltaic array, DC boosting unit, three-phase inversion list
Member, LC filter units;
The control signal of photovoltaic generating system includes the DC control pulse signal of control DC boosting unit and control three
The inversion control pulse signal of phase inversion unit.
Further, Voltage loop control algolithm includes:Maximum power point tracking algorithm, the three-phase inversion unit of photovoltaic array
Nominal input voltage adjust the DC voltage regulation algorithm of algorithm and DC boosting unit.
Further, current loop control algorithm includes:The DC current of DC boosting unit adjusts algorithm, three-phase inversion list
The D axial vector current regulation algorithms of member and the Q axial vector current regulation algorithms of three-phase inversion unit.
The embodiment of the present invention additionally provides several preferred embodiments and the present invention is further expalined, but is worth note
Meaning, the preferred embodiment are intended merely to preferably describe the present invention, do not form and the present invention is improperly limited.Following
Each embodiment can be individually present, and the technical characterstic in different embodiment can be combined to combine in one embodiment and be made
With.
This preferred embodiment is fast parallel using FPGA using DSP+FPGA structure photovoltaic DC-to-AC converter software control frameworks
Data processing advantage completes power grid phaselocked loop, the control of inverter current ring, Boost current loop controls and PWM modulation and calculates each unit
Operation, so as to fulfill switch, the high-frequency therapeutic treatment of control frequency, and then improve the control band of inverter current ring, Boost electric current loops
Width, reduces inversion inductor inductance value, and FPGA parallel datas treatment mechanism can complete each harmonic individually control and compensation.Electricity simultaneously
Net phaselocked loop, electric current loop, PWM modulation operation program are stripped out from DSP, and the sky of bigger can be also brought to DSP controlling cycles
Between, increase more control algolithms.
In inverter software control framework in the preferred embodiment, dsp chip is responsible for modulus (Analog
Digital, AD) sampling, direct memory access (Direct Memory Access, DMA) data carry, external memory connection
Interface (EMIF) communication, the control of inverter voltage ring, the control of Boost Voltage loops, maximum power point tracking (Maximum Power
Point Tracking, MPPT) etc.;Fpga chip is responsible for reference signal generation synchronization time, the processing of EMIF communication datas, power grid
Phaselocked loop, inverter current ring, Boost electric current loops, the generation modulation of PWM carrier waves etc..
Using EMIF communication modes, DSP uses chip selection signal, read signal, writes for DSP and FPGA communications in this preferred embodiment
Signal, 8 bit address lines and 16 position datawires realize 150MHz parallel communications, are divided into transmission AD samplings, instruction and read FPGA prisons
Control three groups of data realizations and the data transmission of FPGA.
Due to cost considerations, FPGA and dsp chip share the AD sampling modules of DSP to this preferred embodiment, save for
The AD sampling A/D chips of great number cost are configured in FPGA.
This preferred embodiment includes a kind of AD sampled datas based on two-way DMA (direct memory access) and is transferred to FPGA's
Method, mono- tunnels of DMA carry AD sampled datas to external storage address, quickly pass to FPGA by EMIF, FPGA receives data
After be latched into local RAM, another way DMA carries AD sampled datas to DSP locals RAM, while triggers DMA interruption (DSP inverters
Control main interruption) carry out and FPGA instruction, the transmission of monitoring data and the algorithm part of DSP oneself, mainly including inversion
Control Voltage loop, Boost control Voltage loops etc..
This preferred embodiment includes a kind of DSP and FPGA algorithms sequential synchronous method, FPGA time references unit generation PWM
Carrier wave is modulated, while identical frequency pulse signal is sent out, and then trigger the analog-to-digital conversion (Analog-to- of DSP by I/O port
Digital Convert, ADC) it samples, ADC samplings complete triggering DMA and pass FPGA progress back by EMIF transmissions AD sampled datas
The control algolithm of power grid phaselocked loop, electric current loop, it is synchronous with PWM carrier signals so as to fulfill AD data transmissions, control algolithm.
Fig. 1 is conventional single-core processor photovoltaic DC-to-AC converter software control structure figure, and Fig. 5 is the DSP+ of this preferred embodiment
FPGA dual core processor photovoltaic DC-to-AC converter software control block diagrams, wherein, each module declaration is as follows:
101 be photovoltaic array (photovoltaic array, PV array), and solar energy is converted into the dress of electric energy
It puts;102 be DC chopped-wave boosting link (boosted switch power supply) Boost, for DC boosting;103 is (more for three phase power device
For IGBT) inverter bridge, for being three-phase alternating voltage by DC voltage inversion;104 be LC filter circuits, sometimes also with LCL etc.
Other forms topology, for pwm pulse type voltage filter and current loop control etc.;105 be alternating current or other power grids;106 be straight
Flow PWM (pulse width modulation), the pulse signal of driving Boost work, for controlling the voltage of PV;107 be for DC PWM
Proportional integration (PI) adjuster of duty cycle adjustment;108 be the pi regulator of the adjusting for DC voltage;109 be maximum work
Rate point tracking MPPT, for the maximum power point of Tracing PV;110 be phaselocked loop, and for locking grid phase, (alternating current phase is same
Step), the DQ shaft voltages for DQ vector controlleds are provided;111 for Clark transformation, (three-phase static coordinate system is to two-phase static coordinate
The transformation of system) and Park transformation (transformation of the two-phase stationary coordinate system to two-phase rotating coordinate system), for by grid-connected three-phase current
Sample AC value is transformed to DQ two-phase D. C. values;112 be state space pwm unit (SVPWM), inverse for generating
Become control pulsed drive three phase inverter bridge;113 for Ipark, (Park inverse transformations, i.e. two-phase rotating coordinate system are to two-phase static coordinate
The transformation of system), for being the voltage under two-phase stationary coordinate system by DQ axis control voltage transformation, it is provided as SVPWM links;114
Pi regulator for the adjusting for being used for D axial vector electric currents;115 be for the adjusting of BUS voltages and the pi regulator of stabilization;116
Pi regulator for the adjusting for being used for Q axial vector electric currents.
Symbol description is as follows:Vpvref is PV voltage reference values;Vpv is PV voltage sample values;Ipv is PV current samples
Value;Vd1, Vd2 are respectively the voltage sample value of dc bus (BUS) capacitance up and down;Lg, Rg are respectively alternating current to inverter apparatus
Between line equivalent inductance, resistance value, the as this patent impedance to be recognized;Van, Vbn, Vcn are respectively three-phase mains mutually electricity
The sampled value of pressure;Ia, Ib, Ic are respectively the sampled value of three-phase mains line current;Vd, Vq are respectively that phaselocked loop link calculates
DQ vector voltages;Idref, Iqref are respectively the given reference value of DQ vector currents;After Iqcomp is completes impedance identification, school
The reactive current value that power factor needs compensate, when not carrying out PFC, which is zero;Id, Iq are respectively
The DQ current values that Clark, Park transform operation go out;Vbusref controls reference value for BUS voltages;Vbus is BUS voltage samples
Value.
Comparison diagram 1 and Fig. 5 is it is found that DSP+FPGA double-cores scheme controls power grid phaselocked loop, coordinate transform, electric current loop PI
Device, PWM modulation module are removed from DSP, are transferred in FPGA and are realized fast parallel operation.Detailed each functional unit block is drawn
Divide referring to Fig. 5.
Fig. 6 is the DSP+FPGA dual core processor photovoltaic DC-to-AC converter software architectures of this preferred embodiment, referring to Fig. 6, outside DSP
The clock pulses of portion clock pins output 150MHz all the way is connected to the system clock unit of FPGA, and FPGA is introduced by I/O port and carried out
Process of frequency multiplication, as the main system clock of FPGA, main system clock frequency dividing generation 80kHzPWM carrier waves, while the crossover frequency
The as control frequency of power grid phaselocked loop, inverter current ring, Boost electric current loops.And again FPGA is passed through by the crossover frequency IO
Mouth is sent out, and then the ADC samplings of triggering DSP, and ADC samplings complete to trigger 80kHz DMA all the way and pass through EMIF transmission 80kHz AD
Sampled data passes FPGA control algolithms unit back, and (FPGA control algolithms unit completes power grid phaselocked loop, coordinate number, inverter current
Ring control, Boost current loop controls and PWM modulation calculate the operation of each unit).After the completion of transmitting data, another way is triggered
20kHzDMA carries AD sampled datas to DSP locals RAM, and sends and interrupt 20kHzDMA responses, the main interruptions of as DSP, and
Wherein instruction, monitoring data read-write and DSP partitioning algorithms part is completed by 20kHz EMIF (to wrap DSP partitioning algorithms part
Include the control of inverter voltage ring, the control of Boost Voltage loops, the operation of maximum power point tracking).FPGA receives 20kHz EMIF data
After carry out latch processing, and carved at the beginning of FPGA control algolithms with parallel mechanism and carry out data synchronization.In addition, two-way DMA
Priority should be set as DMA1>DMA2.
Fig. 7 is the DSP+FPGA dual core processor photovoltaic DC-to-AC converter software timing figures of this preferred embodiment, referring to Fig. 7, DSP
There are two groups of 80k and 20k, therefore there are two sequential with FPGA data interaction:In 80k sequential, FPGA hair 80k synchronizing signal triggerings
DSP AD are sampled, and 2us moment ADC completes sampling, and DMA1 carries AD sampled datas, and the 3.6us moment completes EMIF AD data biography
Defeated, FPGA carries out its control algolithm.In 20k sequential, complete DMA2 after ADC completes sampling in 80k sequential and carry AD sampled datas
It is interrupted to local RAM, 4.3us time triggers DMA2, sign on data are written at once, are completed after 5.67us, complete after 7.85us
Into reading FPGA data.
Above mentioned 80kHz, 20kHz frequency and 2us, 3.6us sequential moment are only experimental debugging as a result, change number
Word is also among the protection of patent of the present invention.
One of ordinary skill in the art will appreciate that all or part of step in the above method can be instructed by program
Related hardware is completed, and described program can be stored in computer readable storage medium, such as read-only memory, disk or CD
Deng.Optionally, all or part of step of above-described embodiment can also be realized using one or more integrated circuits, accordingly
Ground, the form that hardware may be used in each module/unit in above-described embodiment are realized, can also use the shape of software function module
Formula is realized.The present invention is not limited to the combinations of the hardware and software of any particular form.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, that is made any repaiies
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.