CN108170992A - The method and system of coiling congestion are positioned in a kind of chip design - Google Patents
The method and system of coiling congestion are positioned in a kind of chip design Download PDFInfo
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- CN108170992A CN108170992A CN201810067727.XA CN201810067727A CN108170992A CN 108170992 A CN108170992 A CN 108170992A CN 201810067727 A CN201810067727 A CN 201810067727A CN 108170992 A CN108170992 A CN 108170992A
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- congestion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Abstract
The method and system of coiling congestion are positioned in being designed present invention is disclosed a kind of chip, method includes obtaining gate level netlist, and obtain each bottom submodule in the gate level netlist always around line number and the gross area；The coiling degree of Congestion of each bottom submodule is always obtained, and the bottom submodule that coiling congestion occurs is positioned according to coiling degree of Congestion around line number and the gross area according to each bottom submodule.The present invention can be designed in chip and the quick bottom submodule for finding and coiling congestion occurring in positioning chip of synthesis phase, it is ensured that the physical realizability of chip.
Description
Technical field
The present invention relates to chip design fields, and the method for coiling congestion is positioned in being designed more particularly, to a kind of chip and is
System.
Background technology
Integrated circuit chips design cycle includes Front-end Design stage and back-end physical implementation phase, Front-end Design stage
Including logical design and synthesis etc., back-end physical implementation phase includes wiring etc..Coiling congestion in chip design generally will be
It can expose and find during back-end physical implementation phase.When coiling congestion is that chip makes physical is realized, due in certain area
Line causes line can not be around logical situation too much.If finding coiling congestion in physical implementation stage, need to change front end
The code of design phase solves the problems, such as coiling congestion.The function of chip is easily influenced, and can cause by changing code
Time To Market is postponed in the postponement flow of chip, reduces the competitiveness of chip.
In addition, it is for the common way of the positioning of coiling congestion：A detection zone is defined, then the region is carried out
The analysis of coiling congestion, usual detection zone include multiple submodule, position coiling congestion by such mode, efficiency is low.
Invention content
The defects of it is an object of the invention to overcome the prior art, provides the side that coiling congestion is positioned in a kind of chip design
Method and system can quickly find the bottom submodule with generation coiling congestion in positioning chip.
To achieve the above object, the following technical solutions are proposed by the present invention：The side of coiling congestion is positioned in a kind of chip design
Method includes the following steps：
S1 obtains gate level netlist, and obtain each bottom submodule in the gate level netlist always around line number and the gross area；
S2, according to the coiling congestion that each bottom submodule is always obtained around line number and the gross area of each bottom submodule
Degree, and the bottom submodule that coiling congestion occurs is positioned according to coiling degree of Congestion.
Preferably, in step sl, each bottom submodule includes several logical devices being connected, bottom submodule
Block always obtains as follows around line number：
S101 obtains the input terminal quantity being connected on each logical device with other logical devices and output terminal quantity；
S102 calculates the exclusive session number of each logical device according to equation below,
Zi=(Ni+Mi)/2
Wherein, NiFor the input terminal quantity of i-th of logical device, MiFor the output terminal quantity of i-th of logical device, ZiTable
Show the exclusive session number of i-th of logical device, i is more than 0 natural number；
The exclusive session number of each logical device is added and obtains always around line number by S103.
Preferably, the coiling degree of Congestion includes the first coiling congestion value and the second coiling congestion value, first coiling
Congestion value is always around line number and the ratio of the gross area, the second coiling congestion value is total coiling numerical value, according to the first coiling congestion value
Judge that bottom submodule whether there is the risk of coiling congestion with the size of the second coiling congestion value.
Preferably, in step s 2, when the first coiling congestion value is more than preset first congestion threshold, and the second coiling is gathered around
When plug value is less than preset second congestion threshold, then there is no the risks of coiling congestion for the bottom submodule；
When the first coiling congestion value is less than preset first congestion threshold, and the second coiling congestion value is more than preset the
During two congestion thresholds, then there is no the risks of coiling congestion for the bottom submodule；
When the first coiling congestion value is more than preset second more than preset first congestion threshold and the second coiling congestion value
During congestion threshold, then there are the risks of coiling congestion for the bottom submodule.
Preferably, first congestion threshold is obtained by including the following steps：
S201, by the corresponding first coiling congestion value of all bottom submodules according to being ranked sequentially and removing from big to small
Maximum value and minimum value；
S202 calculates the average value of remaining first coiling congestion value, obtains intermediate value degree of Congestion；
S203 by intermediate value degree of Congestion and empirical value multiplication, obtains the first congestion threshold.
A kind of system that coiling congestion is positioned in chip, including
Netlist processing unit, for obtain gate level netlist and obtain each bottom submodule in the gate level netlist always around
Line number and the gross area；And
Coiling congestion positioning unit is used to always obtain each bottom around line number and the gross area according to each bottom submodule
The coiling degree of Congestion of submodule, and the bottom submodule that coiling congestion occurs is positioned according to coiling degree of Congestion.
Preferably, the netlist processing unit includes
Netlist acquiring unit, the netlist acquiring unit are used to obtain gate level netlist；
It is described to be always used to obtain each bottom submodule in gate level netlist around line number acquiring unit always around line number acquiring unit
Always around line number；And
Gross area acquiring unit, the gross area acquiring unit are used to obtain the total of each bottom submodule in gate level netlist
Area.
Preferably, the coiling congestion positioning unit includes
Coiling degree of Congestion acquiring unit, the coiling degree of Congestion acquiring unit be used for according to each bottom submodule always around
Line number and the gross area obtain the coiling degree of Congestion of each bottom submodule；
Analyzing and positioning unit, the analyzing and positioning unit are used to position the bottom that coiling congestion occurs according to coiling degree of Congestion
Submodule.
Preferably, the coiling degree of Congestion includes the first coiling congestion value and the second coiling congestion value, first coiling
Congestion value for always around line number and the ratio of the gross area, the second coiling congestion value for always around line number, according to the first coiling congestion value and
The size of second coiling congestion value judges that bottom submodule whether there is the risk of coiling congestion.
Preferably, when the first coiling congestion value be more than preset first congestion threshold, and the second coiling congestion value it is small with it is pre-
If the second congestion threshold when, then there is no the risks of coiling congestion for the bottom submodule；When the first coiling congestion value does not surpass
Cross preset first congestion threshold, and when the second coiling congestion value is more than preset second congestion threshold, then the bottom submodule
There is no the risks of coiling congestion；When the first coiling congestion value is more than preset first congestion threshold and the second coiling congestion value
During more than preset second congestion threshold, then there are the risks of coiling congestion for the bottom submodule.
The beneficial effects of the invention are as follows：
Compared with prior art, the method and system of positioning coiling congestion of the present invention, can set in the RTL of chip
The meter stage quickly finds the bottom submodule with generation coiling congestion in positioning chip, it is ensured that chip makes physical realizability, drop
It is low due to code revision risk caused by physical routing congestion and a large amount of verification work and chip retarded flow to be led to
The risk of piece and chip functions mistake improves the design efficiency of chip.
Description of the drawings
Fig. 1 is flow chart of the method for the present invention schematic diagram；
Fig. 2 is the present invention always around the preparation method flow chart schematic diagram of line number；
Fig. 3 is the preparation method flow chart schematic diagram of the first congestion threshold of the present invention；
Fig. 4 is the system structure diagram schematic diagram of the present invention；
Fig. 5 is the gate level netlist structure diagram schematic diagram of the present invention.
Specific embodiment
Below in conjunction with the attached drawing of the present invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
The method and system of coiling congestion are positioned in a kind of disclosed chip design, quickly can find and determine
The bottom submodule of coiling congestion occurs in the chip of position, is particularly suitable for the RTL design stage of chip.
As shown in Figure 1, in a kind of chip design of the present invention coiling congestion localization method, include the following steps：
S1 obtains gate level netlist, and obtain each bottom submodule in gate level netlist always around line number and the gross area；
Specifically, the acquisition of gate level netlist can be obtained by logic synthesis tool Design Complier, by RTL
(Register Transfer Level, Method at Register Transfer Level) grade HDL (Hardware Description Language,
Hardware description language) language description circuit conversion be target process library (Target_library) device form gate leve net
Table.Target process library include with the basic logic units such as door or door, and-or inverter or with the combinatorial logic units such as non-, further include
The sequential logics unit such as latch and trigger.
In the present embodiment, to how to obtain bottom submodule by taking the circuit that top-level module includes three bottom submodules as an example
Be always described in detail around line number and the gross area.
Gate level netlist as shown in Figure 5 obtains after being integrated by logic synthesis tool Design Complier,
Design Complier employ the synthesis of retaining hierarchical in synthesis, therefore, three bottoms are still remained in the gate level netlist
Submodule.
Wherein, each bottom submodule includes 4 logical devices, is denoted as the first logical device, the second logic device respectively
Part, third logical device and the 4th logical device, the line of each logical device are as shown in Figure 5.As shown in Fig. 2, each bottom
Submodule is always included the following steps around line number：
S101 obtains the input terminal quantity being connected on each logical device with other logical devices and output terminal quantity；
As shown in figure 5, two input terminals of the first logical device respectively with the 4th logical device and the second logical device phase
Connection, output terminal are connected with third logical device, and therefore, the input terminal quantity of the first logical device is 2, and output terminal quantity is
1；Two input terminals of third logical device are connected respectively with the first logical device and the second logical device, and output terminal is not with appointing
What logical device is connected, and therefore, the input terminal quantity of third logical device is 2, and output terminal quantity is 0.It can similarly obtain, the 4th
The input terminal quantity of logical device is 1, and output terminal quantity is 1；The input terminal quantity of second logical device is 2, output terminal quantity
It is 1.
S102 calculates the exclusive session number of each logical device according to equation below,
Zi=(Ni+Mi)/2
Wherein, NiFor the input terminal quantity of i-th of logical device, MiFor the output terminal quantity of i-th of logical device, i is big
In 0 natural number.
Specifically, it could be counted when some port of logical device is connect with some port of another logical device
For a line, therefore, 1/2 line is monopolized in each port on two logical devices connected by line.Such as Fig. 5 institutes
Show, two input terminals of the first logical device are connected respectively with the second logical device and the 4th logical device, output terminal and
One logical device is connected, then the input port of the 4th logical device monopolizes 1/2+1/2 root lines, and output terminal monopolizes 1/2 company
Line, therefore, the exclusive session number Z of the 4th logical device1For 1/2+1/2+1/2=(2+1)/2=1.5.
By the exclusive session number Z that can be calculated the second logical device2For (2+1)/2=1.5, third logical device it is only
Account for session number Z3For (2+0)/2=1, the exclusive line Z of the 4th logical device4For (1+1)/2=1.
S103 is calculated according to the exclusive session number of each logical device and is obtained always around line number Z.
Specifically, by the addition of the exclusive session number of each logical device can obtain the bottom submodule always around line number Z,
That is Z=Z1+Z2+…Zi.First bottom submodule as depicted is always Z around line number1+Z2+Z3+Z4=5.
Further, the gross area of each bottom submodule can be obtained by logic synthesis tool Design Complier
.Gate level netlist need to be only input in Design Complier, and input the order of reported area.Shown in Fig. 5
In gate level netlist, the gross area of the first bottom submodule is the area of the first logical device, the area of the second logical device, third
The sum of area of the area of logical device and the 4th logical device.
S2, according to the coiling congestion that each bottom submodule is always obtained around line number and the gross area of each bottom submodule
Degree, and the bottom submodule of coiling congestion is occurred according to the judgement of coiling degree of Congestion.
Specifically, coiling degree of Congestion is used to weigh whether bottom submodule can occur coiling congestion, including the first coiling
Congestion value and the second coiling congestion value, wherein, the first coiling congestion value is always around line number and the ratio of the gross area, and the second coiling is gathered around
Plug value is always around line number, can judge whether bottom submodule occurs coiling congestion by the way that the two is combined.When
One coiling congestion value be more than preset first congestion threshold, and the second coiling congestion value be less than preset second congestion threshold when,
Show risk of the bottom submodule there is no coiling congestion；When the first coiling congestion value is less than preset first congestion threshold
Value, and the second coiling congestion value be more than preset second congestion threshold when, show that equally there is no coilings for the bottom submodule
The risk of congestion.Only when the first coiling congestion value is more than preset first congestion threshold and the second coiling congestion value is more than default
The second congestion threshold when, show the bottom submodule occur coiling congestion risk it is larger, at this point, by analyze the bottom
The code of module, you can finding out leads to the code of coiling congestion.In the present embodiment, preset second congestion threshold is 70000.
Further, as shown in figure 3, in step s 2, the first congestion threshold is obtained by including the following steps：S201,
By the corresponding first coiling congestion value of all bottom submodules according to being ranked sequentially and remove maximum value and minimum from big to small
Value；
S202 calculates the average value of remaining first coiling congestion value, obtains intermediate value degree of Congestion；
S203 by intermediate value degree of Congestion and empirical value multiplication, obtains the first congestion threshold.
In step 201, in order to obtain more accurate intermediate value degree of Congestion, the of multiple maximum values can also be chosen to remove
First coiling congestion value of one coiling congestion value and minimum value.
When bottom submodule the first coiling congestion value be more than the first congestion threshold when, show the bottom submodule exist around
The risk of line congestion, and be more more than the first congestion threshold, then coiling congestion risk is bigger.In the present embodiment, experience value coefficient
It is to be obtained according to previous project Physical Experiment experience, usually takes 1.5.
The further bottom submodule by taking LinkAgg top-level modules as an example to how to judge coiling congestion occur in the present embodiment
Block is described in detail.
Always it is more than 5000 bottom submodule in LinkAgg top-level modules around line number as only listed in following table one.
Table one
First coiling congestion value of each bottom submodule is as shown in upper table, by it according to being ranked sequentially from big to small
After be：2.799th, 2.139,1.132,1.792,1.528,1.526,1.353,1.265,1.151, it can be calculated intermediate value degree of Congestion
It is 1.676, it is 2.5 that the first congestion threshold can be obtained by, which being multiplied with experience value coefficient 1.5,.As seen from the table, LinkAggDreProc bottoms
First coiling congestion value of straton module is more than the first congestion threshold, and always larger around line number numerical value, shows
There are coiling congestion risks for LinkAggDreProc submodules, and LinkAggDreProc is found by practical physical layout wiring
There are coiling congestions for submodule.
After code revision that LinkAggDreProc bottom submodules is corresponding, then pass through Design Complier works
Tool is comprehensive to obtain gate level netlist, and counts always around bottom submodule of the line number more than 5000 in gate level netlist, as shown in following table two：
Table two
It is found that LinkAggDreProc's has always substantially reduced around line number, and always around line number and total face from table two
Long-pending ratio is also far smaller than the first congestion threshold.After re-starting physical layout wiring again, LinkAggDreProc is not deposited
The coiling congestion the problem of.
Also known from table two, LinkAggByteCntSel_LinkAgg_0 submodules always around the ratio of line number/gross area
Value is more than the first congestion threshold, but it is always few around line number, therefore there is no the risks of coiling congestion.
As shown in figure 4, the system of coiling congestion is positioned in a kind of chip design, including netlist processing unit and coiling congestion
Positioning unit, wherein, netlist processing unit is used to obtain gate level netlist, and obtain each bottom submodule in the gate level netlist
Always around line number and the gross area；Coiling congestion positioning unit is used for always being obtained around line number and the gross area according to each bottom submodule
The coiling degree of Congestion of each bottom submodule is obtained, and the bottom submodule that coiling congestion occurs is positioned according to coiling degree of Congestion.
Specifically, netlist processing unit includes netlist acquiring unit, always obtains list around line number acquiring unit and the gross area
Member.Wherein, netlist acquiring unit can be incited somebody to action for obtaining gate level netlist by logic synthesis tool Design Complier
The circuit conversion of RTL level HDL language descriptions is gate level netlist, and Design Complier are in synthesis using the comprehensive of retaining hierarchical
It closes；Always around line number acquiring unit be used to obtaining each bottom submodule in gate level netlist always around line number；Gross area acquiring unit
For obtaining the gross area of each bottom submodule in gate level netlist.
Coiling congestion positioning unit includes coiling degree of Congestion acquiring unit and analyzing and positioning unit.Coiling degree of Congestion obtains single
Member is used for the coiling degree of Congestion that each bottom submodule is always obtained around line number and the gross area according to each bottom submodule；Analysis
Positioning unit is used to position the bottom submodule that coiling congestion occurs according to coiling degree of Congestion.Wherein, coiling degree of Congestion include around
Line degree of Congestion is gathered around for weighing whether bottom submodule can occur coiling congestion including the first coiling congestion value and the second coiling
Plug value, wherein, the first coiling congestion value is always around line number and the ratio of the gross area, the second coiling congestion value is always around line number, leads to
It crosses the two being combined and can judge whether bottom submodule occurs coiling congestion.
The bottom of coiling congestion occurs according to the first coiling congestion value and the positioning of the second coiling congestion value for analyzing and positioning unit
Submodule.Specifically, when the first coiling congestion value is more than preset first congestion threshold, and the second coiling congestion value is less than default
The second congestion threshold when, show risk of the bottom submodule there is no coiling congestion；When the first coiling congestion value does not surpass
It crosses preset first congestion threshold, and when the second coiling congestion value is more than preset second congestion threshold, shows the bottom submodule
Equally there is no the risks of coiling congestion for block.Only when the first coiling congestion value is more than preset first congestion threshold and second
When coiling congestion value is more than preset second congestion threshold, show that the risk of bottom submodule generation coiling congestion is larger, this
When, by the code for analyzing the bottom submodule, you can finding out leads to the code of coiling congestion.
The present invention can quickly have found bottom with generation coiling congestion in positioning chip in the RTL design stage of chip
Module, it is ensured that chip makes physical realizability.
The technology contents and technical characteristic of the present invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of the present invention, therefore, the scope of the present invention in teachings of the present invention and announcement
The revealed content of embodiment should be not limited to, and various replacements and modification without departing substantially from the present invention should be included, and is this patent Shen
Please claim covered.
Claims (10)
1. the method for coiling congestion is positioned in a kind of chip design, which is characterized in that include the following steps：
S1 obtains gate level netlist, and obtain each bottom submodule in the gate level netlist always around line number and the gross area；
S2, according to the coiling degree of Congestion that each bottom submodule is always obtained around line number and the gross area of each bottom submodule, and
The bottom submodule that coiling congestion occurs is positioned according to coiling degree of Congestion.
2. according to the method described in claim 1, it is characterized in that, in step sl, each bottom submodule includes several
A logical device being connected, bottom submodule always obtain as follows around line number：
S101 obtains the input terminal quantity being connected on each logical device with other logical devices and output terminal quantity；
S102 calculates the exclusive session number of each logical device according to equation below,
Zi=(Ni+Mi)/2
Wherein, NiFor the input terminal quantity of i-th of logical device, MiFor the output terminal quantity of i-th of logical device, ZiRepresent i-th
The exclusive session number of a logical device, i are more than 0 natural number；
The exclusive session number of each logical device is added and obtains always around line number by S103.
3. according to the method described in claim 1, it is characterized in that, the coiling degree of Congestion includes the first coiling congestion value and the
Two coiling congestion values, the first coiling congestion value are always around line number and the ratio of the gross area, and the second coiling congestion value is
Always around line number, judge that bottom submodule is gathered around with the presence or absence of coiling according to the size of the first coiling congestion value and the second coiling congestion value
The risk of plug.
4. according to the method described in claim 3, it is characterized in that, when the first coiling congestion value is more than preset first congestion threshold
Value, and the second coiling congestion value be less than preset second congestion threshold when, then there is no coiling congestions for the bottom submodule
Risk；
When the first coiling congestion value is less than preset first congestion threshold, and the second coiling congestion value is gathered around more than preset second
When filling in threshold value, then there is no the risks of coiling congestion for the bottom submodule；
When the first coiling congestion value is more than preset second congestion more than preset first congestion threshold and the second coiling congestion value
During threshold value, then there are the risks of coiling congestion for the bottom submodule.
5. according to the method described in claim 3, it is characterized in that, first congestion threshold is obtained by including the following steps
：
S201, by the corresponding first coiling congestion value of all bottom submodules according to being ranked sequentially and remove maximum from big to small
Value and minimum value；
S202 calculates the average value of remaining first coiling congestion value, obtains intermediate value degree of Congestion；
S203 by intermediate value degree of Congestion and empirical value multiplication, obtains the first congestion threshold.
6. the system of coiling congestion is positioned in a kind of chip, which is characterized in that including
Netlist processing unit, for obtain gate level netlist and obtain each bottom submodule in the gate level netlist always around line number
And the gross area；And
Coiling congestion positioning unit, for always obtaining each bottom submodule around line number and the gross area according to each bottom submodule
The coiling degree of Congestion of block, and the bottom submodule that coiling congestion occurs is positioned according to coiling degree of Congestion.
7. system according to claim 6, which is characterized in that netlist processing unit includes
Netlist acquiring unit, the netlist acquiring unit are used to obtain gate level netlist；
It is described to be always used to obtain the total of each bottom submodule in gate level netlist around line number acquiring unit always around line number acquiring unit
Around line number；And
Gross area acquiring unit, the gross area acquiring unit are used to obtain total face of each bottom submodule in gate level netlist
Product.
8. system according to claim 6, which is characterized in that the coiling congestion positioning unit includes
Coiling degree of Congestion acquiring unit, the coiling degree of Congestion acquiring unit are used for according to each bottom submodule always around line number
The coiling degree of Congestion of each bottom submodule is obtained with the gross area；
Analyzing and positioning unit, the analyzing and positioning unit are used to position the bottom submodule that coiling congestion occurs according to coiling degree of Congestion
Block.
9. system according to claim 6, which is characterized in that the coiling degree of Congestion includes the first coiling congestion value and the
Two coiling congestion values, the first coiling congestion value are always around line number and the ratio of the gross area, and the second coiling congestion value is
Always around line number, judge that bottom submodule is gathered around with the presence or absence of coiling according to the size of the first coiling congestion value and the second coiling congestion value
The risk of plug.
10. system according to claim 9, which is characterized in that when the first coiling congestion value is more than preset first congestion
Threshold value, and the second coiling congestion value it is small with preset second congestion threshold when, then there is no coiling congestions for the bottom submodule
Risk；When the first coiling congestion value is less than preset first congestion threshold, and the second coiling congestion value is more than preset the
During two congestion thresholds, then there is no the risks of coiling congestion for the bottom submodule；When the first coiling congestion value is more than preset
When first congestion threshold and the second coiling congestion value are more than preset second congestion threshold, then there are coilings to gather around for the bottom submodule
The risk of plug.
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