CN108170634B - A kind of isomerous multi-source data reconstruction transient state reliable treatments method - Google Patents
A kind of isomerous multi-source data reconstruction transient state reliable treatments method Download PDFInfo
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- CN108170634B CN108170634B CN201711427893.8A CN201711427893A CN108170634B CN 108170634 B CN108170634 B CN 108170634B CN 201711427893 A CN201711427893 A CN 201711427893A CN 108170634 B CN108170634 B CN 108170634B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
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Abstract
The invention discloses a kind of isomerous multi-source data reconstruction transient state reliable treatments methods, comprising: the judgement of FPGA dynamic zone state；FPGA establishes static zones BRAM and realizes to the caching for reconstructing instantaneous data；After the completion of reconstruct, FPGA dynamic area sends inquiry frame to static zones, inquires in frame to include the dynamic area in the coordinate in fpga chip internal physical region and the functional identity of the reconfiguration code run on the dynamic area；The static zones FPGA parse the inquiry frame that dynamic area is sent, and return to acknowledgement frame, include reconstruct moment being buffered in the data in BRAM in acknowledgement frame.The problem of data interaction that method disclosed by the invention is able to solve when the dynamic area as caused by breaking down FPGA dynamic area or function switch reconstructs between the dynamic area occurred and static zones is interrupted, improves the reliability of isomerous multi-source data processing.
Description
Technical field
The invention belongs to electronic engineering and computer science, and in particular to a kind of isomerous multi-source data reconstruction transient state can
By processing method.
Background technique
With the proposition of national strategy " made in China 2025 ", intelligence manufacture has become the hot spot noun of contemporary China.But
It is to realize that intelligence manufacture be unable to do without data, these data more specifically show as the data at manufacture scene, so manufacturing live number
According to reliable acquisition, processing, exchange with transmission be exactly to realize that the Floor layer Technology of intelligence manufacture supports.The data at scene are manufactured in number
According to isomery is shown as in agreement, multi-source is shown as in data volume, how while efficient process isomerous multi-source data, is guaranteed
The reliability of data processing just seems most important.Since FPGA has born hardware concurrent and dynamic restructuring characteristic,
The acquisition of data, such as voltage, the electricity of acquisition lathe are completed in one static zones of FPGA internal build and multiple dynamic areas, static zones
Stream, revolving speed, acquire realtime image data and environmental parameter of production line etc.；Each dynamic area runs different Processing Algorithms,
Such as 1 working voltage of dynamic area filtering processing algorithm, 2 operation image gray proces algorithm of dynamic area, 3 running environment of dynamic area ginseng
Several Preprocessing Algorithms etc., can be achieved with the efficient process of isomerous multi-source data in this way.
But there is certain radiation and ionization at manufacture scene, the micro-chip processor including FPGA is all very possible
There are the failures such as hardware damage and code " run and fly ", but the reliability of data processing can be improved by dynamic restructuring by FPGA,
It is embodied in when " run and fly " occurs in the code run on some dynamic area, the static zones FPGA are stored in by state machine reading
Dynamic code in the outer flash of piece, and being re-loaded in the dynamic area of failure, to realize the failure of dynamic area from extensive
It is multiple；Or the static zones FPGA are read not another dynamic code and are loaded into the dynamic area, to realize that the function of dynamic area is cut
It changes.But during dynamic area reconstruct, the data interaction between static zones and dynamic area is to interrupt, even if FPGA dynamic
Reconstruct time generally in Millisecond, but for the data processing occasion harsher to requirement of real-time, reconstruct causes
Data processing interrupt and also directly affect the reliability of data processing.Therefore, the present invention proposes a kind of isomerous multi-source data reconstruction
Transient state reliable treatments method, data interaction when this method is able to solve FPGA dynamic restructuring between static zones and dynamic area occur
The problem of interruption, can be realized the reliable treatments of isomerous multi-source data.
Summary of the invention
The technical problem to be solved in the present invention are as follows: a kind of isomerous multi-source data reconstruction transient state reliable treatments method is provided, it should
The problem of data interaction when method is able to solve FPGA dynamic restructuring between static zones and dynamic area is interrupted, can be realized
The reliable treatments of isomerous multi-source data.
The present invention solves its technical problem and adopts the following technical solutions to achieve: a kind of isomerous multi-source data reconstruction transient state
Reliable treatments method, comprising the following steps:
Step 1: the judgement of FPGA dynamic zone state is implemented as follows:
1. establishing a width is 1, the dual-port BRAM that depth is 1, under the driving of FPGA master clock, static zones pass through
The numerical value that port A sets the BRAM is high level, and after 10 master clock cycles, judgement is read by port A in static zones
The level state of the numerical value of the BRAM: when for high level, show that dynamic area is in restructuring procedure: when for low level, table
Bright dynamic area is in non-restructuring procedure；
2. dynamic area is read in real time and is judged the level of the numerical value of the BRAM by port B under the driving of FPGA master clock
The level state of the numerical value of the BRAM is reset to low level in next clock cycle when for high level by state；
3. needing to establish k width in static zones is 1, and the dual-port BRAM that depth is 1 is each when there is k dynamic area
The judgement of dynamic zone state is as 1. and 2.；
Step 2: FPGA establishes static zones data buffer storage BRAM and realizes that specific implementation is such as to the caching for reconstructing transient data
Under:
1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones
By data buffer storage to be processed in this BRAM；
2. the static zones FPGA are according to each dynamic area in the coordinate in fpga chip internal physical region and on the dynamic area
The difference of the functional identity of the reconfiguration code of operation, respectively by data buffer storage in the different offset address of the BRAM；
Step 3: after the completion of reconstruct, FPGA dynamic area sends inquiry frame to static zones, and frame format is implemented as follows:
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2-11 is data field, wherein byte 2-3 indicates the dynamic area on the left side in fpga chip internal physical region
The abscissa on upper vertex；Byte 4-5 indicates the dynamic area in the ordinate of the left upper apex in fpga chip internal physical region；Word
Section 6-7 indicates the dynamic area in the abscissa of the bottom right vertex in fpga chip internal physical region；Byte 8-9 indicates the dynamic area
In the ordinate of the bottom right vertex in fpga chip internal physical region；Byte 10-11 indicates the reconstruct run on the dynamic area
The functional identity of code；
3. byte 12 is data field end identifier, i.e. hexadecimal 00；
4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte 14-15 is the length of data field, wherein byte 14 is high byte；
6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；
When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape before 5A, the FE
Character hexadecimal 00；The length of data field does not include the escape character of insertion；
Step 4: the static zones FPGA parse the inquiry frame that dynamic area is sent, and need to turn insertion when frame is inquired in parsing
Adopted character removal, obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconstruct generation run on the dynamic area
The functional identity of code, then corresponding data in data buffer storage BRAM are read in static zones；
Step 5: the static zones FPGA return to acknowledgement frame to dynamic area, and frame format is implemented as follows:
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2- (n+1) is data field, that is, the data being buffered in BRAM when reconstructing, wherein n is data byte length；
3. byte n+2 is data field end identifier, i.e. hexadecimal 00；
4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；；
6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；
When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape before 5A, the FE
Character hexadecimal 00；The length of data field does not include the escape character of insertion.
A kind of isomerous multi-source data reconstruction transient state reliable treatments method that the present invention designs is suitable for Xilinx company
Virtex-5FPGA chip.
The advantages of the present invention over the prior art are that:
(1) traditional method that FPGA dynamic restructuring reliability is improved using triplication redundancy etc., not only increases FPGA
The consumption of resource, and improve merely by the mode of prepare more part the reliability of dynamic area, it is basic without solving reconstruct when
Transient problem.What interrupting occurred in the data interaction when present invention is able to solve FPGA dynamic restructuring between static zones and dynamic area
Problem can be realized the reliable treatments of isomerous multi-source data.
(2) FPGA dynamic zone state proposed by the present invention judges, establishes BRAM to cache the data and static state when reconstruct
Inquiry frame, acknowledgement frame between area and dynamic area can fundamentally solve FPGA reconstruct transient problem.
Detailed description of the invention
Fig. 1 is flow chart of the invention.
Specific embodiment
Further detailed description is done to the present invention with reference to the accompanying drawing.
The present invention relates to a kind of isomerous multi-source data reconstruction transient state reliable treatments methods, using Xilinx company
Virtex-5FPGA chip.This method is asked for the reconstruct transient state of the isomerous multi-source Data processing based on FPGA dynamic restructuring
It inscribes, in the data interaction appearance when reconstruct transient problem of so-called FPGA is exactly FPGA dynamic restructuring between static zones and dynamic area
It is disconnected.The present invention proposes that method is able to solve FPGA reconstruct transient problem, realizes the reliable treatments of isomerous multi-source data.
Flow chart of the invention is as shown in Figure 1, specific embodiment is as follows:
(1) FPGA dynamic zone state judges, is implemented as follows:
1. establishing a width is 1, the dual-port BRAM that depth is 1, under the driving of FPGA master clock, static zones pass through
The numerical value that port A sets the BRAM is high level, and after 10 master clock cycles, judgement is read by port A in static zones
The level state of the numerical value of the BRAM: when for high level, show that dynamic area is in restructuring procedure: when for low level, table
Bright dynamic area is in non-restructuring procedure；
2. dynamic area is read in real time and is judged the level of the numerical value of the BRAM by port B under the driving of FPGA master clock
The level state of the numerical value of the BRAM is reset to low level in next clock cycle when for high level by state；
3. needing to establish k width in static zones is 1, and the dual-port BRAM that depth is 1 is each when there is k dynamic area
The judgement of dynamic zone state is as 1. and 2.；
(2) static zones FPGA are established data buffer storage BRAM and are realized to the caching of reconstruct transient data, are implemented as follows:
1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones
By data buffer storage to be processed in this BRAM；
2. the static zones FPGA are according to each dynamic area in the coordinate in fpga chip internal physical region and on the dynamic area
The difference of the functional identity of the reconfiguration code of operation, respectively by data buffer storage in the different offset address of the BRAM；
(3) after the completion of reconstruct, FPGA dynamic area sends inquiry frame to static zones, and frame format is implemented as follows:
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2-11 is data field, wherein byte 2-3 indicates the dynamic area on the left side in fpga chip internal physical region
The abscissa on upper vertex；Byte 4-5 indicates the dynamic area in the ordinate of the left upper apex in fpga chip internal physical region；Word
Section 6-7 indicates the dynamic area in the abscissa of the bottom right vertex in fpga chip internal physical region；Byte 8-9 indicates the dynamic area
In the ordinate of the bottom right vertex in fpga chip internal physical region；Byte 10-11 indicates the reconstruct run on the dynamic area
The functional identity of code；
3. byte 12 is data field end identifier, i.e. hexadecimal 00；
4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte 14-15 is the length of data field, wherein byte 14 is high byte；
6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；
When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape before 5A, the FE
Character hexadecimal 00；The length of data field does not include the escape character of insertion；
(4) the inquiry frame that parsing dynamic area in the static zones FPGA is sent, needs when frame is inquired in parsing by the escape word of insertion
Symbol removal obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconfiguration code run on the dynamic area
Functional identity, then corresponding data in data buffer storage BRAM are read in static zones；
(5) static zones FPGA return to acknowledgement frame to dynamic area, and frame format is implemented as follows:
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2- (n+1) is data field, that is, the data being buffered in BRAM when reconstructing, wherein n is data byte length；
3. byte n+2 is data field end identifier, i.e. hexadecimal 00；
4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；；
6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；
When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape before 5A, the FE
Character hexadecimal 00；The length of data field does not include the escape character of insertion.
In conclusion the invention discloses a kind of isomerous multi-source data reconstruction transient state reliable treatments methods, comprising: FPGA is dynamic
The judgement of state zone state；FPGA establishes static zones BRAM and realizes to the caching for reconstructing instantaneous data；FPGA dynamic area is sent out to static zones
The acknowledgement frame that the inquiry frame sent and the static zones FPGA are returned to dynamic area.This method is able to solve based on FPGA dynamic restructuring
The reconstruct transient problem of isomerous multi-source Data processing realizes the reliable treatments of isomerous multi-source data.
The content that description in the present invention is not described in detail belongs to the prior art well known to professional and technical personnel in the field.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (2)
1. a kind of isomerous multi-source data reconstruction transient state reliable treatments method, it is characterised in that: the following steps are included:
Step 1: the judgement of FPGA dynamic zone state is implemented as follows:
1. establishing a width is 1, the dual-port BRAM that depth is 1, under the driving of FPGA master clock, static zones pass through port
The numerical value that A sets the BRAM is high level, and after 10 master clock cycles, static zones are read by port A and judge this
The level state of the numerical value of BRAM: when for high level, show that dynamic area is in restructuring procedure: when for low level, showing
Dynamic area is in non-restructuring procedure；
2. dynamic area is read in real time and is judged the level shape of the numerical value of the BRAM by port B under the driving of FPGA master clock
The level state of the numerical value of the BRAM is reset to low level in next clock cycle when for high level by state；
3. needing to establish k width in static zones is 1, the dual-port BRAM that depth is 1, each dynamic when there is k dynamic area
The judgement of zone state is as 1. and 2.；
Step 2: FPGA establishes static zones data buffer storage BRAM and realizes to the caching of reconstruct transient data, is implemented as follows:
1. FPGA establishes static zones a BRAM, when static zones monitor that dynamic area is in restructuring procedure, static zones will be to
The data buffer storage of processing is in this BRAM；
2. the static zones FPGA are run in the coordinate in fpga chip internal physical region and on the dynamic area according to each dynamic area
Reconfiguration code functional identity difference, respectively by data buffer storage in the different offset address of the BRAM；
Step 3: after the completion of reconstruct, FPGA dynamic area sends inquiry frame to static zones, and frame format is implemented as follows:
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2-11 is data field, wherein byte 2-3 indicates that the dynamic area is pushed up in the upper left in fpga chip internal physical region
The abscissa of point；Byte 4-5 indicates the dynamic area in the ordinate of the left upper apex in fpga chip internal physical region；Byte 6-
7 indicate the dynamic area in the abscissa of the bottom right vertex in fpga chip internal physical region；Byte 8-9 indicates that the dynamic area exists
The ordinate of the bottom right vertex in fpga chip internal physical region；Byte 10-11 indicates the reconstruct generation run on the dynamic area
The functional identity of code；
3. byte 12 is data field end identifier, i.e. hexadecimal 00；
4. byte 13 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte 14-15 is the length of data field, wherein byte 14 is high byte；
6. byte 16-17 is postamble, i.e. hexadecimal 5A, FE；
When inquiring that postamble, i.e. hexadecimal 5A, FE occurs in the data field in frame, need to be inserted into escape character before 5A, the FE
Hexadecimal 00；The length of data field does not include the escape character of insertion；
Step 4: the static zones FPGA parse the inquiry frame that dynamic area is sent, and need when frame is inquired in parsing by the escape word of insertion
Symbol removal obtains the dynamic area in the coordinate in fpga chip internal physical region and the reconfiguration code run on the dynamic area
Functional identity, then corresponding data in data buffer storage BRAM are read in static zones；
Step 5: the static zones FPGA return to acknowledgement frame to dynamic area, and frame format is implemented as follows:
1. byte 0-1 is frame head, i.e. hexadecimal 5A, 54；
2. byte 2- (n+1) is data field, that is, the data being buffered in BRAM when reconstructing, wherein n is data byte length；
3. byte n+2 is data field end identifier, i.e. hexadecimal 00；
4. byte n+3 is verification, i.e., the logic sum of each byte takes low byte in data field；
5. byte n+4, n+5 is the length of data field, wherein byte n+4 is high byte；
6. byte n+6, n+7 is postamble, i.e. hexadecimal 5A, FE；
When postamble, i.e. hexadecimal 5A, FE occurs in the data field in acknowledgement frame, need to be inserted into escape character before 5A, the FE
Hexadecimal 00；The length of data field does not include the escape character of insertion.
2. a kind of isomerous multi-source data reconstruction transient state reliable treatments method as described in claim 1, it is characterised in that: described
Method is suitable for Xilinx company Virtex-5FPGA chip.
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| CN110045691B (en) * | 2019-03-13 | 2021-03-16 | 东北大学 | Multi-task processing fault monitoring method for multi-source heterogeneous big data |
| CN112214448B (en) * | 2020-10-10 | 2024-04-09 | 声龙(新加坡)私人有限公司 | Data dynamic reconstruction circuit and method of heterogeneous integrated workload proving operation chip |
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| US7539967B1 (en) * | 2006-05-05 | 2009-05-26 | Altera Corporation | Self-configuring components on a device |
| US8710864B2 (en) * | 2010-04-23 | 2014-04-29 | Utah State University | Dynamically reconfigurable systolic array accelorators |
| CN104008024A (en) * | 2014-06-12 | 2014-08-27 | 北京航空航天大学 | Dynamic reconstruction technology application platform based on FPGA |
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