CN108153644A - A kind of data processing method and electronic equipment - Google Patents
A kind of data processing method and electronic equipment Download PDFInfo
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- CN108153644A CN108153644A CN201711404769.XA CN201711404769A CN108153644A CN 108153644 A CN108153644 A CN 108153644A CN 201711404769 A CN201711404769 A CN 201711404769A CN 108153644 A CN108153644 A CN 108153644A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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Abstract
The invention discloses a kind of data processing method and electronic equipments, the hardware monitoring signal of the processor of electronic equipment is obtained by the built-in FPGA of central processing unit, processor includes central processing unit, hardware fault signal is determined according to hardware monitoring signal, hardware fault signal is sent to hardware control, hardware control is made to analyze and process hardware fault signal.Hardware fault signal is directly sent to hardware control by this programme by the built-in FPGA of central processing unit, so that hardware control only analyzes and processes hardware fault signal, without being analyzed and processed to whole hardware monitoring information in processor, reduce the data processing amount of hardware control, the data volume for being transmitted to hardware control is reduced simultaneously, avoids the occupancy of Internet resources.
Description
Technical field
The present invention relates to control field more particularly to a kind of data processing method and electronic equipments.
Background technology
At present, it to realize the fault diagnosis to the hardware device in CPU and south bridge, need to supervise on the hardware of CPU and south bridge
Control signal is sent to external hardware control, judges whether have hardware to set in CPU according to the hardware signal by hardware control
It is standby to break down, and failure judgement type.
However, using aforesaid way, it is necessary to which CPU and south bridge send whole hardware monitorings to hardware control and believe
Number, data volume is larger, occupies Internet resources.
Invention content
In view of this, the present invention provides a kind of data processing method and electronic equipment, to solve CPU and south in the prior art
The problem of bridge needs to send whole hardware monitoring information to hardware control, and data volume is larger, occupancy Internet resources, it is specific
Scheme is as follows：
A kind of data processing method, applied to electronic equipment, including：
The built-in on-site programmable gate array FPGA of central processing unit obtains the hardware of the processor in the electronic equipment
Monitoring signal, the processor include：The central processing unit；
The built-in FPGA of the central processing unit determines hardware fault signal according to the hardware monitoring signal；
The hardware fault signal is sent to hardware control by the built-in FPGA of the central processing unit, makes the hardware
Controller analyzes and processes the hardware fault signal.
Further, the built-in FPGA of the central processing unit determines that hardware fault is believed according to the hardware monitoring signal
Number, including：
The built-in FPGA of the central processing unit by the hardware monitoring signal and preset hardware fault signal list into
Row compares, and determines the signal for whether having with the Signal Matching in the hardware fault signal list in the hardware monitoring signal.
Further, the built-in FPGA of the central processing unit obtains the hardware monitoring letter of the processor of the electronic equipment
Number, including：
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the central processing unit of the electronic equipment；
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the south bridge of the electronic equipment.
Further, the hardware fault signal is sent to hardware control by the built-in FPGA of the central processing unit,
Including：
The built-in FPGA of the central processing unit is by the hardware fault signal of the central processing unit and/or the south bridge
Hardware fault signal is sent to hardware control by the bus interface of the central processing unit.
A kind of data processing method, applied to electronic equipment, including：
The hardware fault signal of the processor of the electronic equipment sent by the built-in FPGA of central processing unit is received,
The hardware fault signal is to be analyzed according to the hardware monitoring signal of the processor of the electronic equipment, the place
Reason device includes：The central processing unit；
The hardware fault type of the processor is determined according to the hardware fault signal.
Further, it is described to receive through the built-in FPGA of the central processing unit processors of the electronic equipment sent
Hardware fault signal, including：
Receive the hardware monitoring signal of central processing unit sent by the built-in FPGA of central processing unit；
Receive the hardware monitoring signal of south bridge sent by the built-in FPGA of central processing unit.
Further, it is described to receive through the built-in FPGA of the central processing unit processors of the electronic equipment sent
Hardware fault signal, including：
Receive the electricity sent by the built-in FPGA of central processing unit by the bus interface of the central processing unit
The hardware fault signal of the processor of sub- equipment.
A kind of electronic equipment, including：Processor, on-site programmable gate array FPGA and hardware control, wherein：
The processor includes：Central processing unit, the central processing unit are built-in with FPGA；
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the processor, according to the hardware monitoring
Signal determines hardware fault signal, and the hardware fault signal is sent to the hardware control；
The hardware control analyzes and processes the hardware fault signal.
Further, the built-in FPGA of the central processing unit obtains the hardware monitoring signal of the processor, including：
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the central processing unit of the electronic equipment；
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the south bridge of the electronic equipment.
Further, the hardware fault signal is sent to hardware control by the built-in FPGA of the central processing unit,
Including：
The built-in FPGA of the central processing unit is by the hardware fault signal of the central processing unit and/or the south bridge
Hardware fault signal is sent to hardware control by the bus interface of the central processing unit.
It can be seen from the above technical proposal that data processing method disclosed in the present application and electronic equipment, pass through centre
The hardware monitoring signal of the processor of the built-in FPGA acquisition electronic equipments of device is managed, processor includes central processing unit, according to hard
Part monitoring signal determines hardware fault signal, and hardware fault signal is sent to hardware control, makes hardware control to hardware
Fault-signal is analyzed and processed.Hardware fault signal is directly sent to firmly by this programme by the built-in FPGA of central processing unit
Part controller so that hardware control only analyzes and processes hardware fault signal, without to whole hardware in processor
Monitoring information is analyzed and processed, and reduces the data processing amount of hardware control, while is reduced and be transmitted to hardware control
Data volume, avoid the occupancy of Internet resources.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of flow chart of data processing method disclosed by the embodiments of the present invention；
Fig. 2 is a kind of flow chart of data processing method disclosed by the embodiments of the present invention；
Fig. 3 is the structure diagram of a kind of electronic equipment disclosed by the embodiments of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
The invention discloses a kind of data processing method, applied to electronic equipment, flow chart as shown in Figure 1, including：
Step S11, the built-in field programmable gate array FPGA of central processing unit obtains the processing in electronic equipment
The hardware monitoring signal of device, processor include：Central processing unit；
A field programmable gate array FPGA is integrated in the central processor CPU of electronic equipment, to the FPGA
It is programmed, the FPGA is made to have the function of to carry out fault diagnosis to hardware monitoring signal, so that by the FPGA inside CPU
The monitoring signal to break down in directly determining processor, and the monitoring signal of failure is only sent to hardware control,
Without whole monitoring signals is sent to hardware control.
Processor includes central processor CPU, can also be connected including south bridge PCH, PCH by DMI buses with CPU.
FPGA obtains the hardware monitoring signal of the processor in electronic equipment, not only includes：FPGA is obtained in electronic equipment
The hardware monitoring signal of CPU, further includes：FPGA obtains the hardware monitoring signal of PCH in electronic equipment, the hardware monitoring letter of PCH
The FPGA number being sent to by DMI buses in CPU.
Each hardware device on CPU and PCH is monitored, and monitoring signal is sent to FPGA in real time, by FPGA into
Row fault diagnosis.Specifically, can be that hardware monitoring signal is sent to FPGA in real time, or interval preset duration will be hard
Part monitoring signal is sent to FPGA.
Specifically, being monitored to each hardware device on CPU and PCH, can be specially：Only each hardware device is carried out
Monitoring, and monitoring information is directly sent to FPGA；Or：When being monitored to each hardware device, if each is hard
Part device corresponds to a monitoring device, while each monitoring device monitors, whether is additionally operable to the signal for judging to monitor
Normally, if so, not sending hardware monitoring signal, if judging the abnormal signal monitored, hardware monitoring signal is sent, it
Afterwards, the hardware monitoring signal is directly sent to hardware control by FPGA.
Step S12, the built-in FPGA of central processing unit determines hardware fault signal according to hardware monitoring signal；
FPGA obtains the hardware monitoring signal of CPU and PCH, and the hardware monitoring signal of CPU and PCH is diagnosed, and determines
Whether there is hardware fault signal in all hardware monitoring signal received.
Specifically, can be：Hardware fault information list is previously stored in FPGA.
Include the hardware that each hardware device is likely to occur respectively in CPU and PCH in the hardware fault information list
A certain hardware device in fault-signal, i.e. CPU or PCH, such as：First hardware, the failure being likely to occur have it is several, when point
Not Chu Xian these types of failure when, the corresponding monitoring fault-signal of hardware monitoring signal that monitoring device detects, alternatively, the
When there are two or more failures simultaneously in one hardware, the corresponding monitoring of hardware monitoring signal that monitoring device detects is former
Hinder signal.
Wherein, the fault type being likely to occur in FPGA without storage hardware device, it is only necessary to store each hardware device
Part is for the monitoring fault-signal corresponding to different failures.
Furthermore it is also possible to it is：Hardware monitoring signal list is previously stored in FPGA.
Include in the hardware monitoring signal list in CPU i.e. PCH each hardware device it is normal, do not break down when
Hardware monitoring signal standard signal, i.e., for different hardware devices have respectively corresponding hardware monitoring signal standard believe
Number, which can be a standard signal range.
The standard signal of hardware monitoring signal is each hardware device in normal work, and monitoring device detects hard
The value of part monitoring signal, when a certain hardware device breaks down, no matter it occurs that several failures or which kind of event
Barrier, the hardware monitoring signal that monitoring device detects necessarily are different from the hardware monitoring letter detected when the hardware device is normal
Number, when the hardware monitoring signal is different from its corresponding standard signal, show the corresponding hardware device of hardware monitoring signal
It breaks down, which is hardware fault signal.
Wherein, the fault type being likely to occur in FPGA without storage hardware device, it is only necessary to store each hardware device
The standard signal of the hardware monitoring signal of part.
Step S13, hardware fault signal is sent to hardware control by the built-in FPGA of central processing unit, makes hardware controls
Device analyzes and processes hardware fault signal.
When FPGA determines to have hardware fault signal in received hardware monitoring signal, which is sent out
It send to hardware control, the hardware fault signal is analyzed and processed by hardware control.
When there is hardware fault signal in the hardware monitoring signal that FPGA determines received CPU and PCH, no matter this is hard
Part fault-signal is one or multiple, which is hard on hardware fault signal or PCH on CPU
One or more hardware fault signals separately or concurrently can be sent to hardware control by part fault-signal, without by its
He is not that the hardware monitoring signal of hardware fault signal is sent to hardware control.
Not only include the hardware monitoring of the hardware device of the failure that monitoring device detects in hardware fault signal
Signal further includes the mark of the corresponding hardware device of hardware monitoring signal, which can be hardware device title, can also
For number or other, as long as the mark can uniquely show the hardware device.
Each fault type that each hardware device being stored in hardware control on CPU and PCH is likely to occur
Corresponding hardware fault signal can also be stored with the troubleshooting scheme corresponding to each fault type.
When the hardware fault signal for receiving some hardware device, it is first determined the corresponding tool of hardware fault signal
The hardware device of body, searching the hardware fault signal corresponding to each fault type that the hardware device is likely to occur later is
It is no to have the signal consistent with the hardware fault signal detected, if so, then the fault type is that the hardware device is corresponding
Fault type.
After the fault type for determining specific some hardware device appearance, the corresponding troubleshooting side of the fault type is determined
Case is handled the failure according to the troubleshooting scheme.
Further, FPGA will monitor fault-signal when being sent to hardware control, can pass through I2C interface sends monitoring
Fault-signal.
Wherein, hardware control can be：BMC, or：Super IO.
Data processing method disclosed in the present embodiment obtains the processing of electronic equipment by the built-in FPGA of central processing unit
The hardware monitoring signal of device, processor include central processing unit, hardware fault signal are determined according to hardware monitoring signal, by hardware
Fault-signal is sent to hardware control, and hardware control is made to analyze and process hardware fault signal.This programme is in
Hardware fault signal is directly sent to hardware control by the built-in FPGA of central processor so that hardware control is only to hardware event
Barrier signal is analyzed and processed, and without being analyzed and processed to whole hardware monitoring information in processor, reduces hardware control
The data processing amount of device processed, while the data volume for being transmitted to hardware control is reduced, avoid the occupancy of Internet resources.
Present embodiment discloses a kind of data processing method, applied to electronic equipment, flow chart as shown in Fig. 2, including：
Step S21, the hardware fault signal of processor sent by the built-in FPGA of central processing unit, hardware event are received
It is what is analyzed according to the hardware monitoring signal of processor to hinder signal, and processor includes：Central processing unit；
A field programmable gate array FPGA is integrated in the central processor CPU of electronic equipment, to the FPGA
It is programmed, the FPGA is made to have the function of to carry out fault diagnosis to hardware monitoring signal, so that by the FPGA inside CPU
The monitoring signal to break down in directly determining processor, and the monitoring signal of failure is only sent to hardware control,
Without whole monitoring signals is sent to hardware control.
Processor includes central processor CPU, can also be connected including south bridge PCH, PCH by DMI buses with CPU.
FPGA obtains the hardware monitoring signal of the processor in electronic equipment, not only includes：FPGA is obtained in electronic equipment
The hardware monitoring signal of CPU, further includes：FPGA obtains the hardware monitoring signal of PCH in electronic equipment, the hardware monitoring letter of PCH
The FPGA number being sent to by DMI buses in CPU.
Each hardware device on CPU and PCH is monitored, and monitoring signal is sent to FPGA in real time, by FPGA into
Row fault diagnosis.Specifically, can be that hardware monitoring signal is sent to FPGA in real time, or interval preset duration will be hard
Part monitoring signal is sent to FPGA.
Specifically, being monitored to each hardware device on CPU and PCH, can be specially：Only each hardware device is carried out
Monitoring, and monitoring information is directly sent to FPGA；Or：When being monitored to each hardware device, if each is hard
Part device corresponds to a monitoring device, while each monitoring device monitors, whether is additionally operable to the signal for judging to monitor
Normally, if so, not sending hardware monitoring signal, if judging the abnormal signal monitored, hardware monitoring signal is sent, it
Afterwards, the hardware monitoring signal is directly sent to hardware control by FPGA.
FPGA obtains the hardware monitoring signal of CPU and PCH, and the hardware monitoring signal of CPU and PCH is diagnosed, and determines
Whether there is hardware fault signal in all hardware monitoring signal received.
Specifically, can be：Hardware fault information list is previously stored in FPGA.
Include the hardware that each hardware device is likely to occur respectively in CPU and PCH in the hardware fault information list
A certain hardware device in fault-signal, i.e. CPU or PCH, such as：First hardware, the failure being likely to occur have it is several, when point
Not Chu Xian these types of failure when, the corresponding monitoring fault-signal of hardware monitoring signal that monitoring device detects, alternatively, the
When there are two or more failures simultaneously in one hardware, the corresponding monitoring of hardware monitoring signal that monitoring device detects is former
Hinder signal.
Wherein, the fault type being likely to occur in FPGA without storage hardware device, it is only necessary to store each hardware device
Part is for the monitoring fault-signal corresponding to different failures.
Furthermore it is also possible to it is：Hardware monitoring signal list is previously stored in FPGA.
Include in the hardware monitoring signal list in CPU i.e. PCH each hardware device it is normal, do not break down when
Hardware monitoring signal standard signal, i.e., for different hardware devices have respectively corresponding hardware monitoring signal standard believe
Number, which can be a standard signal range.
The standard signal of hardware monitoring signal is each hardware device in normal work, and monitoring device detects hard
The value of part monitoring signal, when a certain hardware device breaks down, no matter it occurs that several failures or which kind of event
Barrier, the hardware monitoring signal that monitoring device detects necessarily are different from the hardware monitoring letter detected when the hardware device is normal
Number, when the hardware monitoring signal is different from its corresponding standard signal, show the corresponding hardware device of hardware monitoring signal
It breaks down, which is hardware fault signal.
Wherein, the fault type being likely to occur in FPGA without storage hardware device, it is only necessary to store each hardware device
The standard signal of the hardware monitoring signal of part.
Step S22, the hardware fault type of processor is determined according to hardware fault signal.
When FPGA determines to have hardware fault signal in received hardware monitoring signal, which is sent out
It send to hardware control, the hardware fault signal is analyzed and processed by hardware control.
When there is hardware fault signal in the hardware monitoring signal that FPGA determines received CPU and PCH, no matter this is hard
Part fault-signal is one or multiple, which is hard on hardware fault signal or PCH on CPU
One or more hardware fault signals separately or concurrently can be sent to hardware control by part fault-signal, without by its
He is not that the hardware monitoring signal of hardware fault signal is sent to hardware control.
Not only include the hardware monitoring of the hardware device of the failure that monitoring device detects in hardware fault signal
Signal further includes the mark of the corresponding hardware device of hardware monitoring signal, which can be hardware device title, can also
For number or other, as long as the mark can uniquely show the hardware device.
Each fault type that each hardware device being stored in hardware control on CPU and PCH is likely to occur
Corresponding hardware fault signal can also be stored with the troubleshooting scheme corresponding to each fault type.
When the hardware fault signal for receiving some hardware device, it is first determined the corresponding tool of hardware fault signal
The hardware device of body, searching the hardware fault signal corresponding to each fault type that the hardware device is likely to occur later is
It is no to have the signal consistent with the hardware fault signal detected, if so, then the fault type is that the hardware device is corresponding
Fault type.
After the fault type for determining specific some hardware device appearance, the corresponding troubleshooting side of the fault type is determined
Case is handled the failure according to the troubleshooting scheme.
Further, FPGA will monitor fault-signal when being sent to hardware control, can pass through I2C interface sends monitoring
Fault-signal.
Wherein, hardware control can be：BMC, or：Super IO.
Data processing method disclosed in the present embodiment obtains the processing of electronic equipment by the built-in FPGA of central processing unit
The hardware monitoring signal of device, processor include central processing unit, hardware fault signal are determined according to hardware monitoring signal, by hardware
Fault-signal is sent to hardware control, and hardware control is made to analyze and process hardware fault signal.This programme is in
Hardware fault signal is directly sent to hardware control by the built-in FPGA of central processor so that hardware control is only to hardware event
Barrier signal is analyzed and processed, and without being analyzed and processed to whole hardware monitoring information in processor, reduces hardware control
The data processing amount of device processed, while the data volume for being transmitted to hardware control is reduced, avoid the occupancy of Internet resources.
Present embodiment discloses a kind of electronic equipment, structure diagram as shown in figure 3, including：
Processor 31, FPGA32 and hardware control 33.
Processor 31 includes：Central processing unit 311, central processing unit 311 are built-in with FPGA32.
Further, can also include in processor 31：PCH312.
The built-in FPGA32 of central processing unit 311 obtains the hardware monitoring signal of processor 31, according to hardware monitoring signal
It determines hardware fault signal, hardware fault signal is sent to hardware control 33.
Hardware control 33 analyzes and processes hardware fault signal.
A field programmable gate array FPGA is integrated in the central processor CPU of electronic equipment, to the FPGA
It is programmed, the FPGA is made to have the function of to carry out fault diagnosis to hardware monitoring signal, so that by the FPGA inside CPU
The monitoring signal to break down in directly determining processor, and the monitoring signal of failure is only sent to hardware control,
Without whole monitoring signals is sent to hardware control.
Processor includes central processor CPU, can also be connected including south bridge PCH, PCH by DMI buses with CPU.
FPGA obtains the hardware monitoring signal of the processor in electronic equipment, not only includes：FPGA is obtained in electronic equipment
The hardware monitoring signal of CPU, further includes：FPGA obtains the hardware monitoring signal of PCH in electronic equipment, the hardware monitoring letter of PCH
The FPGA number being sent to by DMI buses in CPU.
Each hardware device on CPU and PCH is monitored, and monitoring signal is sent to FPGA in real time, by FPGA into
Row fault diagnosis.Specifically, can be that hardware monitoring signal is sent to FPGA in real time, or interval preset duration will be hard
Part monitoring signal is sent to FPGA.
Specifically, being monitored to each hardware device on CPU and PCH, can be specially：Only each hardware device is carried out
Monitoring, and monitoring information is directly sent to FPGA；Or：When being monitored to each hardware device, if each is hard
Part device corresponds to a monitoring device, while each monitoring device monitors, whether is additionally operable to the signal for judging to monitor
Normally, if so, not sending hardware monitoring signal, if judging the abnormal signal monitored, hardware monitoring signal is sent, it
Afterwards, the hardware monitoring signal is directly sent to hardware control by FPGA.
FPGA obtains the hardware monitoring signal of CPU and PCH, and the hardware monitoring signal of CPU and PCH is diagnosed, and determines
Whether there is hardware fault signal in all hardware monitoring signal received.
Specifically, can be：Hardware fault information list is previously stored in FPGA.
Include the hardware that each hardware device is likely to occur respectively in CPU and PCH in the hardware fault information list
A certain hardware device in fault-signal, i.e. CPU or PCH, such as：First hardware, the failure being likely to occur have it is several, when point
Not Chu Xian these types of failure when, the corresponding monitoring fault-signal of hardware monitoring signal that monitoring device detects, alternatively, the
When there are two or more failures simultaneously in one hardware, the corresponding monitoring of hardware monitoring signal that monitoring device detects is former
Hinder signal.
Wherein, the fault type being likely to occur in FPGA without storage hardware device, it is only necessary to store each hardware device
Part is for the monitoring fault-signal corresponding to different failures.
Furthermore it is also possible to it is：Hardware monitoring signal list is previously stored in FPGA.
Include in the hardware monitoring signal list in CPU i.e. PCH each hardware device it is normal, do not break down when
Hardware monitoring signal standard signal, i.e., for different hardware devices have respectively corresponding hardware monitoring signal standard believe
Number, which can be a standard signal range.
The standard signal of hardware monitoring signal is each hardware device in normal work, and monitoring device detects hard
The value of part monitoring signal, when a certain hardware device breaks down, no matter it occurs that several failures or which kind of event
Barrier, the hardware monitoring signal that monitoring device detects necessarily are different from the hardware monitoring letter detected when the hardware device is normal
Number, when the hardware monitoring signal is different from its corresponding standard signal, show the corresponding hardware device of hardware monitoring signal
It breaks down, which is hardware fault signal.
Wherein, the fault type being likely to occur in FPGA without storage hardware device, it is only necessary to store each hardware device
The standard signal of the hardware monitoring signal of part.
When FPGA determines to have hardware fault signal in received hardware monitoring signal, which is sent out
It send to hardware control, the hardware fault signal is analyzed and processed by hardware control.
When there is hardware fault signal in the hardware monitoring signal that FPGA determines received CPU and PCH, no matter this is hard
Part fault-signal is one or multiple, which is hard on hardware fault signal or PCH on CPU
One or more hardware fault signals separately or concurrently can be sent to hardware control by part fault-signal, without by its
He is not that the hardware monitoring signal of hardware fault signal is sent to hardware control.
Not only include the hardware monitoring of the hardware device of the failure that monitoring device detects in hardware fault signal
Signal further includes the mark of the corresponding hardware device of hardware monitoring signal, which can be hardware device title, can also
For number or other, as long as the mark can uniquely show the hardware device.
Each fault type that each hardware device being stored in hardware control on CPU and PCH is likely to occur
Corresponding hardware fault signal can also be stored with the troubleshooting scheme corresponding to each fault type.
When the hardware fault signal for receiving some hardware device, it is first determined the corresponding tool of hardware fault signal
The hardware device of body, searching the hardware fault signal corresponding to each fault type that the hardware device is likely to occur later is
It is no to have the signal consistent with the hardware fault signal detected, if so, then the fault type is that the hardware device is corresponding
Fault type.
After the fault type for determining specific some hardware device appearance, the corresponding troubleshooting side of the fault type is determined
Case is handled the failure according to the troubleshooting scheme.
Further, FPGA will monitor fault-signal when being sent to hardware control, can pass through I2C interface sends monitoring
Fault-signal.
Wherein, hardware control can be：BMC, or：Super IO.
Electronic equipment disclosed in the present embodiment obtains the processor of electronic equipment by the built-in FPGA of central processing unit
Hardware monitoring signal, processor include central processing unit, hardware fault signal are determined according to hardware monitoring signal, by hardware fault
Signal is sent to hardware control, and hardware control is made to analyze and process hardware fault signal.This programme passes through centre
Hardware fault signal is directly sent to hardware control by the built-in FPGA of reason device so that hardware control only believes hardware fault
It number is analyzed and processed, without being analyzed and processed to whole hardware monitoring information in processor, reduces hardware control
Data processing amount, while reduce the data volume for being transmitted to hardware control, avoid the occupancy of Internet resources.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so description is fairly simple, related part is said referring to method part
It is bright.
Professional further appreciates that, with reference to each exemplary unit of the embodiments described herein description
And algorithm steps, can be realized with the combination of electronic hardware, computer software or the two, in order to clearly demonstrate hardware and
The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These
Function is performed actually with hardware or software mode, specific application and design constraint depending on technical solution.Profession
Technical staff can realize described function to each specific application using distinct methods, but this realization should not
Think beyond the scope of this invention.
It can directly be held with reference to the step of method or algorithm that the embodiments described herein describes with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide range caused.
Claims (10)
1. a kind of data processing method, applied to electronic equipment, which is characterized in that including：
The built-in on-site programmable gate array FPGA of central processing unit obtains the hardware monitoring of the processor in the electronic equipment
Signal, the processor include：The central processing unit；
The built-in FPGA of the central processing unit determines hardware fault signal according to the hardware monitoring signal；
The hardware fault signal is sent to hardware control by the built-in FPGA of the central processing unit, makes the hardware controls
Device analyzes and processes the hardware fault signal.
2. according to the method described in claim 1, it is characterized in that, the built-in FPGA of the central processing unit is according to the hardware
Monitoring signal determines hardware fault signal, including：
The built-in FPGA of the central processing unit compares the hardware monitoring signal and preset hardware fault signal list
It is right, determine the signal for whether having with the Signal Matching in the hardware fault signal list in the hardware monitoring signal.
3. according to the method described in claim 1, it is characterized in that, the built-in FPGA of the central processing unit obtains the electronics
The hardware monitoring signal of the processor of equipment, including：
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the central processing unit of the electronic equipment；
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the south bridge of the electronic equipment.
4. according to the method described in claim 3, it is characterized in that, the built-in FPGA of the central processing unit is former by the hardware
Barrier signal is sent to hardware control, including：
The built-in FPGA of the central processing unit is by the hardware fault signal of the central processing unit and/or the hardware of the south bridge
Fault-signal is sent to hardware control by the bus interface of the central processing unit.
5. a kind of data processing method, applied to electronic equipment, which is characterized in that including：
The hardware fault signal of the processor of the electronic equipment sent by the built-in FPGA of central processing unit is received, it is described
Hardware fault signal is to be analyzed according to the hardware monitoring signal of the processor of the electronic equipment, the processor
Including：The central processing unit；
The hardware fault type of the processor is determined according to the hardware fault signal.
6. according to the method described in claim 5, it is characterized in that, described receive is sent by the built-in FPGA of central processing unit
The electronic equipment processor hardware fault signal, including：
Receive the hardware monitoring signal of central processing unit sent by the built-in FPGA of central processing unit；
Receive the hardware monitoring signal of south bridge sent by the built-in FPGA of central processing unit.
7. according to the method described in claim 5, it is characterized in that, described receive is sent by the built-in FPGA of central processing unit
The electronic equipment processor hardware fault signal, including：
It receives and is set by the built-in FPGA of central processing unit by the electronics that the bus interface of the central processing unit is sent
The hardware fault signal of standby processor.
8. a kind of electronic equipment, which is characterized in that including：Processor, on-site programmable gate array FPGA and hardware control,
In：
The processor includes：Central processing unit, the central processing unit are built-in with FPGA；
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the processor, according to the hardware monitoring signal
It determines hardware fault signal, the hardware fault signal is sent to the hardware control；
The hardware control analyzes and processes the hardware fault signal.
9. electronic equipment according to claim 8, which is characterized in that described in the built-in FPGA of the central processing unit is obtained
The hardware monitoring signal of processor, including：
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the central processing unit of the electronic equipment；
The built-in FPGA of the central processing unit obtains the hardware monitoring signal of the south bridge of the electronic equipment.
10. electronic equipment according to claim 9, which is characterized in that the built-in FPGA of the central processing unit is by described in
Hardware fault signal is sent to hardware control, including：
The built-in FPGA of the central processing unit is by the hardware fault signal of the central processing unit and/or the hardware of the south bridge
Fault-signal is sent to hardware control by the bus interface of the central processing unit.
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Application publication date: 20180612 |